JPH061479B2 - Symbol string identification device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a symbol string identification device used in an information retrieval system, a pattern recognition system, a machine translation system and the like.

The symbol string identification device is a device that determines where the input data symbol string (text information) matches with which registered pattern symbol string (keyword etc.) in the file memory of the information retrieval system and where the text information content search is performed. It is indispensable to. A device that accepts the pattern code after pattern observation and feature extraction as the input data symbol string and stores the feature code string for each pattern category as the pattern symbol string is indispensable in the pattern recognition system. The one that accepts foreign language texts and stores words as pattern symbols is a dictionary necessary for machine translation systems.

(Prior Art) The most typical method for searching the contents of text information is to store a pattern symbol string that is a keyword in a memory, and data that is viewed from a window equal in length to the pattern symbol string each time a data symbol string is input as text. This is a method of comparing with the symbol string, outputting a match signal if they match, advancing the window by one character if they do not match, and moving to the next comparison. If the length of the pattern symbol string is 8 characters and the comparison time of the symbol string in units of 8 characters is 1 usec, the content search processing speed per pattern symbol string is 1 MB.
/ Sec.

The first problem when running the matching processing program of this method on a conventional computer is that the processing speed of content retrieval decreases with the number of pattern symbol strings, and the processing speed with 256 is 4 KB / s. Only.

The second problem is that, when comparing a data symbol string of 8 or 16 characters and a pattern symbol string, even if one of the characters has an error, the match signal cannot be permanently issued. In order to relieve the second problem, all the modified pattern symbol strings generated by one character typographical error or typo of addition or omission are stored in the memory, and every time the window looking through the data symbol string is shifted by one character, the data symbol string is shifted. And the pattern symbol string and the modified pattern symbol string are compared, the processing speed decreases in inverse proportion to the number of modified pattern symbol strings and the length of the symbol string.

When an 8-bit symbol code is used, the number of modified pattern symbol strings of the 8-character symbol string is 2 × 8 × 2 ⁸ or about 4000.
Therefore, the processing speed of 4 KB / s falls to 1 B / s.

The solutions proposed so far are divided into a method using an associative memory, a method using a cellular array, and a method using dynamic programming (DP).

The method using the associative memory or the cellular array is effective in solving the first problem, but has no effect on the second problem. The method using the state transition table does not contribute to solving the first problem, but is effective to some extent for solving the second problem. However, make a state transition table for that and RAM
Writing in requires fairly sophisticated intellectual work. Although the method using DP is effective in solving the second problem, it is not very effective in solving the first problem. A true solution must solve two problems and has never been discovered. Furthermore, no symbol string identification device has been proposed that can indicate which character has an error.

As described above, the conventional technique alone cannot achieve the speedup of the ambiguous text content search necessary for the knowledge information system to be developed in the future.

(Object of the Invention) An object of the present invention is to solve the above two problems in the content search of text information including a character error. More specifically, the first object of the present invention is to provide a technique that enables simultaneous comparison between an input data symbol string and a plurality of pattern symbol strings, and a second object is to provide pattern symbols of various lengths. Providing a technology that enables the registration of columns, and the third purpose is to make it possible to perform a search even if there are missing symbols, typos, or typographical errors in either the data symbol sequence or the pattern symbol sequence. The fourth purpose is to provide a technology that enables detection of how many characters of an error do not lead to a perfect match, and the fifth purpose is to provide a symbol string identification device as a one-chip LSI. The purpose is to provide a technology that enables the reduction of the number of input pins required to realize.

(Structure of the Invention) Therefore, according to the present invention, the following apparatus and control method can be obtained. That is, (1) external signal storage means for storing an external signal at an address specified by a symbol code forming a symbol string, and each bit line of the external signal storage means are provided corresponding to a specific symbol code. Delimiter signal holding means for holding an external signal read from each bit line, a plurality of internal signal holding means arranged in a matrix, each row corresponding to each bit line, and a general symbol code. First gate means which is controlled by an external signal read from each bit line and vertically connects the internal signal holding means of adjacent rows for each column; and an internal signal holding between adjacent columns which is controlled by the external signal. The second gate means for connecting the means diagonally or to the left and right in every three adjacent rows and the contents of the delimiter signal holding means control the internal signal to the internal signal holding means in the end column of each row. A symbol string identifying device, comprising: an internal signal supplying means for setting; and a switch means for outputting the contents of the internal signal holding means of a row designated by the contents of the delimiter distinguishingly for each column. , (2) External signal storage means for storing an external signal at an address designated by a symbol code that constitutes a symbol string, and the bit lines of the external signal storage means are provided corresponding to the specific symbol code. Delimiter signal holding means for holding an external signal read from each bit line, a plurality of internal signal holding means arranged in a matrix and each row corresponding to each bit line, and a general symbol code for each First gate means controlled by an external signal read from the bit line to couple the internal signal holding means of adjacent rows up and down for each column, and an internal signal between the adjacent columns controlled by the external signal. Second gate means for connecting the holding means diagonally or laterally in every three adjacent rows, and an internal signal which is controlled by the contents of the delimiter signal holding means and sets an internal signal in the internal signal holding means in the end column of each row. Supply means, switch means for outputting the contents of the internal signal holding means of the row specified by the contents of the delimiter holding means for each column, and output of the contents of the internal signal holding means for which row from the switch means. A delimiter signal position storage means for designating a key, and an identification code output means for selecting an address code of the delimiter signal position storage means by an output signal of the switch means; 3) In the symbol string identifying device, a specific symbol is added to the tail of each pattern symbol string to be registered, and after registration, the specific symbol is output from each bit line. A symbol string identification device characterized in that an external signal to be applied is set in the delimiter holding means, and (4) an arbitrary response output code is stored in the delimiter signal position storage means together with the delimiter signal position designation code. , A symbol string identification device characterized in that the output of the response output code is selected by the output signal of the switch means, and (5) all of the delimiter holding means specified in each column. A symbol string identifying device characterized in that when the logical sum of the contents of the internal signal holding means of a row indicates "1", it outputs to the outside which row the content of the internal signal holding means has become "1". (6) Similarly, only when the logical sum of the contents of the internal signal holding means of all the rows designated by the contents of the delimiter holding means in each column shows "1", the identification code of the matched pattern symbol string Or so It is a symbol string identification device, characterized in that outputs a response output code eclipsed not a connection with.

(Examples) Hereinafter, the present invention will be described in more detail with reference to the drawings.

FIG. 1 is an explanatory diagram of the first embodiment of the present invention. The symbol string identifying device shown in this figure is the left half of the external storage means 11.
0 and the delimiter signal holding means 120 at the center and the internal signal supplying means 125 are arranged in a matrix on the left half,
A first column register 131 and a second column register 132 connected by the first gate means 141 and the second gate means 142.
And an internal signal holding means 130 consisting of
It comprises a first switch 150 and a second switch 155 connected to 1 and 132.

The external signal storage means 110 comprises an address decoder 112, a word line 113 selected by the address decoder 112, and a read circuit 115 and a write circuit 116 connected to a large number of bit lines 114 intersecting the word line 113. The input terminal 111 is a part that receives a symbol code that is a component of a data symbol string.

The pattern symbol string registered in the external signal storage means 110 is stored downward from the uppermost bit line at a rate of one symbol per bit line. To register the i-th symbol in the pattern symbol string, the i-th bit line "1" that intersects the word line designated by the symbol code may be written.

For example, if the pattern symbol string is ABCD *, the first bit line is the address designated by the code of the symbol A (word line 1
From the position marked with a circle only when 13) is selected
"1" is output and "0" is output for other symbol codes.

Similarly, the second, third, fourth, and fifth bit lines 1
14 is for each code of the symbols B, C, D, *
Output "1" and "0" for other symbols. The output signal "1" or "0" output from each bit line at this time is defined as an external signal to distinguish it from the internal signal transmitted through the registers 131 and 132 on the right side. Therefore, the external signal storage means 110 stores the pattern symbol string ABCD * by the above method.

The symbol * is used as a specific symbol for separating a large number of registered pattern symbol strings.

After registration, give the initialization signal to the input terminal 165,
When a specific symbol (*) code is input to the input terminal 111, the signal that detects it advances to the timing control circuit 160 from the address decoder 112, and the external signal output from each bit line is delimited by the specific symbol (*) code. The signal is stored in the signal holding means 120. The external signal taken in by the delimiter signal holding means 120 controls the internal signal supply means 125,
The content (external signal) of the delimiter signal holding means 120 is "1"
In that case, the internal signal supply means 125 constantly generates the internal signal of "1".

The internal signal storage means 130 receives the shift clock pulse of the internal signal each time the symbol code is input from the timing control circuit 160, and when the first gate means 141 is in the ON state, shifts the internal signal from top to bottom. When the first gate means 141 is in the off state, the internal signal does not proceed downward and disappears from the register 131 of the first column. The gate means 143 in the second column fulfills exactly the same function as the first gate means 141.

It is an external signal output from each bit line of the external signal storage means that controls the ON / OFF of the first gate means 141 and 143. However, the internal signal supply means 12
Internal signal "1" generated by 5 is always one row below register 1
It is sent to 31 via the first gate means 141. For example, the delimiter signal holding means 120 connected to the fourth bit line 114 holds "1" and causes the internal signal supply means 125 to generate the internal signal "1". In FIG. 1, the internal signal "1" is constantly sent to the register 131 of the fifth column and the tenth column of the first column of the internal signal storage means 130.

When the data symbol string XYABCDE ... Is given from the input terminal 111 after such a state, the symbols A, B, C, D are given.
, The external signals of "1" are sequentially output from the first, second, third and fourth bit lines 114, respectively.
It is sent to the 1st, 2nd, 3rd, 4th lines. Thereby, the internal signal of the contents of the register 131 in the first column and the first row
"1" advances to the second, third, fourth and fifth lines of the register 131.
The register 131 in the first row always holds the internal signal "1". 1 unless the entered symbol is A
Since the external signal from the th bit line 114 is "0", the internal signal "1" does not proceed downward in the first column.

The second gate means 142 outputs the internal signal "1" of the register 131 in the first row to the register 132 in the third row in the second column in response to the internal signal "1" from the first bit line 114 for the symbol A.
Move to. First bit line 11 for symbols B and C
For the external signal of "0" from 4, the 1st row register 13
The internal signal "1" of 1 is moved to the registers 132 in the first and second rows of the second column.

The internal / external signal "1" transferred to the register 132 of the second column is moved downward by the input of the data symbol string matched with the pattern symbol string through the gate means 143 as in the first column.

The shift of the internal signal "1" from the register 132 in the first column to the second column occurs when there is a one-character difference between the data symbol sequence and the pattern symbol sequence. In this way, it is possible to remedy one character erroneous character (miss type) or erroneous character mixture by the register 132 in the second column.

That is, when the data symbol string ACD is input after the pattern symbol string ABCD * is registered, the internal signal "1" in the register 131 in the first column and the first row is changed to 1 by the input of the code of the symbol A. The process proceeds to both the register 131 in the second row of the column and the register 132 in the third row of the second column. The reason for this is that two kinds of symbols, that is, whether the symbol following A is B or not are expected. If the symbol next to A is C, the internal signal "1" that has proceeded to the register 132 in the second column and the third row advances to the fourth line, and the internal signal of the register 131 in the first column and the second row is the first column 3 It disappears without proceeding to the line. When the symbol D comes after C, the internal signal in the second column and the fourth row
"1" advances to the 5th line.

In this way, the dropout error of the symbol can be remedied by the register 132 in the second column.

If the data symbol string AXCD or AXBCD is input, the external signal for the symbol X is "0". Therefore, the internal signal "1" in the register 131 in the first column and the second row is Register 132 in the second and third rows of the second column
Proceed to and the register 131 in the first column and the third row does not proceed.
If the symbol next to X is B, the register 132 in the second column and the third row
The internal signal "1" that has proceeded to step 1 disappears, and instead, the internal signal "1" of the register 132 in the second column and the second row changes to the register 1 in the third row.
Proceed to 32. If the symbol next to X is C, the internal signal "1" in the register 132 in the second column and the second row disappears, and instead the internal signal "1" in the register 132 in the second column and the third row is replaced. Goes to the register 132 in the fourth row.

The first switch 150 is a mode signal designated from the outside.
By (Strict / lerror free), register 131 of the first column
Can be output, or the contents of the register 131 in the second column can be output. That is, in the Strict mode, whether or not the internal signal "1" has reached the register 131 connected to the delimiter signal holding means 120 containing "1" is determined each time each symbol of the data symbol string is input. To be done.
On the other hand, in the 1 error free mode, the register 1 connected to the delimiter signal holding means 120 containing "1" is included.
Whether or not the internal signal "1" has reached 32 is determined each time each symbol is input.

The second switch 155 has an output terminal 157 for serially scanning and outputting the output signal of the first switch 150 and an output terminal 159 for outputting whether or not any one of the first switches 150 has become "1". . A multiplexer 155 is used in a connection portion between all the first switches 150 and the output terminal 157, and it is selected by an address code input from the terminal 156. First of all
An OR gate 158 is used between the switch 150 and the output terminal 159 to generate a logical sum of the output signals of all the first switches 150. Details are explained in FIG.

In the case of FIG. 1, the matrix of the internal signal holding means 130 has two columns, but if the matrix is increased to three columns or four columns, a two-character error or a three-character error is remedied. First switch 15
If a multiplexer is also used for 0, it is possible to identify how many character errors the input data symbol string has matched with which pattern symbol string.

The pattern symbol string is registered in the symbol string identification device shown in FIG. 1 by writing signal shift register 117 and writing circuit 116 at the left end.
Is performed using. It is assumed that a large number of registered pattern symbol strings are once prepared in an external buffer memory.

Before registration, the external signal storage means 110 is set to the write mode, and the stored contents of all bit lines 114 are cleared. Further, the write signal shift register 117
Write command signal from the input terminal 118
Suppose "1" is set.

It is assumed that the write command signal "1" is shifted downward along the write signal shift register 117 by a shift clock pulse coming from the timing control circuit 160 each time a symbol code is input from the input terminal 111.

At the time of registration, each symbol code of the pattern symbol string prepared in the external buffer memory is sequentially input from the input terminal 111 to the external signal storage means 110, and the word line 113 selected by each symbol code and the write command signal "1". Of the external signal at the intersection with the bit line 114 connected to the register 117 with
"1" is written. By shifting the write command signal "1" downward by 1 bit for each symbol code, the 1-bit line 11
A pattern symbol string is written in sequence from top to bottom for one symbol code per 4.

When the external signal storage means 110 is set to the read mode after the above registration is completed, there is a match between the symbol code and the registered one from all bit lines 114 for each symbol mode of the input data symbol string. External signals indicating whether or not they are output are output all at once. When the input data symbol string includes the same symbol string as the registered pattern symbol string,
The internal signal "1" should have reached the register (internal signal holding means) 131 or 132 in the row corresponding to the delimiter signal holding means 120 including "1", which is the first switch 150 as a match signal. Is output through.

Now, the number of 8-bit lines 113 for the symbol code is 256. When using a 1 Mbit memory chip, the bit line 11
The number of 4 becomes 4096. 1 for a pattern symbol string with a length of 5 characters
It can be seen that about 800 chips can be registered on a chip, and 256 even if it is 8 characters long.

FIG. 2 shows a method of registering a pattern symbol string. For the purpose of registering pattern symbol strings of various lengths without gaps, at the time of registration, it is required to add a specific symbol (in this case *) after each pattern symbol string. This specific symbol is also called a delimiter symbol, and may be * or blank.

FIG. 2 (a) shows that the 4-character symbol string ABCD should be registered by changing it to the 5-character pattern symbol string ABCD *.
(b) shows that the 5-character symbol string DEBAC should be registered by changing it to the 6-character pattern symbol string DEBAC *.

FIG. 2 (c) shows a part of a plurality of pattern symbol strings registered in the external signal storage means of FIG. As a result, long symbols can be created by simply separating a large number of symbol strings with the specific symbol *.
It becomes possible to register as one pattern symbol string.

After registration, the external signal output from each bit line 114 when the specific symbol * is input is called a delimiter signal, and is set in the delimiter signal holding means by the operation of the timing control means 160, and the internal signal supply means 125. Used for control.

FIG. 3 is a detailed explanatory view of a part of FIG. 1, in which the first column register 131 and the second column register 132 of the internal signal holding means 130 and the first gate means 14 for connecting them.
1, 143 and the second gate means 142 are mainly shown.

In particular, the first gate means 141A, 141B and 143A, 1
43B and how the second gate means 142A, 142B are implemented.

First gate means 141A, 141B and 143A, 143
B determines whether or not to transmit the internal signal "1" from the top to the bottom, and performs AND gates 341A and 343A and OR gates 341B and 343 so as to take in the internal signal "1".
It is composed of B. AND gate 341A, 343A
Is an i-th row register of each column (for example, 131 when the external signal coming from the leftmost external signal reading circuit 115A is "1").
A, 132A) plays a role of advancing the internal signal of (A, 132A) to the register (for example, 131B, 132B) of the (i + 1) th row.

The second gate means 142A and 142B set the internal signal "1" to 1
It is a part that determines how to allocate from the second-row register to the second-row register, and is composed of AND gates 342A and 342B.

When the external signal is "0", the AND gate 342A outputs the internal signal of the i-th row register (eg 131B) to the i-th row and (i + 1) th row register (eg 132B and 1) of the second column.
32C) and AND gate 342B.
Plays a role of distributing the internal signal of the i-th row register of the first column (eg 131A) to the register of the (i + 2) th row of the second column (eg 132C) when the external signal is "1".

Let S ij (t) be the internal signal of the register of the i-th row and the j-th column at time t, and let S _io be the internal signal that the delimiter signal holding means 120 of the i-th row can generate, S _i1 (t) = S _{(i-1) 0} + x _i-1 (t) * S _{(i-1) 1} (t _-1 ) S _i2 (t) = x _i-1 (t) * S _{(i-2) 2} ( t _-1 ) + x _i-2 (t) * S _{(i-2) 1} (t _-1 ) + x _i-1 (t) * S _(i-1) (t _-1 ) + x _i
It is represented by (t) * S _i1 (t _-1 ). Here, the * mark shows the logical product, and the + mark shows the operation of the logical sum.

In FIG. 1 and FIG. 3, the internal signal holding means 13 on and after the third column
Although 0 is not shown, if the third and subsequent columns can be introduced, S _ij (t) will be as follows.

S _ij (t) ＝ x _i-1 (t) * S _{(i-1) j} (t _-1 ) + x _i-2 (t) * S _{(i-2) (j-1)} (t _-1 ) + x _i-1 (t) * S
_{(i-1) (j-1)} (t _-1 ) + x _i (t) * S _{i (j-1)} (t _-1 ) Here, j2 and i2. Further, S ₁₁ (t) = “L” and S _1j (t) = x ₁ (t) * S _{1 (j-1)} (t ₋₁ ), _{j 2} .

As the number of columns increases, it is possible to increase the number of character errors (missing characters, typographical errors, typographical errors) per pattern symbol string delimited by a specific symbol. Then, the (j + ₁ ) -th column indicates the presence or absence of matching when there are j character errors.

FIG. 4 is an explanatory diagram of a match signal output method. (a) shows an example of a pattern symbol string stored in order from the first bit of the external signal storage means 110. (b) is 1 of the internal signal holding means 130 corresponding to the application of the external signal of "0" output from each bit line 114 for the space symbol after registration.
The contents of the registers in the second and second columns are shown in order from the first row to the 22nd row. (c) shows the contents of the delimiter signal holding means 120. The delimiter signal is an internal signal
It is used to generate "1", and as shown in (b), it holds the internal signal "1" in the register of the corresponding row. However, 1 in (b)
Only "1" in the line is unconditionally set regardless of the delimiter signal holding means 120. Figure 4 (d) shows the first
Shows the signal output by the switch 150 of, and 0 always outputs "0", and? Is the match signal "1" or
Indicates "0". FIG. 4 (e) shows the state after the data symbol string ABCD is input to the first switch 150 in the perfect match mode, and reflects the contents of the register 131 in the first column, and only the fourth line becomes "1". ing. This indicates that there is a perfect match between the data symbol string and the pattern symbol string ABCD. FIG. 4 (f) shows the state of the first switch 150 after the data symbol string DEAC is input in the error permissible mode, reflecting the contents of the register 132 in the second column, and only the 10th row is "1". It has become. This indicates that the data symbol string was in agreement with the symbol string in which B in the pattern symbol string DEBAC was dropped. A more detailed description of the switch means that makes this possible is provided below.

FIG. 5 shows the contents of the circuit of the first switch 150. The contents of the circuit are the multiplexer 500 and the AND gate 540, and the multiplexer 500 at j2 is 2
It consists of two AND gates 510 and 520 and an OR gate 530, and outputs the contents of the first column register 131 when the mode signal given from the terminal 151 is "1", and outputs the contents of the second column register 132 when it is "0". The output of the multiplexer 500 is the contents of the delimiter signal holding means 120.
Only when it is "1", the content of either one of the two registers 131 and 132 of the corresponding row is output from the terminal 550.

FIG. 6 shows an output circuit of the identification result by the switch means. FIG. 6 (a) shows the same output circuit as that shown in FIG. 1, and outputs the logical sum of the output signals of all the first switches 150 and the multiplexer 155 that serially outputs the output signal of the first switch 150. Output OR gate 158
And consists of.

Only when the match signal “1” is detected from the OR gate 158, the output signals of all the first switches 150 are serially output. A considerably faster multiplexer 155 is needed to reduce the serial output time. Further, the external system is required to check which pattern symbol string each part of the data symbol string matches.

In FIG. 6 (b), a plurality of multiplexers 155 are used to convert the output signals of many first switches 150 into a plurality of output terminals
7'shows the case of serial output. As a result, the output time of the output signals of all the first switches 150 output when "1" is detected from the OR gate 158 is greatly reduced. For example, when the number of the first switches 150 is 4096, and the number of the output terminals 157 'is set to 8, each terminal is reduced to the share of 512 of the first switches 150. Even if the switching time of the multiplexer 155 is set to 50 nsec, the output time still reaches 25.6 μsec. The switch means described in claim (1) of the present invention includes up to FIGS. 6 (a) and 6 (b).

FIG. 6 (c) is intended to shorten the output time of the output signal of the switch means 150 by the delimiter signal position storage means 600 and the identification code output means 620.

The delimiter signal position storage means 600 is the address counter 6
The row in which the delimiter signal is generated is stored in binary code in order from address 0 using 10. The first bit 601 of the storage means 600 stores information for resetting the counter 610 at an address equal to the number of registered pattern symbol strings. For example, when the number of registrations is 2, the reset signal
Suppose "1" is written.

When two pattern symbol strings of ABCD and DEBAC are registered, the specific symbol is the fifth line (01) as shown in FIG. 4 (c).
00) and the 11th line (1010), the delimiter signal position storage means 600 sets 00100 at address 0 and 1 at address 1.
You will store 1010. Then, each time each character of the data symbol string is input, a counter 610 that counts the pulses output by the timing control means 160 specifies access to addresses 0 and 1 to the storage means 600.

Second bit 602 of storage means 600, third bit 60
The outputs of the 3rd and 4th bits 604 and the 5th bit (605) control the switches of the multiplexer 155, and the output signal of the switch means 150 in the 5th row is first output from the first switch 150 in the 10th row. The signal is output from the output terminal 157. That is, when "1" is detected from the OR gate 158, the output signals of all the first switches 150 are decoded only by accessing the storage means 600 twice. Of course, the number of accesses increases with the number of registered pattern symbol strings.

The identification code output means 620, when the match signal of "1" is output from the output terminal 157, the counter 610 at that time
The content of is presented to the outside from the output terminal 625 as an identification code. The identification code of the previously matched pattern symbol string is held until the next match signal comes. The reset signal output from the first bit 601 of the storage means 600 is also fed back to the timing control means 160, and the number of pulses given to the counter 610 is controlled from there.

FIG. 7 shows another embodiment of the present invention, which is the same as FIG. 1 except for the output circuit. That is, in addition to the first switch 150 (FIG. 5) and the second switch, the multiplexer 155 (FIG. 6a), an output circuit (delimiter signal position storage means 600 and identification code output means 620 is added. 6 c) is used, which is a difference from FIG.
As a result, the output time of the identification code when a large number of pattern symbol strings of arbitrary length are registered is greatly reduced.

FIG. 8 is an explanatory diagram of an identification result output circuit obtained by improving FIG. 6 (c).

The difference from FIG. 6 (c) is that the delimiter signal position storage means 80
0 is not only the generation position code of the delimiter signal, but the response output code associated with the pattern symbol string is stored in correspondence therewith, and instead of the identification code of the registration number of the pattern symbol string, The output means 820 for sending the response output code is used.

The response output code is a symbol code associated with each pattern symbol string or a file memory address of associated data. For example, if it is desired to output the sentence "first four letters of the alphabet" to the pattern symbol string ABCD, the address (for example, 101010) of the external file memory storing the sentence becomes the response output code. A ROM that outputs Kana and Japanese translations that have the same meaning for Kana characters and English word pattern symbol strings when performing Kana-Kanji conversion or conversion of English words into Japanese.
The address code of (fixed memory) corresponds to the response output code. When the pattern symbol string is an instruction word, the storage address of the microprogram that executes it is the response output.

In order to output such a response output code, the output means 820 outputs a portion of the response output code in the read output signal of the delimiter signal position storage means 800 according to the match signal output from the second switch (multiplexer) 155. Take in.

The delimiter signal position storage unit 800 increments the address counter that counts a specific symbol *, which divides a large number of pattern symbol strings registered at the time of writing, by 1 bit,
A delimiter signal position code equal to the length of each pattern symbol string is stored, and a response output code is also stored at the same address.

At the time of reading, when the OR gate 158 outputs a match signal of "1", the timing control circuit 160 outputs a pulse for address increment to the address counter 610. As a result, the delimiter signal position storage means 800 is sequentially scanned from address 0 to (registered symbol string number-1). In the example of FIG. 8, the number of registered symbol strings is 2, and addresses 0 and 1 are accessed. When the first bit 801 of the storage device 800 is "1", the address counter 610 is reset, and the pulse sent from the timing control circuit 160 to the address counter 610 is also prohibited by the "1" of the first bit 801. It

The second bit 802 to the fifth bit 805 at the address (i-1) of the delimiter signal position storage means 800 is a binary code of the number of characters from the beginning to the i-th specific symbol appearance in a large number of registered pattern symbol strings. It is stored and used for switch selection of the second switch (multiplexer) 155. On the other hand, 6th bit 806 to 11th bit 8
Up to 11, the response output code related to the i-th of the registered pattern symbol string is stored and sent to the output means 820.

For example, when ABCD is included in the data symbol string, the first switch 150 in the fifth row outputs "1". When a match signal of "1" is output from the output terminal 159 when the last symbol D is applied, the address counter 610 sequentially specifies access to addresses 0 and 1 of the delimiter signal position storage means 800, and as a result, the multiplexer 155. Works to output the output of the first switch 150 on the 5th and 11th lines in sequence.
"1" and "0" are output serially. When "1" is output from the output terminal 157, the output means 820 takes in the response output code from the 6th bit 806 to the 11th bit 811 of the 0th address of the delimiter signal position storage means 800, and outputs "0". Do not accept the response output code at address 1 when

If such delimiter signal position storage means 800 and response output means 820 are provided instead of the delimiter signal position storage means 600 and response output means 620 of FIG. 7, respectively.
In the figure, for each part of the data symbol string, a detection signal of a pattern symbol string corresponding to the part is output from the terminal 159, and a response output code related to the pattern symbol string is output from the terminal 825.

(Effect of the Invention) In the symbol string identification device of the present invention shown in FIGS. 1 and 7, the read / write cycle time of the external signal storage means 110 is 1
If it is μsec, the data symbol string can be accepted at the speed up to 1MB / sec. Then, the first switch 150 outputs the presence / absence of matching between each part of the data symbol string and the pattern symbol string. It is possible to distinguish and detect a perfect match with the pattern symbol string and a match that allows a one-character error. Considering that in the prior art, the matching processing speed with 256 pattern symbol strings was 4 KB / sec, and the matching processing speed when 1 character error was allowed was 1 B / sec, the matching processing speed according to the present invention was 1 character. 1MB / when error is allowed
Since it remains sec, it can be seen that the improvement in processing speed reaches 1 million times.

Moreover, in the symbol string identification device of the present invention, even if the lengths of a large number of pattern symbol strings to be registered are different, registration is easy, and the start position of the pattern symbol string included in the data symbol string is It is possible to identify which pattern symbol string each part of the data symbol string matches (identification of Unanchor mode) without adding a delimiter symbol indicating.

The identification result is not only the information indicating that any pattern symbol string has been matched, but also the identification (registration number) code of the matched pattern symbol string and the response output code related to the matched pattern symbol string. Will also be output. The response output code is output only when there is a match with any pattern symbol string in the data symbol string, so the output time is several μ.
The total processing speed does not decrease even if it reaches from sec to several tens of microseconds.

Moreover, the semiconductor LS with such an improved symbol string identification device
It will be realized with one chip by I technology. The number of input / output terminals is only 20 pins. It is not too far away that the storage capacity of the external signal storage means exceeds 1 Mb. 1 Mb can accommodate 4096 8-bit symbol codes. At this time, the internal signal holding means is the number of bit lines 114, for example, 4096,
2 times the storage capacity of the delimiter signal position storage means 800, and the storage capacity of the delimiter signal position storage means 800 is 256.
16 times as large as the above, so it does not occupy such a large chip size. 25 patterns of 8-character patterns in one chip
6 can be registered, and the parallel matching of data symbol strings and 256 pattern symbol strings can be advanced at a processing speed of 1 MB / sec, which greatly accelerates the speed of content retrieval of text information. become.

As described above, according to the present invention, in the conventional technique, it is difficult to speed up the collation with a large number of pattern symbol strings under the condition that a single character error is allowed. I know you can. The technique of the present invention exerts a particularly great effect when applied to an information retrieval system, a pattern recognition system, a machine translation system, or the like.

In the embodiment of the present invention, the external signal storage means 11
It was explained that 0 is realized by RAM, but ROM and PRO
It may be realized by M or EEPROM, and the registers 131 and 132 of the internal signal holding means 130 may be realized not only by flip-flops but also by simple charge holding elements (capacitors). Is not limited. Further, the serial selection of the writing circuit 116 at the left end in FIGS. 1 and 7 is described as being achieved by the shift register 117, but it can be achieved by using an address decoder. It does not limit the scope of the invention.

[Brief description of drawings]

FIG. 1 is an explanatory view of an embodiment of the present invention, FIGS. 2 (a) to (c) are explanatory views of a method for registering a pattern symbol string, FIG. 3 is a partial view of FIG. 1, and FIG. a) to (f) are explanatory diagrams of the output method of the match signal, FIG. 5 is an explanatory diagram of the first switch circuit, and FIG. 6 (a) to
(c) is an output circuit diagram of the discrimination result in the switch means, FIG. 7 is a diagram showing a second embodiment of the present invention, and FIG. 8 is FIG.
It is an output circuit diagram of the identification result which improved (c). In the above drawings, 110 ... External signal storage means, 111 ... Symbol code input terminal, 112 ... Address decoder, 113 ... Word line, 114
...... Bit line, 115 …… Read circuit, 116 …… Write circuit, 117 …… Write signal shift register, 118 …… Input terminal, 120 …… Delimiter signal holding means, 125 …… Internal signal supply means, 130 …… Internal signal holding means (register array), 131 ... First column register, 132 ... Second column register, 141,143 ... First gate means, 142 ... Second
Gate means, 150 ... First switch, 155, 155 '... Second switch or multiplexer, 151 ... Mode signal terminal, 156 ... Address code input terminal, 157, 157' ...
… Mux output terminal, 158 …… Match signal OR gate, 159 …… OR gate output terminal, 160 …… Timing control circuit, 165 …… Initialization signal input terminal, 3
41A, 343A, 324B, 540 ... AND gate, 342A, 510 ...
... AND gate with negative signal, 341B, 343B, 530 ... OR gate 600, 800 ... Delimiter signal holding means, 601, 6
02,603,604,605 ... 1st bit, 2nd bit, 3rd bit, 4th bit and 5th bit, 610 ... Address counter, 620 ... Identification code output means, 625 ... Identification code output terminal , 820 ... Response output code output means, 825 ...
… Response output code output terminal.

Claims (6)

[Claims] 1. An external signal storage means for storing an external signal at an address designated by a symbol code forming a symbol string, and an external signal storage means provided corresponding to each bit line of the external signal storage means for a specific symbol code. Delimiter signal holding means for holding an external signal read from each bit line, a plurality of internal signal holding means arranged in a matrix, each row corresponding to each bit line, and a general symbol code. First gate means which is controlled by an external signal read from each bit line and vertically connects the internal signal holding means of adjacent rows for each column; and an internal signal holding between adjacent columns which is controlled by the external signal. The second gate means for connecting the means diagonally or to the left and right in every three adjacent rows and the contents of the delimiter signal holding means control the internal signal to the internal signal holding means in the end column of each row. An internal signal supplying means for constant, that symbol string identification device, characterized in that a switching means for outputting the distinction for each column the contents of the internal signal holding means of the row designated by the contents of the delimiter holding means. 2. An external signal storage means for storing an external signal at an address designated by a symbol code forming a symbol string, and an external signal storage means provided corresponding to each bit line of the external signal storage means for a specific symbol code. Delimiter signal holding means for holding an external signal read from each bit line, a plurality of internal signal holding means arranged in a matrix, each row corresponding to each bit line, and a general symbol code. First gate means which is controlled by an external signal read from each bit line and vertically connects the internal signal holding means of adjacent rows for each column; and an internal signal holding between adjacent columns which is controlled by the external signal. The second gate means for connecting the means diagonally or to the left and right in every three adjacent rows and the contents of the delimiter signal holding means control the internal signal to the internal signal holding means in the end column of each row. Internal signal supply means for determining the internal signal holding means of the row specified by the contents of the delimiter holding means, and a switch means for distinguishing and outputting the contents of the internal signal holding means of the row for each column. Delimiter symbol position storage means for specifying whether to output the contents,
An identification code output device for selecting an address code of the delimiter signal position storage device according to an output signal of the switch device. 3. An external signal storage means for storing an external signal at an address designated by a symbol code forming a symbol string, and an external signal storage means provided corresponding to each bit line of the external signal storage means for a specific symbol code. Delimiter signal holding means for holding an external signal read from each bit line, a plurality of internal signal holding means arranged in a matrix, each row corresponding to each bit line, and a general symbol code. First gate means which is controlled by an external signal read from each bit line and vertically connects the internal signal holding means of adjacent rows for each column; and an internal signal holding between adjacent columns which is controlled by the external signal. The second gate means for connecting the means diagonally or to the left and right in every three adjacent rows and the contents of the delimiter signal holding means control the internal signal to the internal signal holding means in the end column of each row. A symbol string identification device having an internal signal supply means for setting and a switch means for separately outputting the contents of the internal signal holding means of the row designated by the contents of the delimiter holding means for each column, which is registered. A symbol string identification device, wherein a specific symbol is added to the tail of each pattern symbol string, and after registration, an external signal output from each bit line for the specific symbol is set in the delimiter holding means. 4. An external signal storage means for storing an external signal at an address designated by a symbol code forming a symbol string, and an external signal storage means provided corresponding to each bit line of the external signal storage means for a specific symbol code. Delimiter signal holding means for holding an external signal read from each bit line, a plurality of internal signal holding means arranged in a matrix, each row corresponding to each bit line, and a general symbol code. First gate means which is controlled by an external signal read from each bit line and vertically connects the internal signal holding means of adjacent rows for each column; and an internal signal holding between adjacent columns which is controlled by the external signal. The second gate means for connecting the means diagonally or to the left and right in every three adjacent rows and the contents of the delimiter signal holding means control the internal signal to the internal signal holding means in the end column of each row. A delimiter signal, which is a symbol string identifying device including an internal signal supply means for setting a predetermined value, and a switch means for distinguishing and outputting the contents of the internal signal holding means of a row designated by the contents of the delimiter holding means for each column. A symbol string identifying device characterized in that an arbitrary response output code is stored together with a delimiter signal position designation code in the position storage means, and the output of the response output code is selected by the output signal of the switch means. 5. An external signal storage means for storing an external signal at an address designated by a symbol code forming a symbol string, and an external signal storage means provided corresponding to each bit line of the external signal storage means for a specific symbol code. Delimiter signal holding means for holding an external signal read from each bit line, a plurality of internal signal holding means arranged in a matrix, each row corresponding to each bit line, and a general symbol code. First gate means which is controlled by an external signal read from each bit line and vertically connects the internal signal holding means of adjacent rows for each column; and an internal signal holding between adjacent columns which is controlled by the external signal. The second gate means for connecting the means diagonally or to the left and right in every three adjacent rows and the contents of the delimiter signal holding means control the internal signal to the internal signal holding means in the end column of each row. A symbol string identification device comprising: an internal signal supply means for determining the contents of the delimiter and a switch means for outputting the contents of the internal signal holding means of a row designated by the contents of the delimiter by distinguishing each column, When the logical sum of the contents of the internal signal holding means of all the lines designated by the contents of the delimiter holding means in 1 indicates "1", which row the contents of the internal signal holding means have become "1" is externally determined. A character string identification device characterized by outputting to. 6. An external signal storage means for storing an external signal at an address designated by a symbol code forming a symbol string, and an external signal storage means provided corresponding to each bit line of the external signal storage means for a specific symbol code. Delimiter signal holding means for holding an external signal read from each bit line, a plurality of internal signal holding means arranged in a matrix, each row corresponding to each bit line, and a general symbol code. First gate means which is controlled by an external signal read from each bit line and vertically connects the internal signal holding means of adjacent rows for each column; and an internal signal holding between adjacent columns which is controlled by the external signal. The second gate means for connecting the means diagonally or to the left and right in every three adjacent rows and the contents of the delimiter signal holding means control the internal signal to the internal signal holding means in the end column of each row. A symbol string identification device comprising: an internal signal supply means for determining the contents of the delimiter and a switch means for outputting the contents of the internal signal holding means of a row designated by the contents of the delimiter by distinguishing each column, Only when the logical sum of the contents of the internal signal holding means of all the lines designated by the contents of the delimiter holding means in 1 indicates "1", the identification code of the matched pattern symbol string or the related code is assigned. A symbol string identifying device which outputs a response output code.