JPH0614307B2 - Voltage stabilization circuit - Google Patents

Voltage stabilization circuit

Info

Publication number
JPH0614307B2
JPH0614307B2 JP17970184A JP17970184A JPH0614307B2 JP H0614307 B2 JPH0614307 B2 JP H0614307B2 JP 17970184 A JP17970184 A JP 17970184A JP 17970184 A JP17970184 A JP 17970184A JP H0614307 B2 JPH0614307 B2 JP H0614307B2
Authority
JP
Japan
Prior art keywords
transistor
circuit
output
emitter
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP17970184A
Other languages
Japanese (ja)
Other versions
JPS6158017A (en
Inventor
田中　　慎二
泰 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP17970184A priority Critical patent/JPH0614307B2/en
Publication of JPS6158017A publication Critical patent/JPS6158017A/en
Publication of JPH0614307B2 publication Critical patent/JPH0614307B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、任意の温度係数に設定可能で、かつ電源電圧
変動，負荷変動等にも安定な定電圧出力を得ることがで
きる電圧安定化回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage stabilizing circuit that can be set to an arbitrary temperature coefficient and that can obtain a constant voltage output that is stable even when power supply voltage changes, load changes and the like. .

従来例の構成とその問題点 従来のバンドギャップ方式の電圧安定化回路は、第１図
の回路図で示されるように、トランジスタQ1〜Q4，抵抗
R1〜R4より成る基準電圧部、トランジスタQ5、負荷抵抗
もしくは帰還抵抗のRLよりなる出力部、およびトランジ
スタQ3，Q6，Q7よりなる誤差増幅部で構成される。第１
図に示した従来例の回路は、基準電圧部の一部と誤差増
幅部の一部とに同一素子を流用するため、素子数が少な
く、消費電流が小さい等の長所があり、広く使用されて
いる。Configuration of Conventional Example and Problems Thereof A conventional bandgap type voltage stabilizing circuit includes transistors Q 1 to Q 4 and resistors as shown in the circuit diagram of FIG.
It is composed of a reference voltage section composed of R 1 to R 4 , a transistor Q 5 , an output section composed of RL of a load resistance or a feedback resistance, and an error amplification section composed of transistors Q 3 , Q 6 , and Q 7 . First
The circuit of the conventional example shown in the figure uses the same element for a part of the reference voltage section and a part of the error amplification section. ing.

第１図の回路の出力電圧は、次の式で示される。（ベ
ース電流無視，ＶBE1ＶBE3，Q1エミッタ面積／Q2エミ
ッタ面積＝0.5） 出力電圧の温度係数は式を温度Ｔで微分することによ
って得られ式で表わされる。The output voltage of the circuit of FIG. 1 is expressed by the following equation. (Ignoring base current, V BE1 V BE3 , Q 1 emitter area / Q 2 emitter area = 0.5) The temperature coefficient of the output voltage is obtained by differentiating the equation with the temperature T and is represented by the equation.

式の第１項，第２項は負の温度係数、第３項は正の温
度係数を持つので任意の温度係数の設定が可能である。 Since the first term and the second term of the equation have a negative temperature coefficient and the third term has a positive temperature coefficient, an arbitrary temperature coefficient can be set.

負帰還での開ループゲインは、トランジスタQ3の段が支
配的で、負荷抵抗２ＫΩ、Q3のエミッタ電流を１００μ
Ａ、トランジスタの電流増幅率を２００とすると５０〜
６０dB程度の値を持つ 出力電圧の負荷特性については、開ループ時の出力イン
ピーダンスの約開ループゲイン分の１となる。負荷特性
を上げるには、誤差増幅部のゲインを上げても効果が薄
い、むしろトランジスタQ7の動作電流を増やすと良い。The open loop gain in the negative feedback is dominated by the stage of the transistor Q 3 , and the load resistance is 2KΩ and the emitter current of Q 3 is 100μ.
A, 50 if the current amplification factor of the transistor is 200
Regarding the load characteristic of the output voltage having a value of about 60 dB, it is about 1 / the open loop gain of the output impedance in the open loop. In order to improve the load characteristics, increasing the gain of the error amplifying section has little effect, but rather the operating current of the transistor Q 7 should be increased.

電源電圧変動は、トランジスタQ6，Q7の電流ミラー対の
ミラー比のドリフトに起因して生じる。Supply voltage variation occurs due to drift of the mirror ratio of the current mirror pair of transistors Q 6, Q 7.

概して、負荷変動、電圧変動に対して安定で、良好な特
性を示す。一般に、出力インピーダンス数Ω、電源リッ
プル除去比約６０dB程度の特性を持っている。Generally, it shows stable characteristics against load fluctuations and voltage fluctuations, and shows good characteristics. Generally, the output impedance is several Ω and the power supply ripple rejection ratio is about 60 dB.

しかしながら、起動回路が必要である、位相補償用コン
デンサが必要である、ＰＮＰトランジスタが必要である
等の理由により、集積回路に作りこむ場合、チップ面積
の増大傾向がまぬがれない、という重欠点を有してい
た。However, there is a serious defect that the tendency of increasing the chip area is inevitable when it is built into an integrated circuit because of the necessity of a start-up circuit, the requirement of a phase compensation capacitor, the requirement of a PNP transistor, and the like. Was.

発明の目的 本発明は、上記バンドキャップ方式の電圧安定化回路の
欠点を排除すべくなされたものであり、位相補償用コン
デンサを用いなくても安定動作し、ＩＣ化した際のチッ
プサイズを小さくし得るを提供するものである。SUMMARY OF THE INVENTION The present invention has been made to eliminate the drawbacks of the band-cap type voltage stabilizing circuit described above. The present invention enables stable operation without using a phase compensation capacitor and reduces the chip size when integrated into an IC. It provides what you can do.

発明の構成 本発明は、共通接続部に一端を接続した第１，第２の抵
抗（Ｒ1，Ｒ2）と、コレクタに前記第１の抵抗（Ｒ1）
の他端を接続したダイオード手段用の第１のトランジス
タ（Ｑ1）と、ベース及びエミッタ回路を前記第１のト
ランジスタのベース及びエミッタと並列接続すると共
に、前記第２の抵抗（Ｒ2）の他端にコレクタを接続し
た第２のトランジスタ（Ｑ2）とによって構成され、異
なる電流密度で動作する電流ミラー対と、電源入力端子
（ＶCC）に一端を接続した抵抗負荷（Ｒ5）の他端にコ
レクタを結合し、前記エミッタ回路の共通接続点にエミ
ッタを接続すると共に、前記第２のトランジスタ
（Ｑ2）のコレクタにベースを接続した第３のトランジ
スタ（Ｑ3）と、コレクタに前記電源入力端子（Ｖcc）
が接続され、ベースに前記抵抗負荷の他端が結合される
と共に、エミッタに出力端子（ＶOUT）が接続された出
力用トランジスタ（Ｑ5）と、前記出力端子（ＶOUT）か
ら前記第１，第２の抵抗（Ｒ1，Ｒ2）の共通接続部に出
力信号を帰還する帰還回路とを備え、前記電流ミラー
対，前記第３のトランジスタ，前記出力用トランジスタ
（Ｑ5）及び前記帰還回路（Ｑ4，Ｑ4）が負帰還ループ
を構成することを特徴とした電圧安定化回路であり、こ
の構成により、開ループゲインが低く設定され、位相補
償用コンデンサを用いなくても回路が安定に動作し、Ｉ
Ｃ化した際のチップサイズが小さくできる。Configuration of the Invention The present invention first, a second resistor (R 1, R 2), the first resistor in the collector having one end connected to the common connection portion (R 1)
A first transistor (Q 1 ) for diode means having the other end thereof connected, and a base and emitter circuit connected in parallel with the base and emitter of the first transistor, and the second resistor (R 2 ) A current mirror pair composed of a second transistor (Q 2 ) having a collector connected to the other end and operating at different current densities, and a resistive load (R 5 ) having one end connected to the power supply input terminal (V CC ). A collector is coupled to the other end, an emitter is connected to the common connection point of the emitter circuit, and a collector is connected to a third transistor (Q 3 ) whose base is connected to the collector of the second transistor (Q 2 ). The power source input terminal ( Vcc )
From the output terminal (V OUT ) to the output transistor (Q 5 ) having the base connected to the other end of the resistive load and the emitter connected to the output terminal (V OUT ). , A feedback circuit for feeding back the output signal to the common connection part of the second resistors (R 1 , R 2 ), the current mirror pair, the third transistor, the output transistor (Q 5 ) and the feedback circuit. The circuit (Q 4 , Q 4 ) is a voltage stabilizing circuit characterized by forming a negative feedback loop. With this configuration, the open loop gain is set low, and the circuit can be configured without using a phase compensation capacitor. Stable operation, I
The chip size when converted to C can be reduced.

実施例の説明 以下、第２図を参照しながら本発明の電圧安定化回路に
係る一実施例を説明する。Description of Embodiments An embodiment of the voltage stabilizing circuit of the present invention will be described below with reference to FIG.

第２図に示すように実施例の電圧安定化回路は、一端を
共通接続部に接続した抵抗Ｒ1，Ｒ2と、コレクタに抵抗
Ｒ1の他端を接続したダイオード手段用のトランジスタ
Ｑ1と、ベース及びエミッタ回路をトランジスタＱ1のベ
ース及びエミッタと並列接続したトランジスタＱ2とで
電流ミラー対を構成する。トランジスタＱ2は、コレク
タに抵抗Ｒ2の他端が接続され、エミッタに抵抗Ｒ3が接
続され、トランジスタＱ1とＱ2とが異なる電流密度で動
作し、抵抗Ｒ1，Ｒ2の共通接続部の動作電圧の誤差検出
を行う回路である。Voltage stabilizing circuit of embodiment, as shown in FIG. 2, a resistor R 1, R 2 connected to the common connection portion at one end, a transistor to Q 1 diode means connected to the other end of the resistor R 1 to the collector And a transistor Q 2 whose base and emitter circuits are connected in parallel with the base and emitter of the transistor Q 1 form a current mirror pair. In the transistor Q 2 , the other end of the resistor R 2 is connected to the collector, the resistor R 3 is connected to the emitter, the transistors Q 1 and Q 2 operate at different current densities, and the resistors R 1 and R 2 are commonly connected. It is a circuit that detects an error in the operating voltage of the unit.

そして、トランジスタＱ3は、エミッタがトランジスタ
Ｑ1，Ｑ2のエミッタ回路の共通接続点に接続され、ベー
スがトランジスタＱ2のコレクタに接続され、一端を電
源入力端子Ｖccに接続した抵抗負荷Ｒ5の他端にコレク
タが結合され、電流ミラー回路で検出した誤差電圧を増
幅する回路である。Then, the transistor Q 3 are an emitter connected to the common connection point of the emitter circuit of the transistor Q 1, Q 2, a base connected to the collector of the transistor Q 2, one end of the resistor connected to the power input terminal V cc load R A collector is coupled to the other end of 5 to amplify the error voltage detected by the current mirror circuit.

出力用トランジスタＱ5は、コレクタに電源入力端子Ｖ
ccが接続され、ベースに抵抗負荷Ｒ5の他端が結合され
ると共に、エミッタに出力端子ＶOUTが接続され、抵抗
負荷Ｒ5の端子間に出力される電圧をインピーダンス変
換して、出力端子ＶOUTに出力電圧を出力する。The output transistor Q 5 has a collector connected to the power input terminal V
cc is connected, the other end of the resistive load R 5 is coupled to the base, the output terminal V OUT is connected to the emitter, the voltage output between the terminals of the resistive load R 5 is impedance-converted, and the output terminal Output the output voltage to V OUT .

出力端子ＶOUTにベースを接続したエミッタホロワ用の
トランジスタＱ４と、トランジスタＱ4のエミッタと抵
抗Ｒ1，Ｒ2の共通接続部との間に接続された抵抗Ｒ4と
は帰還回路を成し、出力端子ＶOUTの出力電圧を電流ミ
ラー対に帰還する回路であると共に、抵抗Ｒ4の抵抗値
を可変して、出力電圧ＶOUTを任意の値に設定する回路
でもある。即ち、出力電圧ＶOUTを大きくしたい場合は
抵抗Ｒ4の抵抗値を大きくし、出力電圧ＶOUTを最低電位
に設定したい場合は抵抗Ｒ1，Ｒ2の共通接続部を出力端
子ＶOUTに直結すればよい。A transistor Q 4 for emitter follower whose base is connected to the output terminal V OUT, forms a feedback circuit and the resistor R 4, which are connected between a common connection of the emitter and the resistance of the transistor Q 4 R 1, R 2 , Is a circuit for feeding back the output voltage of the output terminal V OUT to the current mirror pair, and is also a circuit for varying the resistance value of the resistor R 4 to set the output voltage V OUT to an arbitrary value. That is, when it is desired to increase the output voltage V OUT , the resistance value of the resistor R 4 is increased, and when it is desired to set the output voltage V OUT to the lowest potential, the common connection portion of the resistors R 1 and R 2 is directly connected to the output terminal V OUT . do it.

そして、この電圧安定化回路は、電流ミラー対Ｑ1，
Ｑ2、トランジスタＱ3、出力用トランジスタＱ5及び帰
還回路（Ｑ4，Ｒ4）が負帰還ループを構成するように回
路構成する。Then, this voltage stabilizing circuit includes a current mirror pair Q 1 ,
The circuit configuration is such that Q 2 , the transistor Q 3 , the output transistor Q 5, and the feedback circuit (Q 4 , R 4 ) form a negative feedback loop.

従って、第２図の実施例は、第１図の従来例とトランジ
スタＱ3のバイアス電流供給を能動負荷で行うか抵抗R1
で行うかの点に相違がある。Thus, embodiments of the second figure, if the resistance R 1 of the bias current supply in the prior art and a transistor Q 3 of FIG. 1 performed in the active load
There is a difference in what to do in.

出力電圧をついては、第１図の回路同様、式式で表
わされる。The output voltage is expressed by the equation as in the circuit of FIG.

出力インピーダンスについては、以下の通り式で表わ
される。The output impedance is expressed by the following equation.

また、開ループゲインはトランジスタＱ3の段が支配的
となるので、以下の式の通り近似する 及び式より出力インピーダンスZoは式で表わせ
る。この回路で一般的な回路定数を選択すれば、 （１＋ｈFE）Ｚｂ≫ｒe5 Ｚｂ／ｒe3≫１ となるから、式は式の通りとなり、開 ループゲインを上げても出力インピーダンスは余り下が
らないことになる。むしろトランジスタQ3のバイアス電
流を増やす方が効果がある。 Since the open loop gain is dominated by the stage of the transistor Q 3 , it is approximated by the following equation. And the output impedance Z o can be expressed by the equation. If a general circuit constant is selected in this circuit, (1 + h FE ) Zb >> r e5 Zb / r e3 >> 1. Even if the loop gain is increased, the output impedance will not decrease so much. Rather, it is more effective to increase the bias current of the transistor Q 3 .

通常、出力インピーダンスをより下げるには、トランジ
スタQ3のコレクタ端のインピーダンスを下げて、開ルー
プゲインを落とさぬように、バッファを追加したり、出
力トランジスタQ5をダーリントン構成にして対策する。Usually, in order to further reduce the output impedance, the impedance at the collector end of the transistor Q 3 is lowered, and a buffer is added so that the open loop gain is not lowered, or the output transistor Q 5 is made into a Darlington configuration, and measures are taken.

ＩＣ１個程度の小規模な回路に供給する電圧安定化回路
は、数Ω程度の出力インピーダンスで動作する回路でも
十分な能力があり、第２図に示す実施例は次の点で有効
である。The voltage stabilizing circuit supplied to a small-scale circuit of about one IC has sufficient capability even for a circuit operating with an output impedance of about several Ω, and the embodiment shown in FIG. 2 is effective in the following points.

第２図の本実施例は、トランジスタＱ3の負荷として、
安定化した出力電圧を基にした定電流負荷（Ｑ4，Ｑ6，
Ｑ7）を用いないで、抵抗負荷Ｒ5としたことから、電流
入力端子Ｖccから抵抗負荷Ｒ5を介して出力用トランジ
スタＱ5のベースにバイアスを与えるため、出力用トラ
ンジスタＱ5が導通し、出力端子ＶOUTに出力電圧が出力
される。そして、その出力電圧が帰還回路（Ｑ4，
Ｒ4），電流ミラー対，並びにトランジスタＱ3を起動
し、電源入力端子Ｖccに電圧が投入されると同時に全て
の回路が機能する。従って、従来例のように、定電流負
荷（Ｑ7）を起動するための起動回路は必要としないの
である。In this embodiment shown in FIG. 2, the load of the transistor Q 3 is
Constant current load (Q 4 , Q 6 , based on the stabilized output voltage)
Since the resistance load R 5 is used without using Q 7 ), a bias is applied to the base of the output transistor Q 5 from the current input terminal V cc via the resistance load R 5 , so that the output transistor Q 5 becomes conductive. Then, the output voltage is output to the output terminal V OUT . The output voltage of the feedback circuit (Q 4 ,
R 4 ), the current mirror pair, and the transistor Q 3 are activated so that the voltage is applied to the power supply input terminal V cc and at the same time, all the circuits function. Therefore, unlike the conventional example, the starting circuit for starting the constant current load (Q 7 ) is not required.

更に、トランジスタＱ3の負荷を抵抗負荷Ｒ5とすると、
開ループゲインが小さくなり、位相補償用コンデンサを
用いなくても安定に動作し、位相補償用コンデンサを排
除することで、ＩＣ化した時のチップサイズが小さくな
ることを可能にするだけでなく、高域周波数の負荷変動
を生じても安定な出力電圧が得られる。Further, if the load of the transistor Q 3 is a resistive load R 5 ,
The open loop gain becomes small, the stable operation is achieved without using the phase compensating capacitor, and by eliminating the phase compensating capacitor, it is possible to reduce the chip size when integrated into an IC. A stable output voltage can be obtained even if load fluctuations occur in the high frequency range.

なお、トランジスタＱ4と抵抗Ｒ4とで構成される帰還回
路は、出力電圧ＶOUTの設定値に応じて適宜に変更さ
れ、抵抗Ｒ4は必ずしも必要としない。The feedback circuit composed of the transistor Q 4 and the resistor R 4 is appropriately changed according to the set value of the output voltage V OUT , and the resistor R 4 is not always necessary.

発明の効果 以上の説明から明らかな様に、本発明の電圧安定化回路
は、負荷といて抵抗負荷を用いたために、起動回路を用
いなくても電源投入時の起動がなされるだけでなく、開
ループゲインが小さくなることから、位相補償用コンデ
ンサが無くても安定に動作し、ＩＣ化した時のチップサ
イズを小さくすること、負荷変動の高域周波数特性の改
善を可能にできるという格別の効果を奏する。EFFECTS OF THE INVENTION As is clear from the above description, since the voltage stabilizing circuit of the present invention uses the resistive load as the load, not only the startup at the time of power-on is performed without using the startup circuit, Since the open loop gain becomes small, it operates stably even without a phase compensation capacitor, the chip size when integrated into an IC can be made small, and the high frequency characteristics of load fluctuation can be improved. Produce an effect.

【図面の簡単な説明】[Brief description of drawings]

第１図は従来のバンドギャップ方式による電圧安定化回
路図、第２図は本発明によるバンドギャップ方式の電圧
安定化回路の一実施例を示す回路図である。 Q1〜Q7……トランジスタ、R1〜R5，RL……抵抗、C1……
コンデンサ。FIG. 1 is a conventional bandgap voltage stabilizing circuit diagram, and FIG. 2 is a circuit diagram showing an embodiment of a bandgap voltage stabilizing circuit according to the present invention. Q 1 ~Q 7 ...... transistor, R 1 ~R 5, R L ...... resistors, C 1 ......
Capacitors.

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】共通接続部に一端を接続した第１，第２の
抵抗と、コレクタに前記第１の抵抗の他端を接続したダ
イオード手段用の第１のトランジスタと、ベース及びエ
ミッタ回路を前記第１のトランジスタのベース及びエミ
ッタと並列接続すると共に、前記第２の抵抗の他端にコ
レクタを接続した第２のトランジスタとによって構成さ
れ、異なる電流密度で動作する電流ミラー対と、 電源入力端子に一端を接続した抵抗負荷の他端にコレク
タを結合し、前記エミッタ回路の共通接続点にエミッタ
を接続すると共に、前記第２のトランジスタのコレクタ
にベースを接続した第３のトランジスタと、 コレクタに前記電源入力端子が接続され、ベースに前記
抵抗負荷の他端が結合されると共に、エミッタに出力端
子が接続された出力用トランジスタと、 前記出力端子から前記第１，第２の抵抗の共通接続部に
出力信号を帰還する帰還回路とを備え、 前記電流ミラー対，前記第３のトランジスタ，前記出力
用トランジスタ及び前記帰還回路が負帰還ループを構成
することを特徴とした電圧安定化回路。1. A first and a second resistor having one end connected to a common connection, a first transistor for diode means having a collector connected to the other end of the first resistor, and a base and an emitter circuit. A current mirror pair that is connected in parallel to the base and emitter of the first transistor and has a second transistor having a collector connected to the other end of the second resistor and that operates at different current densities; A collector connected to the other end of the resistive load having one end connected to the terminal, an emitter connected to the common connection point of the emitter circuit, and a third transistor having a base connected to the collector of the second transistor; Is connected to the power supply input terminal, the other end of the resistive load is coupled to the base, and the output transistor is connected to the emitter at the output terminal. And a feedback circuit that feeds back an output signal from the output terminal to the common connection portion of the first and second resistors, wherein the current mirror pair, the third transistor, the output transistor, and the feedback circuit are A voltage stabilizing circuit characterized by forming a negative feedback loop. 【請求項２】出力用トランジスタがダーリントン接続の
トランジスタ回路であることを特徴とした特許請求の範
囲第１項記載の電圧安定化回路。2. The voltage stabilizing circuit according to claim 1, wherein the output transistor is a Darlington connection type transistor circuit.
JP17970184A 1984-08-28 1984-08-28 Voltage stabilization circuit Expired - Lifetime JPH0614307B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17970184A JPH0614307B2 (en) 1984-08-28 1984-08-28 Voltage stabilization circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17970184A JPH0614307B2 (en) 1984-08-28 1984-08-28 Voltage stabilization circuit

Publications (2)

Publication Number Publication Date
JPS6158017A JPS6158017A (en) 1986-03-25
JPH0614307B2 true JPH0614307B2 (en) 1994-02-23

Family

ID=16070359

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17970184A Expired - Lifetime JPH0614307B2 (en) 1984-08-28 1984-08-28 Voltage stabilization circuit

Country Status (1)

Country Link
JP (1) JPH0614307B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03179514A (en) * 1989-11-02 1991-08-05 Toshiba Corp Constant voltage circuit
JP5353548B2 (en) 2009-08-14 2013-11-27 富士通セミコンダクター株式会社 Band gap reference circuit
CN106292823B (en) * 2016-08-31 2018-10-09 苏州纳芯微电子股份有限公司 A kind of high-low pressure conversion integrated circuit

Also Published As

Publication number Publication date
JPS6158017A (en) 1986-03-25

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