JPH06142387A - Control system for inverter type fully automatic washing machine - Google Patents

Abstract

PURPOSE:To achieve higher reliability of communication by making a frequency of a PWM chopper synchronize with a clock output timing of the communication to strengthen a proof stress against surging. CONSTITUTION:A microcomputer 1 for a washing machine sequence executes a sequence set by a customer monitoring various state signals of an external lid or the like and sensors 6 such as water level sensors. The setting by the customer is inputted into the microcomputer 1 to indicate through an input WS circuit 2. The state of proceeding is shown on a display circuit 3 area drive command of a motor by practical application of the sequence is communicated to a microcomputer 10 for controlling an inverter motor through a serial ring section 9 while the condition of the motor is communicated to the microcomputer 1 from the microcomputer 10. Here, a serial baud rate fbau and a PWM chopping frequency fcp are expressed by fbau = fcp or fbau>=fcp X n (n>=12:12 is given as the longest bit structure). This enables the strengthening of a proof stress against surging thereby achieving higher reliability of communication.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improving the reliability of communication means for control in which a serial link is composed of a plurality of microcomputers in a control system for an inverter fully automatic washing machine.

[0002]

2. Description of the Related Art In many cases, the inverter control of a washing machine is controlled by a one-chip microcomputer.
Conventionally, there is no case composed of more than chips. Therefore, serial communication was never used. However, from now on, it will be required to control the next output current waveform by high-speed calculation based on the high-speed current detection by the inverter control (effect is silent etc.), and it will add value to the washing machine sequence and functions. Nowadays, there are many demands for products that use a microcomputer with several chips and serial communication. The present invention proposes a method of improving reliability as a system by avoiding internal noise (internal surge) occurrence timing and timing when the cause and timing are clear during serial communication.

[0003]

Usually, parity check, sum check, retry, etc. are means and systems for ensuring reliability, but communication reliability is ensured against noise (surge) generated by PWM. , The challenge is to improve.

[0004]

[Means for Solving the Problems] The basic structure is (1) P.
Generated by transmitting and receiving in synchronization with the PWM chopper, with the same clock source for the WM chopper and (2) UART (asynchronous communication) baud rate generator, or as a configuration having means for synchronizing even if they are individual Always shift the timing of data transfer from the internal surge.

[0005]

As a measure against the internally generated surge and noise, the timing of data transfer is always shifted from the internal surge generated by transmitting and receiving in synchronization with the PWM chopper, and the reliability of the serial link is enhanced.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A block diagram of the inverter-controlled fully automatic washing machine shown in FIG. 1 will be described. The logic controller is composed of two one-chip microcomputers, a washing machine sequence microcomputer 1 and an inverter motor control microcomputer 10. The washing machine sequence microcomputer 1 manages the washing process, time management, input, display, and driving of loads other than the motor. The inverter motor control microcomputer 10 is a microcomputer that controls the inverter motor (software servo). These two microcomputers are based on the microcomputer peripheral circuit part of the inverter motor control microcomputer clock circuit 17 and the inverter motor control microcomputer reset circuit 18 as well as the washing machine sequence microcomputer clock circuit 7 and the washing machine sequence microcomputer reset circuit 8. Is serially coupled via a serial link circuit unit 9. In the embodiment, these are constructed asynchronously, so that they are composed of two signal lines of Tx (transmission side) and Rx (reception side). The microcomputer 1 mainly monitors the water supply valve solenoid, the drainage motor, the clutch solenoid, and various drive statuses such as an outer lid, various status signal groups 5 such as status detection, and a sensor group 6 such as a water level sensor, a humidity sensor, and a dirt sensor. It executes the sequence set by the customer. The above-described customer setting is input to the washing machine sequence microcomputer 1 via the input SW circuit 2. The progress status is displayed on the display circuit 3, and the motor drive command (rotation speed, rotation direction, etc.) due to the execution of the sequence is transferred to the inverter motor control microcomputer 10 via the serial link unit 9 and from the inverter motor control microcomputer 10 to the washing operation. The state of the motor is communicated to the machine sequence microcomputer 1. In this way, even in white goods household appliances, high-performance computing functions and high-speed analog channels are required because the processing that exceeds the processing speed normally possessed by a one-chip microcomputer is imposed on the microcomputer due to the sophistication of functions by incorporating inverter control. There is a need for a serial link due to the configuration of multiple microcomputers including a microcomputer with a normal washing sequence and a microcomputer for normal washing sequence, but at the same time, internal surge and noise generated by inverter control become a problem. There are various serial links such as synchronous, asynchronous, half-duplex, full-duplex, 2-wire type, 3-wire type, etc.
Most of recent one-chip microcomputers have built-in hardware and software satisfying these functions, and in this embodiment, they are configured by using asynchronous type and full duplex.

The inverter drive signal will be described with reference to FIG. 2 showing the drive signal and waveform of the inverter motor and FIG. 1 which is a block diagram of the inverter-controlled fully automatic washing machine.

A signal indicating the positional relationship between the rotor position and the stator is input from the DC brushless motor 13 to the position detection signal circuit 16. A, B, and C in FIG. 2 are the position signals. Using these signals as reference signals, the driver 12 passes the upper arm UV through the pre-drive 14 as shown in FIG.
W and lower arm UVW are sequentially generated. These switchings are supplied from the AC 100V to the driver 12 as the DC power source 11 in the converter section. When the upper arm and the lower arm are switched, a current flows through the corresponding coil of the brushless motor 13 and a magnetic field is generated, so that the rotor rotates. When a current flows through the coil, the feedback current is detected by the current detection circuit 15 and input to the inverter control microcomputer. In the upper arm (this example is the upper arm chopper, there is also a lower arm chopper method), and the applied voltage is controlled by chopping. In this way, the duty of the chopper is changed every moment based on the deviation of the actual rotation speed from the target rotation speed.

The cause of the surge will be described with reference to FIG. 3 showing the PWM chopper and its generated surge, and FIG. 1 described above. As described above, in the PWM chopper, the applied voltage is controlled by the ratio of the ON section between 0 and t1 of the PWM chopper cycle T and the OFF section between t1 and tn, and the duty ratio. At t1 and tn, the timer / counter incorporated in the microcomputer is activated and the output timing is generated by comparing the existing set values of t1 and tn with the count value of the timer / counter. Generally, T and tn are fixed and t
1 is determined from the calculation result based on the load state, the rotation speed from the position signal circuit 16 of FIG. 1, the current change of the current / current detection circuit 15, and the like. Normally, at the time of rising at the time of commutation, at the time of transition at the time of startup, and at other steady times, t1 is changed from moment to moment in accordance with the difference between the target number of revolutions and the actual number of revolutions. As described above, the PWM chopper is an important factor for controlling the inverter. Now, in FIG. 1, the driver 12A of the upper arm U and the driver 12C of the lower arm W
Considering the case where is on, when the driver of the driver 12A of the upper arm U is turned off, the current flowing through the coil flows through the forward direction of the free wheeling diode U12D.
At the next moment, when the driver of the driver 12A of the upper arm U is turned on, the free wheeling diode U12D passes in the reverse direction and flows a steep surge current until the reverse blocking capability is restored. These are surges generated at the timings shown in FIG. 3, and surges are generated at the rising and falling edges of the PWM chopper as shown in the figure. This adversely affects the operation of other light electric circuits. As an example thereof, as an important component sensitive to noise and surge, FIG. 3 exemplifies asynchronous communication for transmitting and receiving an operation command and a state when the two microcomputers are configured. The signal sequence is composed of 8 bits of data (1) to (8), (9) parity bits and stop bits with the start bit at the beginning, and as shown in the figure, (2), (4), (). If data is garbled as a result of inducing a signal line or applying normal mode noise to the data of 8), the command or state to the inverter motor will be erroneous. Normally, a 1-bit error can be detected by the parity check, but an error occurring randomly in a plurality of bits cannot be dealt with as shown in the figure.

By using FIG. 4 showing the timings of the asynchronous communication and the PWM chopper, it will be explained that the above-mentioned problems can be avoided by synchronizing the timing of the surge occurrence and the asynchronous communication as in the present invention. The bit configuration of the asynchronous communication in the figure consists of start bit 1, 8-bit data, parity bit 1 and stop bit 1. These are Tx data transmission and Rx data reception inside (or outside) of each microcomputer with reference to the clock rate of 8f, 16f, ... Of baud rate fbau.

In UART (asynchronous communication), the central part of the bit is taken out by the clock, so avoiding them, in chopper A (example when the duty is large), it is synchronized with the rising edge as shown in the figure. If asynchronous communication is activated and the baud rate is made the same, it is possible to avoid the timing at which a surge is likely to occur. Similarly, the chopper B (an example when the duty is small) may be synchronized with the falling edge.

That is, assuming that the serial baud rate is fbau and the PWM chopping frequency is fcp, the timings of the PWM chopper output and the asynchronous communication start are synchronized to fbau = fcp or fbau ≧ fcp × n (n ≧
It is clear that 12) is sufficient.

The method of synchronization and the scaling of the clock frequency will be specifically described by using the configuration of the embodiment shown in FIG.

Fsys19 is a system clock of the microcomputer. This is used as a prescaler in the 1 / k1 frequency dividing circuit 20 to adjust the frequency, and the frequency-divided output 21 is used as the clock source of the PWM counter 26. This clock source determines the duty resolution of the chopper. The PWM counter 26 is cleared by the position signal 25 at the initial stage of commutation, and thereafter the chopper cycle T is 0 to t1.
It is repeatedly counted as tn. The values t1 and tn are set by software in the compare register 28. The counter values of the PWM counter 26 are compared by the comparator 27. When they match, the INT generation 29 activates the UART 30. The processing at the time of start-up is processed by software interrupt, and t1 or tn is set in the compare register 28 via t1, tn set 33 according to t1 / tn sel 36, and t1 start-up or tn is started depending on the magnitude of the duty. Start the UART 30.

On the other hand, the UART 30 becomes 1 /
k2 div 34 prescaler 1/8 div 2
The 2 (8 f clock in this embodiment) baud rate generator is cleared via the signal line 23 to operate at fbau.
The clock 24 is synchronized. Similarly, a transmission signal is transmitted from Tx31 by the synchronized φ clock 35 of the opposite phase, and R
The reception operation is performed at x32. In summary, the formula is as follows. The baud rate for asynchronous communication is fbau = fsys × (1 / k1) × (1 / k2) × (1 /
8) The PWM chopper frequency is f cp = fsys × (1 / k1) × tn count, and in this embodiment, fbau = f cp is synchronized.

The above is the description of the embodiment.

By synchronizing with such a configuration, surge can be avoided and a highly reliable system configuration can be realized.

Although the above is composed of circuit blocks and expressed, usually, a counter / timer function with a built-in microcomputer, U
It can be configured by controlling the ART function, microcomputer interrupt function, etc. with software, and there is no cost. Also, communication can be realized by the same idea even if it is a synchronous system. UART
In the case of 1, the inverter side takes the initiative in switching between transmission and reception and has a full-duplex configuration. However, in the synchronous 3-wire system, if only SCK is generated at the above-mentioned timing, the configuration can have a relatively high degree of freedom.

[0019]

According to the method of the present invention, it changes every moment during communication and is extremely resistant to the noise and surge environment applied. It is a very effective means when combined with the conventional noise countermeasures, parity check and sum check. Yes, the communication function can be completed while recovering without stopping the function of the product. In addition, it can be easily embodied using a simple algorithm software and a function built into the microcomputer. Furthermore, there is an effect that the wiring design has a resistance even if a strong electric system and a communication, and a weak electric system related to a power source and the like are close to each other.

[Brief description of drawings]

FIG. 1 is a block diagram of an inverter-controlled fully automatic washing machine.

FIG. 2 is a diagram showing a drive signal and a waveform of an inverter motor.

FIG. 3 is a diagram showing a PWM chopper and its generated surge.

FIG. 4 is a diagram showing timings of asynchronous communication and a PWM chopper.

FIG. 5 is a diagram showing a configuration of an example.

[Explanation of symbols]

1 ... Washing machine sequence microcomputer, 3 ... Serial link circuit section, 10 ... Inverter motor control microcomputer, 26
... PWM counter, 27 ... comparator, 28 ... compare register, 30 ... UART, 31 ... Tx, 32 ... Rx.

Claims (2)

[Claims] 1. A fully automatic washing machine, including an inverter motor, an actuator such as a water supply valve, a water level sensor, an input signal source such as a lid opening / closing switch, an input means for taking in customer's settings, a setting state, and a progress. The control board has a display means for displaying the status, and has a plurality of microcomputers for executing and controlling the sequence in accordance with the setting status and the status of the input signal. A control method for an inverter fully automatic washing machine characterized by synchronizing the communication clock with inverter-controlled chopping in order to properly execute communication between microcomputers. 2. A serial baud rate f in the above configuration.
bau and PWM chopping frequency fcp
bau = fcp or fbau ≧ fcp × n (n ≧ 1
2. The control system for the fully automatic inverter washing machine according to claim 1, wherein 2:12 is the longest bit configuration).