JPH06140893A - Semiconductor multiplexer circuit - Google Patents

Abstract

PURPOSE:To remove noise at a point of the change-over time by inputting plural control signals from an external side, detecting the overlapping of an H level and generating an internal control signal which permits whole switches to be non-conductive in the overlapping period. CONSTITUTION:Control C1 inputted to a control signal terminal 21 for controlling the switch 31 is permitted to be an H level state so as to be in a conductive state from a point of the time t1 to t5. At the same time, the control signal C2 is the H level state from a point of the time t0 to t3 and the control signal C3 is from a point of the time t7 to t9. An internal control signal generating circuit 40 outputs the control signals G1-G3, within the signal C3, which lets switch-type transistor T1-T3 be a non-conductive state for a period for the period of time when Tr T1-T3 are conductive. Then, the all respective switches 31-33 are the non-conductive state over a period of time when from a point of the time t2-t4 and an analog signal output terminal 10 becomes a high impedance state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor multiplexer circuit, and more particularly to a multiplexer circuit having a plurality of switch elements.

[0002]

2. Description of the Related Art When handling an analog signal, for example,
In recent years, there has been a great demand for inputting analog signals of several systems to one analog-digital converter, or for allocating signals from multiple audio band signals or image band signal sources to multiple devices. It's getting stronger.

Therefore, a multiplexer circuit and a cross-point switch circuit in which one ends of a plurality of switch elements are commonly connected have been put to practical use in semiconductor integrated circuits and the like.

FIG. 4 shows a conventional three-input analog multiplexer circuit as an example. That is, the first to third semiconductor switch elements (hereinafter abbreviated as switches) 31, 32, 3
Each output terminal of 3 is connected to the analog signal output terminal 10 via an output node N.

In the figure, analog signal input terminals 11 and 1
2 and 13 are analog signals S1 to S for each switch.
3, and the control input signal terminals 21, 22, and 23 input the control signals C1 to C3 to the control terminals g1 to g3 of the switches 31 to 33, respectively.

FIG. 5 is a time chart of the operation of the analog multiplexer circuit shown in FIG. To simplify the description, the analog signal S input to each switch is
1 to S3 do not change, the input signal S1 of the first switch 31 is 6V, and the input signal S of the second switch 32 is
2 is 0V, and the input signal S3 of the third switch 33 is 2V.

It is assumed that each switch is conductive when the control signals C1 to C3 are at "H" level and non-conductive when the control signals are at "L" level. In the time chart, the conductive state of the switches is "H" level. Further, the non-conducting state is shown by "L" level.

It is assumed that the switch 31 is conductive from time t1 to t5, the switch 32 is conductive from time t0 to t2, and the switch 33 is conductive from time t7 to t11.

When the conduction and non-conduction of each switch are controlled in this way, both the switch 31 and the switch 32 are in the conductive state from the time t1 to t2, and the output node N, and further the analog signal. At the output terminal 10, the analog input signal S16V and the analog input signal S2 of 0 V are divided by the signal source resistance.

For example, each analog signal input terminal 11, 12
If the output resistance values of the input signal sources connected to each other are the same and the resistance values of the switches when they are conductive are equal, 3 V, which is just the midpoint level of the two analog input signals S1 and S2, is output. It will be.

This is an output that cannot originally appear as the output signal SN of the analog multiplexer circuit and becomes noise. On the other hand, all the switches are in the non-conducting state from time t5 to t7.

In this case, the output contact of each switch and the capacitance CS of the analog signal output terminal 10 have
The input level of the analog signal S1 applied to the switch 31 which has been in the conducting state until the time t5 is held, and the switch 33 becomes the conducting state at the time t7, so that an unnecessary signal level that becomes noise is generated. No output.

[0013]

As described above, in the conventional semiconductor multiplexer circuit, conduction of each switch,
Due to a delay between control signals for controlling non-conduction and the like, the two switch elements are simultaneously turned on, and an unnecessary signal level that becomes noise is output.

In order to eliminate this noise, it is necessary to control the signal switching in consideration of the delay time of the control signal of each switch element up to each switch element. Particularly, this circuit is provided on an integrated circuit. When configured, it was virtually impossible to prevent any noise from being output.

An object of the present invention is to provide a semiconductor multiplexer circuit that does not generate noise when switching.

[0016]

According to the semiconductor multiplexer circuit of the present invention, one end of each of a plurality of switch elements is connected in common and the other end serves as an input end or an output end of a signal, and control signals corresponding to the control end are respectively supplied. In a semiconductor multiplexer circuit for inputting, an external control signal is input, and a weight detection circuit for detecting a combination of the control signals in which at least two or more switch elements are simultaneously turned on, and a weight detection signal output by the weight detection circuit and the control A control signal generating circuit for inputting a delay signal of the signal and supplying an internal control signal to the switch is configured.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention.
The analog multiplexer circuit of this embodiment is the switches 31 to 33 of the conventional analog multiplexer circuit of FIG.
Control input terminals g1 to g3 and control signal input terminals 21 to 23
Are the same except that the internal control signal generating circuit 40 is inserted between the two.

FIG. 2 is a circuit of the block shown in FIG. The switch elements 31 to 33 are the N-type MOS transistors T1 to T1.
Gate control signal G which is composed of T3 and is input to each gate
The analog signals S1 to S3 are output as output node signals SN by 1 to G3, respectively.

The internal control signal generation circuit 40 has control input signals C1 to C3 of the switches 21 to 23 applied from the outside.
Detects whether the two are at "H" level at the same time,
A time point (tf + t) that is delayed by a certain time td from the rising time point tr of one or more of the control signals if two or more control signals become "H" level at the same time.
up to d) control signals G1 to G3 to all switches T1 to T3
The signals G1 to G3 for setting the "L" level, that is, the non-conduction state
Is a circuit for outputting.

That is, the internal control signal generating circuit 40 is an AN.
At a time point (tf + td) after the weight detection circuit 70 having the D gates 71 to 73 and the NOR gate 74, and one of the two combinations of the switch control signals C1 to C3 becomes "L" level. Delay circuits 78 to 80 and an AND circuit are provided to release the non-conduction state of all switches.
It has gates 75-77.

FIG. 3 shows a time chart of each signal for explaining the operation of the circuit of FIG. Analog input signal is S
1 to S3 are the same as the conventional waveform shown in FIG.

Here, the control signal C1 input to the control signal terminal 21 for controlling the switch 31 is in the "H" level state so as to be in the conductive state from the time t1 to the time t5. Similarly, the control signal C2 is in the "H" level state from the time t0 to t3 and the control signal C3 is in the conductive state from the time t7 to t9.

In the internal control signal generating circuit 40, the two switching transistors T1 to T3 of C3 are in the conductive state at the same time, that is, the period T from the time t1 to the time t3.
All switching transistors T1 to T3 through 13
In order to output the control signals G1 to G3 for making the switch non-conducting state and to apply to the conduction / non-conducting control signal terminals of the respective switch elements, the switch becomes non-conducting state at time t2 and the switch 31 becomes conducting state at time t4. During the period T24 from the time point t2 to the time point t4, the switches 31 to 33 are all in the non-conductive state, and the analog signal output terminal 10 is in the high impedance state.

Therefore, unnecessary noise signals that should not be generated at the output terminal 10 do not appear, that is, the control signals C1 to C3 of the switching transistors T1 to T3.
Even if the simultaneous "H" level period is long, an unnecessary noise signal can be completely removed from the analog signal terminal.

[0025]

As described above, the present invention is provided with the weight detection circuit for inputting a plurality of control signals from the outside and detecting the weights of those "H" levels, and the weight detection circuit is used for all the overlapping periods. Since the internal control signal that causes the switch to become non-conductive is generated, consider the delicate timing of the switch control signal for the signal that becomes unnecessary noise that has been generated when switching the switch circuit in the past. There is an effect that it can be completely removed without.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a detailed circuit diagram of FIG.

3 is a timing chart of each signal for explaining the operation of the circuit of FIG.

FIG. 4 is a block diagram of an example of a conventional semiconductor multiplexer circuit.

FIG. 5 is a time chart of each signal for explaining the operation of the block of FIG.

[Explanation of symbols]

 10 analog signal output terminals 11 to 13 analog signal input terminals 21 to 23 control signal input terminals 31 to 33 switch element 40 internal control signal generation circuit N output node 71 to 77 AND gate 74 NOR gate 78 to 80 delay circuit C1 to C3 control Signal G1 to G3 Gate signal S1 to S3 input signal SN output node signal

Claims (1)

[Claims] 1. A semiconductor multiplexer circuit in which one end of each of a plurality of switch elements is commonly connected and the other end serves as an input end or an output end of a signal, and a control signal corresponding to the control end is input, and an external control signal is input. However, a weight detection circuit that detects a combination of the control signals in which at least two or more switch elements are simultaneously turned on, and a weight detection signal output from the weight detection circuit and a delay signal of the control signal are input to the switch. A semiconductor multiplexer circuit comprising a control signal generation circuit for supplying an internal control signal.