JPH06140213A - Resistor matrix circuit and driving method thereof - Google Patents

Abstract

PURPOSE:To provide the title resistance matrix circuit and driving method thereof in simple structure displaying the functions as storage elements in high recording density having easy recording and reading out capacity. CONSTITUTION:A plurality of mutually insulated rows Xie and a plurality of columns Yjf formed on the rows Xie with insulating layers therebetween are provided. Next, resistors Rijk both ends of which are connected to the rows Xie and columns Yjf respectively are provided on the intersecting parts of the rows Xie and the columns Yjf with insulating layers therebetween. Through repetion of the procedures, a plurality of layers are formed of the rows Xie, the resistors Rijk and the columns Yif.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resistance matrix circuit used as a memory element by stacking circuits assembled in a matrix form and a driving method thereof.

[0002]

2. Description of the Related Art Conventionally, as disclosed in Japanese Patent Laid-Open No. 63-142915 of the applicant of the present invention, a resistance matrix circuit is provided between conductor patterns that are two-dimensionally assembled in the XY directions. The resistor is formed at each intersection. The resistance matrix circuit measures various physical quantities by measuring the resistance value of the resistors incorporated in the matrix. In addition, this resistance matrix circuit
A memory used as a digital memory or an analog memory has also been proposed.

[0003]

In the above conventional technique, there is a problem that the array of the resistors is two-dimensional and the storage capacity when used as a storage element is small. Further, the known semiconductor memory has a complicated structure, and the higher the storage density, the more complicated the manufacturing process. Further, other known magnetic storage media, optical disks, and the like have a problem that a recording / reproducing apparatus becomes large in size because a mechanical structure is required for recording / reproducing.

The present invention has been made in view of the above-mentioned problems of the prior art, and has a simple structure and a resistance matrix circuit having a function as a memory element having a high recording density and easy recording and reading. It is an object to provide a driving method thereof.

[0005]

The present invention is directed to a plurality of row lines insulated from each other, and a plurality of column lines insulated from each other on the row lines and sandwiched between the plurality of row lines and an insulating layer. Is provided, and a resistor whose both ends are connected to the row line and the column line is provided at a portion where the row line and the column line intersect with each other across the insulating layer, and the row line, the resistor, and the column line are provided. Is a resistance matrix circuit formed by repeating a plurality of layers. This invention also
The potential of any one of the row lines in the same layer is set to the first potential, and the potential of the other row lines in the same layer is set to the second potential different from the first potential, The potential of any one column line in the layer of the column line adjacent to this row line is set to the above second potential across the resistor, and the potentials of the other column lines in that layer are set to the above first potential. The potential of the column line adjacent to the other side of the arbitrary one row line is set to the first potential, and the row adjacent to the other side of the arbitrary one column line is set to the first potential. This is a method of driving a resistance matrix circuit in which the potential of the line is set to the second potential and the value of the resistor between the arbitrary row line and column line is read.

[0006]

In the resistance matrix circuit and the driving method thereof according to the present invention, since the circuits formed in a matrix shape with the resistors interposed therebetween are three-dimensionally stacked, the recording density is high,
Moreover, when reading the resistance value, the current is prevented from sneaking from the lines other than the line sandwiching the arbitrary resistor, and the resistance value can be read accurately.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. As shown in FIGS. 1 to 3, the resistance matrix circuit of this embodiment has a Y1 layer composed of n conductor row lines of copper or the like insulated from each other, and SiO ₂ on the Y1 layer.
The insulating layer 11 is formed, and on the insulating layer 11, the X2 layer formed of m conductor row lines of copper or the like insulated from each other is formed. Further, a Y3 layer similar to the Y1 layer is formed via the insulating layer 12, an X4 layer similar to the X2 layer is formed via the insulating layer 13, and a Y1 layer is formed thereon via the insulating layer 14. A similar Y5 layer is formed. Hereinafter, each row line is referred to as Xie (i is the number of rows and is an arbitrary natural number from 1 to m, e is a layer position and is 2 or 4), and each column line is Yjf (j is the number of columns and 1). ~ N is an arbitrary natural number, f is the position of the layer, and is represented by 1, 3 or 5. Therefore, this embodiment is a three-dimensional circuit having five layers of row lines or column lines. The Y1 layer, which is the bottom layer, is formed on the ceramic substrate 15, and each column line Yj is formed.
1 is formed via the nickel film line 16. The uppermost Y5 layer is entirely covered with a SiO ₂ protective film 17.

The row line Xie and the column line Yjf are the intersections between the row or column lines of the layers adjacent to each other, and are formed in the through holes formed in the insulating layers 11 to 14 with resistors Rijk (i) such as tantalum. , J are the same as above, and k is 1
4 to 4 (corresponding to the insulating layers 11 to 14) are provided. Each resistor Rijk has 500Ω, 1k for each position.
Ω, 2kΩ, 4kΩ to a value appropriately selected,
It forms predetermined information.

Each row line Xie is a switch SXiLe (i is 1 to 1 corresponding to a row line) formed by a multiplexer or the like.
via any natural number of m, e is 2 or 4),
It is connected to the output side terminal of the buffer amplifier 20 for each row formed of an operational amplifier or the like, and the input terminal of each buffer amplifier 20 is connected to a predetermined low potential line 22 via a resistor Rx. Further, each row line Xie is also connected to a high potential line 24 of a predetermined high potential VH1 via a switch SXiHe (i is an arbitrary natural number of 1 to m corresponding to the row line, e is 2 or 4). Has been done.

Each column line Yjf is composed of an operational amplifier or the like via a resistor Rs and a switch SYjLf (j is an arbitrary natural number 1 to n corresponding to the column line, and f is 1, 3 or 5). It is connected to the output side terminal of the buffer amplifier 26, and the input terminal of this buffer amplifier 26 is connected to a predetermined low potential VL1. Further, each column line Yjf is provided with a resistor Rs and a switch SYjHf (j is an arbitrary natural number of 1 to n corresponding to the column line, f is 1, 3 or 5), and each column line is composed of operational amplifiers or the like. Of the buffer amplifier 28, and the input terminal of each buffer amplifier 28 is connected to a high potential line 30 of a predetermined high potential VH2 (here, VH1 = VH2) via a resistor Ry. ing. Each column line Yjf is connected to the output line 32 by a switch SWoj.
connected via f (f is 1, 3 or 5). A buffer amplifier 34 is provided on the output line 32, and is further connected to the low potential line 22 via a buffer amplifier 36.

In the method of manufacturing the resistance matrix circuit of this embodiment, a nickel thin film and a copper thin film are respectively formed on the ceramic substrate 15 by vapor deposition, and these are etched at a predetermined width and at a predetermined interval to form the column line Yj1 of the Y1 layer. To form. The nickel thin film is formed to ensure the adhesiveness between the ceramic substrate 15 and the copper thin film. After this, SiO ₂
The insulating layer 11 is formed by vapor deposition. This insulating layer 11
Further, through holes having a pitch equal to that of the column line Yj1 and narrower than the line width are formed vertically and horizontally by etching. After that, tantalum is vapor-deposited, and the tantalum in the through hole is left, and etching is performed at each through hole position so as to have a desired resistance value among the above four types, thereby forming a resistor Rij1. Copper is vapor-deposited on this, and etching is performed so that the row line Xi2 is formed in the direction orthogonal to the column line Yj1 at the same pitch. Thereafter, similarly to the above, the insulating layer 12, the resistors Rij2, Y3 are sequentially arranged.
Layer, insulating layer 13, resistor RiJ3, X4 layer, insulating layer 1
4, resistor Rij4, Y5 layer is formed, and finally the protective film 1
7 is vapor-deposited.

The operation of the resistance matrix circuit of this embodiment will be described below. The driving method of the matrix circuit of this embodiment is, for example, as shown in FIG.
Consider the case of reading the value of
Wo33 is closed, switch SX3H2 and switch SY
3L3 is closed, and the row line X32 of the X2 layer is set to the high potential VH1.
The column line Y33 of the Y3 layer is connected to the low potential VL1. Further, since all the row lines Xi2 other than the row line X32 of the X2 layer are connected to the low potential line 22, all the switches SXiL2 other than the switch SX3L2 are closed. Further, since all the row lines Yj3 other than the column line Y33 of the Y3 layer are connected to the high potential line 30, all the switches SYjH3 other than the switch SY3H3 are closed. Further, in order to connect all the column lines Yj1 of the Y1 layer adjacent to the X2 layer to the high potential line 30, all the switches SYjH1 are closed. Then, in order to connect all the row lines Xi4 of the X4 layer adjacent to the Y3 layer to the low potential line 22, all the switches SXiL4 are closed. Also, leave all other switches open.

As a result, a noise current does not flow into the row line X32 of the X2 layer and the column line Y33 of the Y3 layer from other lines or layers. When the output potential is VL2, VL2 = VH1 {Rs / (R3
32 + Rs)}, R332 = Rs (VH
1 / VL2-1), and the resistance value is calculated from the output VL2. Further, the values of other arbitrary resistors Rijk can be read in the same manner.

According to the resistance matrix circuit of this embodiment, only the current flowing through the resistance at the position to be read is output, and the current does not flow from the other line of the same layer or the line of the other layer, and the accurate resistance is obtained. The value can be calculated. Therefore, by setting this resistance value arbitrarily, it can be used as an accurate analog memory and also as a digital memory, and since it is formed in a three-dimensional structure, it has a high recording density and can be read out. An easy storage element can be obtained.

As another embodiment of the resistor matrix of the present invention, the resistor of the above embodiment may be formed in a narrow pattern by using a material having a fuse property. Then, in order to cut the fuse portion at the desired position, the desired row and column lines are connected to H and L and the fuse portion is cut, as in the case of reading the value of the resistor in the above embodiment. Apply the required voltage. At this time, the other fuse parts are connected via a predetermined resistor so that the current flows only to the extent that the fuse is not cut. In addition, each fuse part also has a resistance, except for the desired row and column lines,
The floating circuit is made to have a resistance at least tripled so that the electric power applied to each fuse portion cannot be reduced to 1/9 or less. As a result, like the PROM of the semiconductor memory, it can be used as a writable memory.

Further, instead of the resistor of the above embodiment, a high resistance film may be formed on the entire surface between the lines and an insulating film having a through hole may be formed at a desired intersection. According to this, a current flows through the high resistance film in the portion where the through hole is formed, and the resistance is infinite in other portions, so that a binary digital memory can be formed.

Further, an insulating film is formed on the conductor line and a through hole is formed at a desired position, and then an imidazole layer is formed or anodization is performed so that a resistance value can be obtained at this through hole portion. A thin insulating layer may be formed on the surface and a conductor line of the next layer may be formed thereon. This also
Sufficient digital memory can be obtained and can be easily manufactured.

[0018]

According to the resistance matrix circuit and the driving method thereof of the present invention, since the circuits formed in a matrix shape with the resistors interposed therebetween are three-dimensionally laminated, the recording density is high and the resistance value is high. At the time of reading, current does not flow from a line other than a line sandwiching an arbitrary resistance, driving can be performed without noise, and accurate reading is possible.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a resistor matrix circuit according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing the structure of a resistance matrix circuit of this embodiment.

FIG. 3 is a vertical cross-sectional view showing the structure of a resistance matrix circuit of this embodiment.

[Explanation of symbols]

 11-14 Insulating Layer Rijk Resistor Xie Row Line Yjf Column Line

Claims (2)

[Claims] 1. A plurality of row lines insulated from each other, and a plurality of column lines insulated from each other above the row lines and formed so as to be orthogonal to the plurality of row lines sandwiching an insulating layer. , A resistor whose both ends are connected to the row line and the column line is provided at a portion where the row line and the column line cross each other across the insulating layer, and the row line, the resistor, and the column line are repeated. A resistance matrix circuit comprising a plurality of layers. 2. A plurality of row lines insulated from each other, and a plurality of column lines insulated from each other above the row lines and formed so as to be orthogonal to the plurality of row lines sandwiching an insulating layer. , A resistor whose both ends are connected to the row line and the column line is provided at a portion where the row line and the column line cross each other across the insulating layer, and the row line, the resistor, and the column line are repeated. A resistance matrix circuit formed by forming a plurality of layers is formed, and the potential of any one of the row lines in the same layer is set to the first potential, and the potential of other row lines in the same layer is set. The second potential different from the first potential is set, and the potential of any one column line of the layer of the column line adjacent to this row line is set to the second potential with the resistor interposed therebetween. , Set the potential of the other column line of the layer to the first potential above, The potential of a column line adjacent to the arbitrary one row line on the opposite side of the arbitrary one column line is set to the first potential, and the potential of the arbitrary one column line is set to the first potential. And the potential of a row line adjacent to the side opposite to the arbitrary one row line is set to the second potential, and the value of the resistor between the arbitrary row line and the column line is read. And method for driving a resistance matrix circuit.