JPH06139346A - Huffman decoding circuit and method therefor - Google Patents

Abstract

PURPOSE:To provide the Huffman decoding circuit capable of high-speed operation and small in circuitry. CONSTITUTION:Plural Huffman codes are divided into three groups by code length. Huffman codes whose number of bits is <=6 are decoded by a decoding circuit 51 consisting of a logic circuit. Huffman codes whose number of bits is >=7 and <=12 are decoded by a memory table 52 consisting of a static RAM. Huffman codes whose number of bits is >=13 and <=16 are decoded by a memory table 53 consisting of a static RAM. Additional bit length data ABL is subtracted from total bit length data TBL outputted from each of memory tables 52 and 53 to calculate Huffman code length data HCL.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Huffman decoding circuit and a Huffman decoding method for decoding a Huffman code coded by the Huffman coding method.

[0002]

2. Description of the Related Art Image data contains a very large amount of information. Therefore, it is not practical to process the image data as it is in terms of memory capacity and communication speed. Therefore, image data compression technology is important.

J is one of the international standards for image data compression.
There is PEG (Joint Photographic Expert Group).
In JPEG, a DCT (Discrete Cosine Transform) method that performs lossy encoding and a DPCM (Differentientiation) in a two-dimensional space
A reversible coding method that performs alPCM) is adopted.
The DCT method image data compression will be described below.

(1) Basic Configuration of DCT Method FIG. 10 is a block diagram showing the basic configuration of a system for executing the DCT method.

On the encoding side, the DCT device 100 performs DCT conversion on the input original image data and outputs DCT coefficients. The quantizer 200 has a quantization table 400.
, The DCT coefficient is quantized and a quantized DCT coefficient (hereinafter referred to as a quantized DCT coefficient) is output. The entropy encoder 300 refers to the encoding table 500, performs entropy encoding processing on the quantized DCT coefficient, and outputs compressed data. The Huffman coding method is used as the entropy coding method.

On the decoding side, the entropy decoder 600
Performs entropy decoding processing on the compressed data with reference to the encoding table 500, and outputs the quantized DCT coefficient. The inverse quantizer 700 refers to the quantization table 400 to perform inverse quantization processing on the quantized DCT coefficient,
Output the T coefficient. The inverse DCT device 800 performs inverse DCT conversion on the DCT coefficient and outputs reproduced image data.

(2) DCT Transform Next, the DCT transform will be described. First, as shown in FIG. 11, the image data is divided into a plurality of 8 × 8 pixel blocks. As shown in FIG. 12, the value of each pixel data in one 8 × 8 pixel block is shown by P _XY (X, Y = 0, ..., 7). Here, X and Y represent the position of the pixel data in the block.

Two-dimensional DCT conversion according to the following equation is performed on each of the divided 8 × 8 pixel blocks.

[0009]

[Equation 1]

Here, S_UVRepresents the DCT coefficient,
U and V represent the position of the DCT coefficient. When U = V = 0
Is C_U= C_V= 1 / √2, otherwise C
_U= C _V= 1. Furthermore, the pixel data P_XYBit of
L when the precision is 8 bits _S= 128, the pixel
Data P_XYIf the bit precision of is 12 bits, L_S
= 2048.

As a result of the DCT transformation, 64 DCT coefficients S
_UV is obtained. The DCT coefficient S _{0 0} is called a DC coefficient, and the remaining 63 DCT coefficients are called AC coefficients.

The DC coefficient indicates the average value (DC component) of 8 × 8 pixel data. As shown in Expression (1), the expected value of the DC coefficient is level-shifted to 0 by subtracting L _S from each pixel data P _XY .

As shown in FIG. 12, the upper left and lower right of the DCT transformed block are DCT coefficients S _{0 0} ,
Corresponds to the S _{7 7.} As the DCT-transformed block progresses from left to right, it contains many high-frequency horizontal frequency components, and as it progresses from top to bottom, it contains many high-frequency vertical frequency components.

On the other hand, DC is obtained by the inverse DCT conversion shown in the following equation.
64 pixel data P _XY (X, Y = from the T coefficient S _UV
0, ..., 7) can be obtained.

[0015]

[Equation 2]

As shown in equation (2), the level shift amount is restored by adding L _S to each pixel data.

FIG. 13 shows an example of an 8 × 8 pixel block and
And the result of DCT conversion of the pixel block. Figure 1
As can be seen from 3, the DC coefficient and the low frequency component AC
The absolute value of the coefficient is large. For example, the DC coefficient
S_{0 0}Is 260, AC coefficient S _{0 1}Is 49, AC coefficient S
_TenIs -79.

(3) Quantization The DCT coefficient S _UV is linearly quantized by the following equation using the quantization table Q _UV which is different for each coefficient position, and quantized D
The CT coefficient r _UV is obtained.

R _UV = round (S _UV / Q _UV ) ... (3) round means integerization to the nearest integer. FIG. 14 shows the relationship between the quantized DCT coefficient r _UV , the DCT coefficient S _UV and the quantization table Q _UV .

Dequantization is performed on the decoding side. The quantized DCT coefficient obtained by the Huffman decoding described below is r
_{If it is UV} , inverse quantization is performed by the following equation.

S _UV = r _UV × Q _UV (4) The image quality can be controlled by changing the value of the quantization table Q _UV . When the value of the quantization table Q _UV is set small, the value of the quantized DCT coefficient r _UV becomes large, and an image with good image quality can be encoded. On the contrary, when the value of the quantization table Q _UV is set to be large, the value of the quantized DCT coefficient r _UV becomes small and the amount of encoded information decreases, but the image quality deteriorates.

As described above, by changing the value of the quantization table Q _UV , the image quality and the amount of encoded information can be freely controlled.

FIG. 15 shows an example of the quantization table. Generally, it is said that human vision has the characteristics of a low-pass filter, and it is insensitive to high frequency components. Therefore, even if rough quantization is performed on the DCT coefficient corresponding to the high frequency component, the effect is not so noticeable. for that reason,
As shown in FIG. 15, a large value is set for the high frequency component of the quantization table.

FIG. 16 shows the result of quantizing the DCT coefficients shown in FIG. 13 using the quantization table shown in FIG. For example, S _{0 0} = 260, Q
_{Since 0 0} = 16, r _{0 0} = round (260 /
16) = 16. Further, S _{0 1} = 49, Q _{0 1} = 1
Since it is 1, r _{0 1} = round (49/11) = 4
Becomes Furthermore, S _{1 0} = -79, since it is _{Q 1 0 = 12, r 1} 0 = round (49/12) = - a 7.

(4) Entropy coding The quantized DCT coefficient r _UV is entropy coded and compressed data is output. As shown below, the DC coefficient and the AC coefficient have different encoding methods.

(A) Coding of DC Coefficients FIG. 17 shows a flow chart of Huffman coding of DC coefficients. In the Huffman coding of the DC coefficient, the value (DC difference value) ΔDC _i of the difference between the DC coefficient D _i −1 of the immediately preceding block and the DC coefficient D _i of the current block is coded. As described above, the DC coefficient indicates the average value of the pixel data of the 8 × 8 pixel block. Therefore, except for a special image such as a computer graphic image, the DCT coefficients of adjacent blocks rarely change greatly. Therefore, the DC difference values are concentrated near 0. DC
Highly efficient encoding can be expected by encoding the difference value.

The DC difference values are classified into 16 groups according to the table shown in FIG. That is, according to the table of FIG. 19, it is determined to which group the obtained DC difference value belongs. For example, the group number SSSS of the DC difference value 0 is "0", and the DC difference value -1,1
The group number SSSS is "1". The group number SSSS of the DC difference values -3, -2, 2 and 3 is "2", and the group number SSSS of the DC difference values -7 to -4 and 4 to 7 is "3".

The DC difference value is encoded into a Huffman code using the Huffman code table shown in FIG. For example, the Huffman code “011” is assigned to the DC difference value whose group number SSSS is “2”, and the Huffman code “100” is assigned to the DC difference value whose group number SSSS is “3”.

For example, since the group number "2" includes eight DC difference values -7 to -4 and 4 to 7, one of the eight DC difference values is specified by the additional 3 bits. It The additional bits are assigned smaller values in order from the smaller DC difference value. For example, in the case of the group number “2”, the additional bit “00” is added to the DC difference value −7.
0 "is assigned, and an additional bit" 001 "is added to the DC difference value -6
Is assigned, and “111” is assigned to the DC difference value 7.

If the DC coefficient of the previous block is 25 and the DC coefficient of the current block is 16, the DC difference value is -9. From the table of FIG. 19, the group number SSSS of the DC difference value −9 is “4”. Therefore, according to the Huffman code table of FIG. 20, the Huffman code of the group number “4” is “101”. Since the DC difference value −9 is the seventh smallest DC difference value belonging to the group number “4”, as shown in FIG.
The additional bit is “0110”.

(B) Coding of AC Coefficients FIG. 22 shows a flow chart of Huffman coding of AC coefficients. In Huffman coding of AC coefficients, as shown in FIG. 23, AC coefficients are first arranged one-dimensionally by a zigzag scan. As will be described below, the AC coefficients arranged in one dimension include a run length indicating the length of consecutive "0" coefficients (ineffective coefficients) and values of coefficients other than "0" (effective coefficients). Is encoded using. That is, Huffman coding is performed using the run length NNNN of the invalid coefficient and the group number SSSS of the valid coefficient.

The AC coefficients are grouped according to the table shown in FIG. As shown in FIG. 24, the group number SSSS only limits the group to which the effective coefficient belongs. One of the effective coefficients belonging to one group
Additional bits are used to identify one. In Huffman coding of AC coefficients, a Huffman code is assigned to a combination of a run length NNNN and a group number SSSS. FIG. 25 shows a Huffman code table for AC coefficients. The run length / group number is encoded into a Huffman code using the Huffman code table.

When the last AC coefficient in the block is 0, "EOB" (End of Block) is added immediately after the Huffman code corresponding to the last effective coefficient, and the Huffman coding of the block is completed. However, when the last AC coefficient in the block is not 0, "EOB"
Not attached. When the run length of the invalid coefficient exceeds “15”, the run length of the invalid coefficient is 1 for every 16 invalid coefficients.
"ZRL" representing 6 is continuously added until the remaining run length becomes 15 or less, and then the remaining run length is Huffman coded as NNNN.

For example, the Huffman coding of the AC coefficient shown in FIG. 16 will be described. First, the effective coefficient of the first AC coefficient is r _{0 1} = 4. From the table of FIG. 24, the group number SSSS is “3”. The run length NNNN of the invalid coefficient is 0. Therefore, from the Huffman code table of FIG. 25, the Huffman code is “100”. As shown in FIG. 26, since the effective coefficient 4 is the fifth smallest AC coefficient among the AC coefficients belonging to the group number “3”, the additional bit is “100”. Therefore, the effective coefficient r _{0 1} is encoded as “100100”.

The next effective coefficient is r ₁₀ = -7. The group number SSSS is "3", and the run length N of the invalid coefficient
NNN is 0. As shown in FIG. 26, the effective coefficient is −7.
Is the smallest among the AC coefficients belonging to the group number “3”, the additional bit is “000”. Therefore, the effective coefficient r ₁₀ is encoded as “100000”.

By zigzag scanning, the next effective coefficient is r _{1 1} = 3. From the table of FIG. 24, the group number SSSS is “2”. In this case, the AC coefficient r _{2 0}
Is 0, the run length NNNN is 1. Therefore, the Huffman code is “11011” from the Huffman code table of FIG. As shown in FIG. 26, since the effective coefficient 3 is the largest among the AC coefficients belonging to the group number “2”, the additional bit is “11”. Therefore, AC
The coefficients r _{2 0} and r _{1 1} are encoded as “1101111”.

FIG. 27 shows an example of the above Huffman code.
As shown in FIG. 27, 64 pieces of pixel data of an 8 × 8 pixel block can be encoded into continuous encoded data (compressed data).

As shown in FIG. 28, each compressed data is composed of a variable length Huffman code and a variable length additional bit.
The length of the Huffman code is called the Huffman code length, and the length of the additional bit is called the additional bit length. The sum of the Huffman code length and the additional bit length is called the total bit length. The Huffman code length and the additional bit length differ depending on each compressed data.

(5) Conventional Huffman Decoding Circuit FIG. 29 is a block diagram showing the configuration of the main part of a conventional Huffman decoding circuit.

In FIG. 29, 3 consecutive compressed data
Two bits are provided in parallel to a 32-bit register 1 having a latch enable function. The output data of the register 1 is applied to the 32-bit register 2 which also has a latch enable function. The output data of the register 2 and the output data of the register 1 are provided in parallel to the 64-bit barrel shifter 3. The barrel shifter 3 has a function of bit shifting the supplied data up to 32 bits.

The first 16 bits of the data held in the barrel shifter 3 are given to the memory table 12. The memory table 12 outputs the total bit length data TBL, the end-of-block code EOB, the run length data RL, the additional bit length data ABL, and the Huffman code length data HCL based on the supplied 16-bit data.

The 5-bit adder 6 has the memory table 1
The total bit length data TBL given from 2 is cumulatively added to calculate the shift amount of the barrel shifter 3. The adder 6 carries the carry signal C when the cumulative addition result becomes 32 or more.
Output R. The 5-bit register 7 latches the output data of the adder 6. The decoder 8 decodes the output data of the register 7 and controls the shift amount of the barrel shifter 3.

On the other hand, the register 9 has a memory table 12
The end-of-block code EOB, the run length data RL, the additional bit length data ABL, the Huffman code length data HCL, and the leading 32-bit data held in the barrel shifter 3 are latched. The additional bit extraction circuit 10 extracts the additional bit AB from the 32-bit data based on the additional bit length data ABL and the Huffman code length data HCL output from the register 9.

The control circuit 13 receives the carry signal CR from the adder 6, applies the latch enable signal LE1 to the registers 1 and 2, and supplies the latch enable signal LE2 to the registers 7 and 9. Also, the control circuit 1
3 generates a control signal CNT which controls the read operation of the memory table 12.

A clock signal CK is given to the registers 1, 2, 7, 9 and the control circuit 13, and a reset signal RST is given to the register 7 and the control circuit 13.
Is given.

Next, the operation of the Huffman decoding circuit shown in FIG. 29 will be described. First, the reset signal RST resets the control circuit 13 and clears the contents of the register 7 to zero. As a result, the shift amount of the barrel shifter 3 output from the decoder 8 is set to 0.

First, the DC Huffman code (Huffman code corresponding to the DC coefficient) is decoded. The enable signal LE1 from the control circuit 13 causes the register 32 to latch the first 32 bits of the compressed data, and the register 1 to latch the next 32 bits of the compressed data. As a result, the first 32-bit compressed data output from the register 2 and the next 32-bit compressed data output from the register 1 are provided to the barrel shifter 3.

The first 16 bits of the compressed data in the barrel shifter 32 are used as an address signal in the memory table 12.
Given to. Control signal C from control circuit 13
In response to NT, the read operation of memory table 12 is performed. As a result, Huffman code length data H corresponding to the DC Huffman code included in the leading 16-bit data
CL, additional bit length data ABL and total bit length data TBL are output. The total bit length data TBL is given to the adder 6 and cumulatively added.

Next, the control circuit 13 supplies the latch enable signal LE2 to the registers 7 and 9. The register 7 latches the cumulative addition result of the adder 6 in response to the latch enable signal LE2 and gives it to the decoder 8. The decoder 8 decodes the cumulative addition result from the register 7 and supplies the barrel shifter 3 with a shift signal indicating a shift amount. The barrel shifter 3 bit-shifts the compressed data by the cumulative addition result.

The register 9 has a latch enable signal LE.
Huffman code length data HCL and additional bit length data AB read from the memory table 12 in response to
The 32-bit data output from L and the barrel shifter 3 is latched and output. Additional bit extraction circuit 10
Extracts the additional bit AB from the 32-bit data based on the Huffman code length data HCL and the additional bit length data ABL. In this way, the decoding of the DC Huffman code is completed.

Similarly, the AC Huffman code (Huffman code corresponding to the AC coefficient) is decoded. When decoding the AC Huffman code, from the memory table 12,
Huffman code length data HCL, additional bit length data AB
L, run length data RL and total bit length data T
BL is output.

Meanwhile, when the cumulative addition result of the adder 6 becomes 32 or more, the adder 6 outputs the carry signal CR. The control circuit 13 gives the latch enable signal LE1 to the register 1 in response to the carry signal CR. As a result, new 32-bit compressed data is given to the latter 32 bits of the barrel shifter 3.

In this way, until the end of block code EOB is read from the memory table 12, the AC
Decoding of the Huffman code continues.

Additional bit AB obtained as described above
The quantized DCT coefficient can be obtained based on the run length data RL.

[0055]

In the conventional Huffman decoding circuit, the speed of Huffman coding is determined by the operating speed of the hardware constituting the barrel shifter 3, the adder 6, the decoder 8 and the memory table 12. Of these, the access time of the memory table 12 is an obstacle to speeding up the Huffman coding process.

Further, the memory table 12 is provided with 16-bit compressed data equal to the maximum code length of the Huffman code as an address signal. Therefore, the address space of the memory table 12 is 2 ¹⁶ words. In this way, the capacity of the memory table 12 becomes very large.

Therefore, the required memory capacity is reduced by dividing the memory table by the first half bit and the latter half bit of the maximum code length. However, even then, a memory capacity of about 5 to 6 times the number of Huffman codes is required. Thus, the circuit scale of the Huffman decoding circuit is still large.

An object of the present invention is to provide a Huffman decoding circuit and a Huffman decoding method capable of performing Huffman decoding processing at high speed with a small circuit scale.

[0059]

A Huffman decoding circuit according to the present invention comprises a plurality of decoding means and a selection means. The plurality of Huffman codes are classified into a plurality of groups based on the code length. The plurality of decoding means are provided corresponding to the plurality of groups and decode the Huffman codes in the corresponding groups. The selecting means selects and activates one of the plurality of decoding means based on the number of consecutive bits having the same value from the leading bit of the given Huffman code.

The plurality of decoding means are a first decoding means composed of a memory element and a second decoding means composed of a logic circuit.
May be included in the decoding means. The first decoding means is assigned to a group containing a Huffman code having a long code length, and the second decoding means is assigned to a group containing a Huffman code having a short code length.

Each of the plurality of decoding means outputs the additional bit length and the total bit length. It may further include an arithmetic means for calculating the Huffman code length from the additional bit length and the total bit length.

The Huffman decoding method according to the present invention includes the following steps. A plurality of Huffman codes are classified into a plurality of groups based on the code length. A plurality of decoding means for decoding a given Huffman code is assigned to each of a plurality of groups. One of the plurality of decoding means is selected and activated based on the number of consecutive bits having the same value from the leading bit of the given Huffman code.

The plurality of decoding means are a first decoding means composed of a memory element and a second decoding means composed of a logic circuit.
May be included in the decoding means. The first decoding means is assigned to a group containing a long code length Huffman code, and the second decoding means is assigned to a group containing a short code length Huffman code.

[0064]

In the Huffman decoding circuit and the Huffman decoding method according to the present invention, a plurality of Huffman codes are classified into a plurality of groups based on the code length, and a plurality of decoding means are respectively assigned to the plurality of groups. This reduces the overall capacity and circuit scale of the decoding means.

Focusing on the property of the Huffman code, the same value continues from the leading bit to a certain bit in the Huffman code having a long code length, and different values coexist from the leading bit to a bit in the Huffman code having a short code length.

By utilizing this property, it is possible to determine which group the given Huffman code belongs to based on the number of consecutive bits having the same value from the first bit, and the decoding means assigned to the group can be determined. You can choose.

In the Huffman coding method, a Huffman code having a short code length is assigned to data having a high appearance frequency, and a Huffman code having a long code length is assigned to data having a low appearance frequency.

On the other hand, the decoding means constituted by the logic circuit has a high operation speed but a relatively large circuit scale. On the other hand, the decoding means constituted by the memory device does not operate at a high speed, but the circuit scale is relatively small.

Therefore, when a Huffman code with a short code length that frequently appears is decoded by a logic circuit that can operate at high speed, and a Huffman code with a long code length that rarely appears is decoded by a memory element having a small circuit scale, the whole is obtained. A decoding circuit that can operate at high speed and has a small circuit scale can be obtained.

Further, if arithmetic means for calculating the Huffman code length from the additional bit length and the total bit length is further provided, compared with the case where each decoding means outputs the additional bit length, the total bit length and the Huffman code length, The circuit scale of each decoding means is reduced.

[0071]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A Huffman decoding circuit and a Huffman decoding device according to an embodiment of the present invention will be described below in detail with reference to the drawings.

In the Huffman decoding circuit and the Huffman decoding method of this embodiment, as shown in FIG. 1, the Huffman code is divided into three groups G1 and G based on the Huffman code length.
2, G3.

A Huffman code having a Huffman code length of 6 bits or less is assigned to the group G1, and the Huffman code length is 7
Huffman codes with more than 12 bits and less than 12 bits are group G
Assigned to 2 and Huffman code length is 13 bits or more 16
Sub-bit Huffman codes are assigned to group G3.

The Huffman code has the following regularity. In the Huffman code of 6 bits or less, at least one “0” exists from the first bit to the fourth bit.
In addition, in the Huffman code of 7 bits or more and 12 bits or less, the first bit to the fourth bit are all "1" and at least one "0" exists from the fifth bit to the last bit. Further, in the Huffman code of 13 bits or more and 16 bits or less, the first bit to the ninth bit are all "1".

By utilizing this regularity, it is possible to determine which of the groups G1, G2 and G3 the given Huffman code belongs to.

The Huffman codes belonging to the group G1 are decoded by the decoding circuit composed of a high-speed logic circuit, and the Huffman codes belonging to the groups G2 and G3 are RAM.
It is decoded by a memory table composed of (random access memory).

As shown in FIG. 2, the decoding circuit receives the first to sixth bits of the compressed data including the Huffman code of the group G1.

With respect to the Huffman code of the group G2, since the first bit to the fourth bit are all "1", one Huffman code can be specified by using the fifth bit to the twelfth bit. Therefore, the memory table is provided with the fifth to twelfth bits of the compressed data including the Huffman code of the group G2 as the address signal.

With respect to the Huffman code of the group G3, since the first bit to the ninth bit are all "1", one Huffman code can be specified by using the tenth bit to the sixteenth bit. Therefore, the memory table is provided with the 10th to 16th bits of the compressed data including the Huffman code of the group G3 as the address signal.

By grouping as described above, the circuit scale of the decoding circuit becomes smaller and the memory capacity required for each memory table becomes smaller.

Further, by decoding the Huffman code of 6 bits or less, which frequently appears, by the high-speed logic circuit, the processing speed of the entire Huffman decoding circuit is increased. According to the simulation, the appearance frequency of Huffman code of 6 bits or less is about 85%.

FIG. 3 is a block diagram showing the configuration of the main part of the Huffman decoding circuit according to this embodiment.

The Huffman decoding circuit of FIG. 3 differs from the Huffman decoding circuit of FIG. 29 in that a decoder 4 and a decoder block 5 are provided instead of the memory table 12, and a control circuit 11 is provided instead of the control circuit 13. That is the point.

In FIG. 3, 32 bits of compressed data are applied in parallel to a 32-bit register 1 having a latch enable function. The output data of register 1 is
Similarly, it is applied to a 32-bit register 2 having a latch enable function. The output data of the register 2 and the output data of the register 1 are the 64-bit barrel shifter 3
Given in parallel to. The barrel shifter 3 has a function of bit shifting the supplied data up to 32 bits.

The first 16 bits of the data held in the barrel shifter 3 are the decoder 4 and the decoder block 5.
Given to. The decoder 4 includes a Huffman code (group G1) of 6 bits or less or a Huffman code of 7 bits or more and 12 bits or less (group G2) based on the 16-bit data supplied from the barrel shifter 3. It is detected whether the Huffman code including 13 bits or more and 16 bits or less (group G3) is included, and decoder selection signals DS1, DS2, DS3 are generated.

However, the decoder 4 receives the decoder selection signals DS1 and DS1 when the DC code selection signal DCSL supplied from the control circuit 11 is in the active state.
2, do not output DS3.

The decoder block 5 decodes 16-bit data given from the barrel shifter 3 in response to the decoder selection signals DC1, DC2, DC3, and outputs the total bit length data TBL and the end-of-block code EO.
B, run length data RL, additional bit length data ABL and Huffman code length data HCL are generated.

The 5-bit adder 6 cumulatively adds the total bit length data TBL supplied from the decoder block 5 to calculate the shift amount of the barrel shifter 3. The adder 6 outputs the carry signal CR when the cumulative addition result is 32 or more. The 5-bit register 7 latches the output data of the adder 6. The decoder 8 decodes the output data of the register 7 and controls the shift amount of the barrel shifter 3.

On the other hand, the register 9 is used in the decoder block 5
The end-of-block code EOB, the run length data RL, the additional bit length data ABL, the Huffman code length data HCL, and the leading 32-bit data output from the barrel shifter 3 are latched. The additional bit extraction circuit 10 extracts the additional bit AB from the 32-bit data output from the barrel shifter 3 based on the additional bit length data ABL and the Huffman code length data HCL output from the register 9.

The control circuit 11 receives the decoder selection signal DC1 generated by the decoder 4 and the carry signal CR output from the adder 6, and receives the registers 1 and 2.
The latch enable signal LE1 to the registers 7 and 9
To the latch enable signal LE2.

The clock signal CK is applied to the registers 1, 2, 7, 9 and the control circuit 11, and the reset signal RST is applied to the register 7 and the control circuit 11.
Is given.

FIG. 4 is a block diagram showing a detailed structure of the decoder block 5. The decoder block 5 includes a decoding circuit 51, a memory table 52, and a memory table 5.
3, a decode circuit 54, a subtractor 55, a 3-state buffer 56, and a gate circuit 57.

The decode circuits 51 and 54 are composed of logic circuits capable of high speed operation, and the memory tables 52 and 54
53 is composed of a RAM.

The decoding circuit 51 is supplied with the first bit to the sixth bit of the 16-bit compressed data.
The memory table 52 stores the fifth 16-bit compressed data.
Bits to the 12th bit are given. The memory table 53 is provided with the 10th to 16th bits of 16-bit compressed data. Decoding circuit 54
Is given from the first bit to the 9th bit of 16-bit compressed data.

The decoding circuit 51 uses the decoder selection signal D
AC Huffman code of 6 bits or less, which is activated in response to S1, is decoded to generate Huffman code length data HCL,
The run length data RL, the additional bit length data ABL, the total bit length data TBL and the end of block code EOB are output. The memory table 52 is activated in response to the decoder selection signal DC2 and has 7 bits or more and 12 bits or more.
The AC Huffman code of less than or equal to bits is decoded and the run length data RL, the additional bit length data ABL and the total bit length data TBL are output. Memory table 53
Is activated in response to the decoder selection signal DS3,
Run length data RL and additional bit length data AB are decoded by decoding AC Huffman codes of 3 bits or more and 16 bits or less.
It outputs L and total bit length data TBL.

The decoding circuit 54 uses the DC code selection signal D
It is activated in response to CSL, decodes the DC Huffman code, and outputs Huffman code length data HCL, additional bit length data ABL, and total bit length data TBL.

The subtractor 55 has the memory tables 52 and 53.
The additional bit length data ABL is subtracted from the total bit length data TBL output from the Huffman code length data HCL. The Huffman code length data HCL output from the subtractor 55 is supplied to the 3-state buffer 56. On the other hand, the decoder selection signal DC2 is applied to one input terminal of the gate circuit 57, and the decoder selection signal DS3 is applied to the other input terminal. The 3-state buffer 56 is controlled by the output signal of the gate circuit 57.

When either of the decoder selection signals DC2 and DC3 becomes active, the 3-state buffer 56
Becomes the same state, and when both the decoder selection signals DC2 and DC3 become inactive, the 3-state buffer 56 becomes high impedance.

Next, the operation of the Huffman decoding circuit shown in FIGS. 3 and 4 will be described. First, the reset signal RS
The control circuit 11 is reset by T, and the content of the register 7 is cleared to 0. As a result, the shift amount of the barrel shifter 3 output from the decoder 8 is set to 0.

First, the DC Huffman code is decoded. The control circuit 11 uses the DC code selection signal CDS
Make L active. At this time, the decoder selection signals DC1, DC2, DC3 generated from the decoder 4 are all inactive. As a result, the decode circuit 54 in the decoder block 5 is activated, and the decode circuit 51 and the memory tables 52 and 53 are activated.
Becomes inactive.

Then, the latch enable signal LE1 from the control circuit 11 causes the register 32 to latch the first 32 bits of the compressed data and the register 1 to latch the next 32 bits of the compressed data. As a result, the barrel shifter 3 is provided with the first 32-bit compressed data output from the register 2 and the next 32-bit compressed data output from the register 1.

The first 16 bits of the compressed data in the barrel shifter 32 are given to the decoder 4 and the decoder block 5. The decoding circuit 51 in the decoder block 5 decodes the DC Huffman code included in the 16-bit compressed data, and the Huffman code length data HCL, the additional bit length data ABL, and the total bit length data T.
BL is output. The total bit length data TBL is given to the adder 6 and cumulatively added.

Control circuit 11 controls the timing of latch enable signals LE1 and LE2 in response to a decoding end signal (not shown) output from decoder 4. Upon receiving the decoding end signal from the decoder 4, the control circuit 11 immediately applies the latch enable signal LE2 to the registers 7 and 9.

The register 7 has a latch enable signal LE.
In response to 2, the cumulative addition result of the adder 6 is latched and given to the decoder 8. The decoder 8 decodes the cumulative addition result from the register 7 and supplies the barrel shifter 3 with a shift signal indicating a shift amount. The barrel shifter 3 bit-shifts the compressed data by the cumulative addition result.

The register 9 has a latch enable signal LE.
In response to 2, the Huffman code length data HCL and the additional bit length data AB output from the decoder block 5.
The 32-bit compressed data output from L and the barrel shifter 3 is latched and output. The additional bit extraction circuit 10 is based on the Huffman code length data HCL and the additional bit length data ABL given from the register 9.
The additional bits AB are extracted from the 32-bit compressed data and output.

When the decoding of the DC Huffman code is completed, the control circuit 11 outputs the DC code selection signal DCS.
Make L inactive. Thereby, the decoder 4
Are decoder selection signals DS1, DS2, D based on 16-bit compressed data provided from the barrel shifter 3.
One of S3 is made active.

When the decoder selection signal DS1 becomes active, the decoding circuit 51 in the decoder block 5 decodes the AC Huffman code included in the compressed data, and the Huffman code length data HCL and run length data R are obtained.
L, additional bit length data ABL and total bit length data TBL are output.

When the decoder selection signal DS2 becomes active, the memory table 52 in the decoder block 5 is
From, the run length data RL, the additional bit length data ABL and the total bit length data TBL corresponding to the AC Huffman code included in the compressed data are read.

When the decoder selection signal DC3 becomes active, the memory table 53 in the decoder block 5 is
From, the run length data RL, the additional bit length data ABL and the total bit length data TBL corresponding to the AC Huffman code included in the compressed data are read.

When the decoder selection signals DS2 and DS3 are in the active state, the enable signal SE applied from the control circuit 11 to the subtractor 55 is in the active state and the subtractor 55 is activated. The subtractor 55 calculates the additional bit length data A from the total bit length data TBL.
BL is subtracted and the Huffman code length data HCL is given to the 3-state buffer 56. At this time, since the output signal of the gate circuit 57 is in the active state, the 3-state buffer 56 is in the same state. Therefore, the Huffman code length data HCL is output from the 3-state buffer 56. Since the calculation of the subtracter 55 is performed in parallel with the calculation of the adder 6, the calculation time of the subtractor 55 does not increase. By calculating the Huffman code length data HCL using the subtractor 55 in this manner, the memory capacity of the memory tables 52 and 53 can be reduced.

Upon receiving the decoding end signal from the decoder 4, the control circuit 11 gives the latch enable signal LE2 to the registers 7 and 9. The register 7 latches the cumulative addition result of the adder 6 and gives it to the decoder 8 in response to the latch enable signal LE2. The decoder 8
The cumulative addition result given from the register 7 is decoded and the barrel shifter 3 is given a shift signal indicating the shift amount. The barrel shifter 3 bit-shifts the compressed data by the cumulative addition result.

The register 9 has a latch enable signal LE.
In response to 2, the Huffman code length data HCL, the additional bit length data ABL and the run length data RL output from the decoder block 5 and the 32-bit compressed data output from the barrel shifter 3 are latched and output.
The additional bit extraction circuit 10 extracts and outputs the additional bit length AB from the 32-bit compressed data based on the Huffman code length data HCL and the additional bit length data ABL output from the register 9.

Meanwhile, when the cumulative addition result of the adder 6 becomes 32 or more, the adder 6 outputs the carry signal CR. The control circuit 11 gives the latch enable signal LE1 to the register 1 in response to the carry signal CR. As a result, new 32-bit compressed data is given to the latter 32 bits of the barrel shifter 3.

In this way, the decoding of the AC Huffman code is continued until the end of block code EOB is output from the decoding circuit 51 in the decoder block 5.

FIG. 5 is a circuit diagram showing the structure of the decoder 4. Decoder 4 includes a 4-input AND gate 41, a 6-input NAND gate 42 and a 2-input NAND gate 43.

The four input terminals of the AND gate 41 are
The first bit to the fourth bit of the 16-bit compressed data are given. The decoder selection signal DS1 is output from the output terminal of the AND gate 41. NAND gate 42
The output signal of the AND gate 41 is applied to one of the input terminals of, and the remaining five input terminals are applied with the fifth to ninth bits of the 16-bit compressed data. N
Decoder selection signal DS from the output terminal of the AND gate 42
3 is output. The output signal of NAND gate 42 is applied to one input terminal of NAND gate 43, and the output signal of AND gate 41 is applied to the other input terminal. A decoder selection signal DS2 is output from the output terminal of the NAND gate 43.

If at least one of the first bit to the fourth bit of the 16-bit compressed data is "0", A
Decoder selection signal DS1 output from the ND gate 41
Becomes low level (active state). At this time, N
Decoder selection signal DS output from AND gate 42
3 and the decoder selection signal DS2 output from the NAND gate 43 becomes high level (inactive state).

When all the bits from the first bit to the fourth bit of the 16-bit compressed data are "1", the decoder selection signal DS1 output from the AND gate 41 becomes high level. At this time, if at least one of the fifth bit to the ninth bit of the 16-bit compressed data is "0", the decoder selection signal DS3 output from the NAND gate 42 becomes high level and is output from the NAND gate 43. The decoder selection signal DS2 is turned to a low level (active state).

If all the bits from the first bit to the ninth bit of the 16-bit compressed data are "1", the decoder selection signal DS1 output from the AND gate 41 becomes high level and the decoder selection signal output from the NAND gate 42 is selected. The signal DS3 becomes low level (active state). At this time, the decoder selection signal DS2 output from the NAND gate 43 becomes high level.

FIG. 6 is a block diagram showing the structure of the decoder circuit 51. The decoder circuit 51 is a combination circuit 51.
It includes as many 19-bit registers 512 as there are Huffman codes of 1 and 6 bits or less.

The combination circuit 511 is supplied with the first bit to the sixth bit of the 16-bit compressed data.
Each register 512 has a Huffman code length data HCL corresponding to an AC Huffman code, a run length data RL, an additional bit length data ABL, and a total bit length data TB.
L is stored in advance. Also, the end of block code E
The OB is prestored in the corresponding register 512.

According to the data supplied to the combination circuit 511, one of the plurality of registers 512 is selected, and the Huffman code length data HCL from the selected register 512 is selected.
The run length data RL, the additional bit length data ABL and the total bit length data TBL are output. When the end of block code EOB is stored in the selected register 512, the end of block code EOB is also output.

FIG. 7 is a block diagram showing the structure of the memory table 52. The memory table 52 comprises a static RAM 521.

Address line 5 of static RAM 521
The fifth to twelfth bits of the 16-bit compressed data are given to 22 as an address signal.

Since the address signal of the static RAM 521 is 8 bits, the address space of the static RAM 521 is 2 ⁸ words. Static RAM 5
At each address of 21, the run length data RL corresponding to the Huffman AC code, the additional bit length data ABL, and the total bit length data TBL are stored in advance.

Address line 5 of static RAM 521
The run length data RL, the additional bit length data ABL, and the total bit length data TBL are read out via the data line 523 according to the data supplied to 22.

FIG. 8 is a block diagram showing the structure of the memory table 53. The memory table 53 is composed of a static RAM 531.

Address line 5 of static RAM 531
To 32, the 10th to 16th bits of 16-bit compressed data are given as address signals.

Since the address signal given to the static RAM 531 is 7 bits, the static RAM
The address space of 531 is 2 ⁷ words. At each address of the static RAM 531, the run length data RL corresponding to the AC Huffman code, the additional bit length data ABL
And the total bit length data TBL is stored in advance.

Address line 5 of static RAM 531
According to the data supplied to 32, run length data RL, additional bit length data ABL and total bit length data TBL are read out via data line 533.

FIG. 9 is a block diagram showing the structure of the decoding circuit 54. The decoding circuit 54 is a combination circuit 54.
1 and a number of 14-bit registers 542 equal to the number of DC Huffman codes.

The combination circuit 541 is supplied with the first bit to the ninth bit of the 16-bit compressed data.
The Huffman code length data HCL and the additional bit length data ABL corresponding to the DC Huffman code are stored in each register 542.
And the total bit length data TBL is stored in advance.

One of the plurality of registers 542 is selected in accordance with the data given to the combination circuit 541, and the Huffman code length data HCL from the selected register 542,
The additional bit length data ABL and the total bit length data TBL are output.

The operation speed of decode circuit 51 shown in FIG. 6 and decode circuit 54 shown in FIG. 9 is one digit faster than the operation speed of memory table 52 shown in FIG. 7 and memory table 53 shown in FIG. . By configuring the decoding block 5 as in the above embodiment,
The processing speed of the Huffman decoding circuit becomes high and the circuit scale becomes small.

[0135]

As described above, according to the present invention, by classifying a plurality of Huffman codes into a plurality of groups based on the code length and assigning a plurality of decoding means to the plurality of groups, respectively, the decoding means as a whole. The capacity and the circuit scale of are reduced.

Further, by decoding a Huffman code having a short code length having a high appearance frequency by a logic circuit capable of high-speed operation, and by decoding a Huffman code having a long code length having a low appearance frequency by a memory element having a small circuit scale. As a whole, a Huffman decoding circuit that can operate at high speed and has a small circuit scale can be obtained.

Furthermore, by further providing an arithmetic means for calculating the Huffman code length from the additional bit length and the total bit length, the circuit scale of each decoding means can be further reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing grouping of Huffman codes in a Huffman decoding circuit and a Huffman decoding method according to an embodiment of the present invention.

FIG. 2 is a diagram showing bits given to a decoding circuit or a memory table when decoding a Huffman code belonging to each group.

FIG. 3 is a block diagram showing a configuration of a main part of a Huffman composite circuit according to an embodiment of the present invention.

4 is a block diagram showing a detailed configuration of a decoder block included in the Huffman decoding circuit of FIG.

5 is a circuit diagram showing a detailed configuration of a decoder included in the Huffman compounding circuit of FIG.

6 is a block diagram showing a configuration of a decoding circuit included in the decoder block of FIG.

7 is a block diagram showing a configuration of a memory table included in the decoder block of FIG.

8 is a block diagram showing a configuration of a memory table included in the decoder block of FIG.

9 is a block diagram showing a configuration of a decoding circuit included in the decoder block of FIG.

FIG. 10 is a block diagram showing the basic configuration of a DCT image data compression system.

FIG. 11 is a diagram showing how image data is divided into blocks.

FIG. 12 is a diagram showing an 8 × 8 pixel block and a DCT-transformed block.

FIG. 13 is a diagram showing an example of 8 × 8 pixel blocks and DCT coefficients.

FIG. 14 is a diagram showing a relationship among a DCT coefficient, a quantized DCT coefficient, and a quantization table.

FIG. 15 is a diagram showing an example of a quantization table.

FIG. 16 is a diagram showing an example of quantized DCT coefficients.

FIG. 17 is a flowchart showing Huffman coding of DC coefficients.

FIG. 18 is a diagram for explaining a DC difference value.

FIG. 19 is a diagram showing grouping of DC difference values.

FIG. 20 is a diagram showing a Huffman code table for DC difference values.

FIG. 21 is a diagram showing additional bits for a DC difference value.

FIG. 22 is a flow diagram showing Huffman coding of AC coefficients.

FIG. 23 is a diagram for explaining zigzag scanning.

FIG. 24 is a diagram showing grouping of AC coefficients.

FIG. 25 is a diagram showing a Huffman code table for AC coefficients.

FIG. 26 is a diagram showing additional bits for AC coefficients.

FIG. 27 is a diagram illustrating an example of Huffman coding.

FIG. 28 is a diagram showing a structure of compressed data.

FIG. 29 is a block diagram showing a configuration of a main part of a conventional Huffman compounding circuit.

[Explanation of symbols]

 1, 2 registers 3 barrel shifter 4 decoder 5 decoder block 6 adder 7 register 8 decoder 9 register 10 additional bit extraction circuit 11 control circuit 51, 54 decoding circuit 52, 53 memory table 55 subtracter 56 3 state buffer 57 gate circuit DS1, DS2, DS3 Decoder selection signal DCSL DC code selection signal LE1, LE2 Latch enable signal HCL Huffman code length data ABL Additional bit length data RL Run length data EOB End of block code AB additional bit The same code in each figure is the same or corresponding part Indicates.

Claims (5)

[Claims] 1. A plurality of decoding means for classifying a plurality of Huffman codes into a plurality of groups on the basis of code lengths, the plurality of decoding means being provided corresponding to the plurality of groups and decoding the corresponding Huffman codes respectively. A Huffman decoding circuit comprising: a selection unit that selects and activates one of the plurality of decoding units based on the number of consecutive bits of the same value from the leading bit of a given Huffman code. 2. The plurality of decoding means includes a first decoding means including a memory element and a second decoding means including a logic circuit, and the first decoding means includes a group including a Huffman code having a long code length. 2. The Huffman decoding circuit according to claim 1, wherein the second decoding means is assigned to a group including a Huffman code having a short code length. 3. Each of the plurality of decoding means outputs decoding information including an additional bit length and a total bit length, and further comprises arithmetic means for calculating a Huffman code length from the additional bit length and the total bit length. Claim 1 including
Huffman decoding circuit described. 4. A plurality of Huffman codes are classified into a plurality of groups based on code lengths, a plurality of decoding means for decoding a given Huffman code are assigned to each of the plurality of groups, and the head of the given Huffman code is divided. A Huffman decoding method, wherein one of the plurality of decoding means is selected and activated based on the number of consecutive bits having the same value. 5. The plurality of decoding means includes a first decoding means including a memory element and a second decoding means including a logic circuit, and the first decoding means is divided into a group including a Huffman code having a long code length. 5. The Huffman decoding method according to claim 4, wherein the second decoding means is assigned to a group including a Huffman code having a short code length.