JPH0613825A - Automatic gain control circuit - Google Patents

Automatic gain control circuit

Info

Publication number
JPH0613825A
JPH0613825A JP18991192A JP18991192A JPH0613825A JP H0613825 A JPH0613825 A JP H0613825A JP 18991192 A JP18991192 A JP 18991192A JP 18991192 A JP18991192 A JP 18991192A JP H0613825 A JPH0613825 A JP H0613825A
Authority
JP
Japan
Prior art keywords
signal
output signal
automatic gain
amplitude
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18991192A
Other languages
Japanese (ja)
Inventor
Kiyoshi Amasawa
清 天沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Faurecia Clarion Electronics Co Ltd
Original Assignee
Clarion Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Clarion Co Ltd filed Critical Clarion Co Ltd
Priority to JP18991192A priority Critical patent/JPH0613825A/en
Publication of JPH0613825A publication Critical patent/JPH0613825A/en
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To attain a stable automatic gain control operation for the frequency of a sine wave of the input signal even though the frequency is approximate to the frequency of the amplitude fluctuation by accelerating the responsiveness of the automatic gain control. CONSTITUTION:An output signal S0 is inputted to a phase shifter 4 and a signal S0' having a phase delayed by 120 deg. is obtained. The signal S0' is inputted to a phase shifter 4' and a signal S0'' having a phase delayed by 120 deg. is obtained. Thus these signals S0, S0' and S0'' have the phase difference of 120 deg. respectively. Then the signals S0, S0' and S0'' are inputted to the detectors 3, 3' and 3'' respectively to undergo the half cycle detection. These detection outputs S3, S3' and S3'' are synthesized by a synthesizer 5, and an output S4 is obtained. The output S4 is equal to a perfect DC component and serves as the control signal of a variable attenuator 1. This signal S4 instantaneously has an answer to the signal S0.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は自動利得制御回路(Auto
Gain Control Circuit;以下、AGC回路と記す)に
関する。
The present invention relates to an automatic gain control circuit (Auto
Gain Control Circuit; hereinafter referred to as AGC circuit).

【0002】[0002]

【従来の技術】従来方式のAGC回路の構成を図3のブ
ロック図に示す。図3においては、1は可変アッテネー
タ、2はアンプ、3は検波器、6はLPF(ローパスフ
ィルタ)である。図3のAGC回路では、出力信号S0
は検波器3に入力され(例えば、ダイオード等)によっ
て半波又は両波検波を行なう。ここで、検波出力S3に
はリップル成分があるため直流以外の高周波成分をLP
F6で除去し、直流成分S4を得る。そして、直流成分
S4によって、可変アッテネータ1を制御しその出力S
i’を低下させ、この閉ループにより出力S0が一定に
なるようにコントロールしている。
2. Description of the Related Art The structure of a conventional AGC circuit is shown in the block diagram of FIG. In FIG. 3, 1 is a variable attenuator, 2 is an amplifier, 3 is a detector, and 6 is an LPF (low-pass filter). In the AGC circuit of FIG. 3, the output signal S0
Is input to the detector 3 (for example, a diode or the like) to perform half-wave or double-wave detection. Here, since the detection output S3 has a ripple component, high-frequency components other than DC are
It is removed at F6 to obtain the DC component S4. Then, the variable attenuator 1 is controlled by the DC component S4 and its output S
i ′ is lowered and the output S0 is controlled to be constant by this closed loop.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、上記の
ような従来のAGC回路において、入力信号Siが周波
数fiの正弦波で振幅(エンベローブ)が変動する時、
振幅変動に対して追従性が悪いという問題点があった。
具体的には、図3のLPF6は図4のような利得と位相
特性を有している。そして、図4においてθは通常90
°以上となる。振幅変動の周波数をfNとすると、その
周波数でのLPF6の位相遅れがほぼ“0”の時はAG
C回路は十分な追従性を有するが、LPF6は周波数f
iの信号を除去するので、周波数fiによりLPF6の
位相遅れ“0”の上限周波数が決定される。従って、周
波数fNが周波数fiに接近している時はLPF6での
位相遅れの影響を受けることとなる。この影響がある場
合、出力信号S0は図5の波線で示すように一定振幅と
ならず、振幅が不足したりオーバーシュート等の現象が
生ずる。
However, in the conventional AGC circuit as described above, when the amplitude (envelope) of the input signal Si changes with a sine wave of the frequency fi,
There is a problem that the followability with respect to amplitude fluctuation is poor.
Specifically, the LPF 6 of FIG. 3 has the gain and phase characteristics as shown in FIG. And in FIG. 4, θ is usually 90.
° or more. When the frequency of amplitude fluctuation is fN, when the phase delay of the LPF 6 at that frequency is almost "0", AG
Although the C circuit has sufficient followability, the LPF 6 has a frequency f
Since the signal i is removed, the upper limit frequency of the phase delay "0" of the LPF 6 is determined by the frequency fi. Therefore, when the frequency fN is close to the frequency fi, it is affected by the phase delay in the LPF 6. When this influence is exerted, the output signal S0 does not have a constant amplitude as shown by the broken line in FIG. 5, and phenomena such as insufficient amplitude and overshoot occur.

【0004】本発明は上記問題点に鑑みてなされたもの
であり、自動利得制御の応答性を速めることにより、入
力時のサイン波の周波数と振幅変動の周波数が接近して
いても入力信号のサイン波の周波数の安定的な自動利得
制御動作をなし得る自動利得制御回路を提供することを
目的とする。
The present invention has been made in view of the above problems, and by accelerating the response of the automatic gain control, even if the frequency of the sine wave at the time of input and the frequency of the amplitude fluctuation are close, An object of the present invention is to provide an automatic gain control circuit capable of performing a stable automatic gain control operation of the frequency of a sine wave.

【0005】[0005]

【課題を解決するための手段】上記の目的を達成するた
めに、本発明の自動利得制御回路は、振幅成分が変動す
る入力信号を入力し、信号の振幅を所定の制御信号によ
り制御して出力信号を得ると共に、出力信号を振幅検波
して直流成分を得て所定の制御信号とし、出力信号が一
定振幅となるように制御する自動利得制御回路におい
て、出力信号に複数の所定の位相差を与えそれぞれ位相
差出力信号を得る位相差出力手段と、各位相差出力信号
をそれぞれ振幅検波しそれぞれ直流成分を得る検波手段
と、それぞれの直流成分を合成し制御信号としての合成
出力信号を得る合成手段と、を有することを特徴とす
る。
To achieve the above object, the automatic gain control circuit of the present invention inputs an input signal whose amplitude component varies and controls the amplitude of the signal by a predetermined control signal. In the automatic gain control circuit that obtains the output signal, amplitude-detects the output signal, obtains the DC component, and sets it as the predetermined control signal, and controls so that the output signal has a constant amplitude. A phase difference output means for obtaining a phase difference output signal, a wave detecting means for amplitude-detecting each phase difference output signal to obtain a DC component, and a synthesis output signal as a control signal for synthesis And means.

【0006】[0006]

【作用】上記構成により本発明の自動利得制御回路は、
位相差出力手段により出力信号に複数の所定の位相差を
与えそれぞれ位相差出力信号を得て検波手段に出力し、
検波手段が各位相差出力信号をそれぞれ振幅検波しそれ
ぞれ直流成分を得る。そして、合成手段がそれぞれの直
流成分を合成し制御信号としての合成出力信号を出力
し、出力した合成出力信号を制御信号として入力信号の
振幅を制御し一定振幅の出力信号を得る。この場合、制
御信号である合成出力信号は上述の出力信号の変化に対
して瞬時に応答することができる。
With the above structure, the automatic gain control circuit of the present invention is
A plurality of predetermined phase differences are given to the output signal by the phase difference output means to obtain each phase difference output signal and output to the detection means,
The detection means amplitude-detects each phase difference output signal to obtain a DC component. Then, the synthesizing means synthesizes the respective DC components and outputs a synthesized output signal as a control signal, and controls the amplitude of the input signal by using the outputted synthesized output signal as a control signal to obtain an output signal having a constant amplitude. In this case, the combined output signal, which is the control signal, can instantly respond to the change in the above-mentioned output signal.

【0007】[0007]

【実施例】図1は、本発明の自動利得回路の一実施例の
構成を示すブロック図である。図1において、1は可変
アッテネータ、2はアンプ、3,3’,3”は検波手段
としての検波器、4,4’は位相差出力手段としての1
20°の移相器、5は合成手段としての合成器である。
また、図2は検波器への入力(図2A)及び検波出力
(図2B)の信号波形図である。
1 is a block diagram showing the configuration of an embodiment of an automatic gain circuit according to the present invention. In FIG. 1, 1 is a variable attenuator, 2 is an amplifier, 3, 3'and 3 "are detectors as detecting means, and 4 and 4'are 1 as phase difference outputting means.
The 20 ° phase shifter 5 is a combiner as a combining means.
FIG. 2 is a signal waveform diagram of the input (FIG. 2A) and the detection output (FIG. 2B) to the detector.

【0008】図1において、出力信号S0は移相器4に
入力され、120°位相の遅れた信号S0’を得る。更
にS0’を移相器4’に入力し更に120°位相の遅れ
た信号S0’を得る。この結果、信号S0,S0’,S
0”は図2Aに示すようにそれぞれが120°の位相差
を有する信号となる。次に、これら信号S0,S0’,
S0”をそれぞれ検波器3,3’,3”に入力し半サイ
クル検波を行なうと、図2Bに示すように信号S0,S
0’,S0”の半サイクル成分S3,S3’,S3”が
得られる。これらの半サイクル成分S3,S3’,S
3”を合成器5で合成すると、図2Bにおいて太線で示
す、合成出力S4が得られる。この合成出力S4は入力
信号Siの振幅変動成分であるfiの周波数成分を含ま
ない完全な直流成分となる。
In FIG. 1, the output signal S0 is input to the phase shifter 4, and a signal S0 'having a 120 ° phase delay is obtained. Further, S0 'is input to the phase shifter 4', and a signal S0 'delayed by 120 ° in phase is obtained. As a result, the signals S0, S0 ', S
0 ″ is a signal having a phase difference of 120 ° as shown in FIG. 2A. Next, these signals S0, S0 ′,
When S0 "is input to the detectors 3, 3 ', 3" and half-cycle detection is performed, signals S0, S are generated as shown in FIG. 2B.
Half cycle components S3, S3 ', S3 "of 0', S0" are obtained. These half cycle components S3, S3 ', S
2 "is combined by the combiner 5, a combined output S4 shown by a thick line in FIG. 2B is obtained. This combined output S4 is a complete DC component that does not include the frequency component of fi which is the amplitude fluctuation component of the input signal Si. Become.

【0009】また、図2Aの点線に示したように時間t
において振幅がP1からP1’に増大するとS0’はP
2からP2’へ、S0”はP3からP3’へ増大するよ
うに変化する。これを検波すると図5Bの点線で示した
ように、S3’はP2からP2’へ、S3”はP3から
P3’へ変化する。従って、合成器5の出力信号は図2
Bの太線で示したP4からP4’に変化することとな
る。このように、本発明では可変アッテネータ1の制御
信号であるS4は出力信号S0に対して瞬時に応答する
ことができる。
Further, as shown by the dotted line in FIG. 2A, the time t
When the amplitude increases from P1 to P1 'at S0' becomes P
2 to P2 ′, S0 ″ changes so as to increase from P3 to P3 ′. When this is detected, S3 ′ changes from P2 to P2 ′ and S3 ″ changes from P3 to P3, as shown by the dotted line in FIG. 5B. Change to '. Therefore, the output signal of the synthesizer 5 is as shown in FIG.
It changes from P4 shown by the thick line of B to P4 '. As described above, in the present invention, the control signal S4 of the variable attenuator 1 can instantly respond to the output signal S0.

【0010】なお、移相器としてはオールパスフィルタ
や、損失を補償したR・C又はR・Lの微・積分器など
を用いることができる。また、本実施例において検波器
は半サイクル検波を行なうものとして説明したが、両波
検波してもよい。また、本実施例では120°の移相器
を用いているがこれに限られることなく、更に細分化し
た移相器を用いてもよい。
As the phase shifter, an all-pass filter or a loss / compensated R / C or R / L fine / integrator can be used. Further, in the present embodiment, the detector has been described as performing half-cycle detection, but it is also possible to detect both waves. Further, although the phase shifter of 120 ° is used in the present embodiment, the phase shifter is not limited to this, and a further subdivided phase shifter may be used.

【0011】[0011]

【発明の効果】以上説明したように本発明によれば、検
波した信号をLPFで濾過する必要がないので、AGC
の制御の応答遅れが大幅に改善される。そして入力信号
の周波数fiとそのエンベローブの変動周波数fNとが
接近してても十分安定したAGC動作を行なわせること
ができる。
As described above, according to the present invention, since it is not necessary to filter the detected signal with the LPF, the AGC is possible.
The response delay of control is significantly improved. Even if the frequency fi of the input signal and the fluctuation frequency fN of the envelope are close to each other, it is possible to perform a sufficiently stable AGC operation.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の自動利得制御回路の一実施例の構成を
示すブロック図である。
FIG. 1 is a block diagram showing a configuration of an embodiment of an automatic gain control circuit of the present invention.

【図2】検波器への入力(部分図A)及び検波出力(部
分図B)の信号波形図である。
FIG. 2 is a signal waveform diagram of an input (partial view A) and a detection output (partial view B) to a detector.

【図3】従来の方式による自動利得制御回路の構成を示
すブロック図である。
FIG. 3 is a block diagram showing a configuration of an automatic gain control circuit according to a conventional method.

【図4】従来方式の自動利得制御回路に用いられている
LPFの周波数特性図である。
FIG. 4 is a frequency characteristic diagram of an LPF used in a conventional automatic gain control circuit.

【図5】従来方式の自動利得制御回路の応答特性図であ
る。
FIG. 5 is a response characteristic diagram of a conventional automatic gain control circuit.

【符号の説明】[Explanation of symbols]

1 可変アッテネータ 2 アンプ 3,3’,3” 検波器(検波手段) 4,4’ 移相器(位相差出力手段) 5 合成器(合成手段) DESCRIPTION OF SYMBOLS 1 Variable attenuator 2 Amplifier 3,3 ', 3 "Detector (detection means) 4,4' Phase shifter (phase difference output means) 5 Combiner (combining means)

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 振幅成分が変動する入力信号を入力し、
該信号の振幅を所定の制御信号により制御して出力信号
を得ると共に、該出力信号を振幅検波して直流成分を得
て前記所定の制御信号とし、前記出力信号が一定振幅と
なるように制御する自動利得制御回路において、前記出
力信号に複数の所定の位相差を与えそれぞれ位相差出力
信号を得る位相差出力手段と、前記各位相差出力信号を
それぞれ振幅検波しそれぞれ直流成分を得る検波手段
と、前記それぞれの直流成分を合成し制御信号としての
合成出力信号を得る合成手段と、を有することを特徴と
する自動利得制御回路。
1. Inputting an input signal whose amplitude component varies,
The amplitude of the signal is controlled by a predetermined control signal to obtain an output signal, and the output signal is amplitude-detected to obtain a direct current component to be the predetermined control signal, and the output signal is controlled to have a constant amplitude. In the automatic gain control circuit, a phase difference output means for giving a plurality of predetermined phase differences to the output signal to obtain a phase difference output signal, and a detection means for detecting the amplitude of each phase difference output signal to obtain a DC component respectively. And a synthesizing means for synthesizing the respective DC components to obtain a synthetic output signal as a control signal.
JP18991192A 1992-06-24 1992-06-24 Automatic gain control circuit Pending JPH0613825A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18991192A JPH0613825A (en) 1992-06-24 1992-06-24 Automatic gain control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18991192A JPH0613825A (en) 1992-06-24 1992-06-24 Automatic gain control circuit

Publications (1)

Publication Number Publication Date
JPH0613825A true JPH0613825A (en) 1994-01-21

Family

ID=16249276

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18991192A Pending JPH0613825A (en) 1992-06-24 1992-06-24 Automatic gain control circuit

Country Status (1)

Country Link
JP (1) JPH0613825A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0425665B1 (en) * 1988-05-10 1994-08-24 Teijin Limited Method for assaying chondrocalcine
JPH11202959A (en) * 1997-11-04 1999-07-30 Robert Bosch Gmbh Charge pump

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0425665B1 (en) * 1988-05-10 1994-08-24 Teijin Limited Method for assaying chondrocalcine
JPH11202959A (en) * 1997-11-04 1999-07-30 Robert Bosch Gmbh Charge pump

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