JPH0613569A - Semiconductor memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce an area of a memory cell and to increase capacitance of a capacitor. CONSTITUTION:A DRAM has stacked memory cells 3A, 3B in which capacitors 2a, 2b are superposed on transistor elements 1a, 1b, and has a structure in which the other capacitor 2b is superposed on an upper surface of the one capacitor 2a of adjacent memory cells 3A, 3B through an interlayer insulating film 20. Thus, since an area of a superposed part of both capacitors 2a, 2b is commonly provided, an effective area of the cell can be increased, and the capacitance of the capacitor can be increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device (hereinafter referred to as DR) in which stack type memory cells (also referred to as stacked capacitor cells) are arranged in an array on a semiconductor substrate.
AM) and a method of manufacturing the same, and more particularly to a capacitor structure in a stack type memory cell.

[0002]

2. Description of the Related Art Generally, it is known that when the area of a memory cell in a DRAM is reduced, the storage capacity of a capacitor is reduced, and it is vulnerable to a soft error due to alpha rays. Therefore, various DRAMs having a memory cell structure having a sufficiently large storage capacity even if the memory cell area is small have been proposed in the past, and an example thereof is shown in FIG.

FIG. 2 shows an example of a conventional DRAM using a stacked cell structure and shows the basic structure of two memory cells. This is a stack type memory cell 3 (3A, 3B) composed of one switching MOS transistor 1 (1a, 1b) on a semiconductor substrate 11 and a capacitor 2 (2a, 2b) stacked on this element.
2 has an array structure in which the capacitors 2a and 2b of adjacent memory cells 3A and 3B are formed independently of each other without overlapping each other, as shown in FIG. ing.

That is, the lower electrode 31 of one capacitor 2a is formed on the region of the MOS transistor 1a, and the lower electrode 32 of the other capacitor 2b is formed on the region of the transistor 1b, and each lower electrode 3 is formed.
After forming the capacitor insulating films 33 and 34 on the capacitors 1 and 32, a common upper electrode 36 is formed so as to cover the insulating films.

In FIG. 2, 12 is an element isolation field oxide film formed on the semiconductor substrate 11, 13 is a gate electrode also serving as a word line for each of the transistors 1a and 1b, 1
3 _W is a word line wired under each capacitor 2a, 2b of the adjacent memory cells, and 26 is each MOS transistor 1a, 1b formed on the interlayer insulating film 36.
It is a bit line that connects the two.

Such a stack type memory cell structure is
Compared with the normal planar cell structure, the capacitor 2 can be formed on the switching MOS transistor 1 so as to be overlapped with each other and not curved, so that the capacitor capacitance can be increased and the cell area can be reduced. There is.

[0007]

However, in the DRAM using the conventional tacked cell structure, the lower electrodes of the adjacent memory cells are formed in the regions of the independent transistors, and the respective electrodes are covered with the common upper electrode. Since the structure is formed as described above, the memory cell area is reduced as the chip is reduced, and it is difficult to secure the capacitor capacity. In other words, due to the reduction of the chip area, it is unavoidable to reduce the capacitance of the capacitor, and attempts have been made to increase the surface area of the lower electrode by increasing the film thickness of the lower electrode. However, effective capacitance expansion cannot be achieved. There was a problem.

In view of the above points, the present invention has been made to solve the above problems, and provides a DRAM using a stack type memory cell capable of reducing the memory cell area and the capacitor capacity. The purpose is to get.

[0009]

In order to achieve the above object, a DRAM and a method of manufacturing the same according to the present invention have an interlayer insulating film interposed on the upper surface of a capacitor of one memory cell in adjacent memory cells. By overlapping the capacitors of the other memory cell, the capacitor area is expanded.

[0010]

Therefore, in the stack type memory cell according to the present invention, the effective memory cell area can be increased by superposing the capacitors of the adjacent memory cells, so that the capacitance of the capacitor can be increased.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the embodiments shown in the drawings. FIG. 1 is a basic process sectional view for explaining an embodiment of a method of manufacturing a DRAM according to the present invention, and two memory cells are shown for convenience of explanation. In this embodiment, first, as shown in FIG. 1 (a), a silicon semiconductor substrate 11 is selectively oxidized by a normal LOCOS method to form a field oxide film 12 for element isolation, and then a threshold voltage of a transistor is determined. In order to do so, a channel-doped impurity is implanted into the element region by an ion implantation method.

Next, polysilicon to be a gate electrode (or word line) is deposited by a low pressure CVD method, impurities are implanted by a diffusion method or the like, and dry etching is performed to form a gate electrode 13 and a word line 13 _W. . Then, by using the gate electrode 13 as a mask, a predetermined impurity is ion-implanted to form the source / drain region portion 14, so that each of the switching MOS transistors 1 (1a, 1b) can be formed by the same method as the conventional method. Form.
Then, a CVD oxide film 1 is formed on the substrate as an interlayer insulating film.
After depositing 5 and patterning thereof, the contact hole 16 is selectively opened by dry etching.

Next, the polysilicon to be the lower electrode (storage node) of the capacitor 2a constituting one memory cell 3A of the adjacent memory cells is decompressed by CVD.
Then, the impurities are implanted and then patterned, and the lower electrode 17 of one of the capacitors 2a is bent and formed as shown in the drawing. Next, a nitride film is deposited on the lower electrode 17 by a low pressure CVD method to a thickness of about 10 nm, and the surface of the nitride film is further oxidized in a water vapor atmosphere to form a composite film of an oxide film and a nitride film as a capacitor insulating film 18.

Thereafter, doped polysilicon to be the upper electrode (cell plate) is deposited by the CVD method and patterned to form the upper electrode 19 of one of the capacitors 2a. As a result, as shown in Fig. 1 (a),
A stack type memory cell 3A is formed by stacking capacitors 2a on the region of one MOS transistor 1a in the adjacent memory cells.

Then, as shown in FIG. 1B, an interlayer insulating film 20 such as an oxide film is formed on the substrate including the one capacitor 2a by the CVD method. Then, Fig. 1 (c)
As shown in, the MOS that constitutes the other memory cell 3B
After opening the contact hole 21 in the region of the transistor 1b, polysilicon is deposited by the low pressure CVD method to form the lower electrode 22 of the other by the same method as the one of the capacitor 2a described above, and the insulation for the capacitor is formed. The film 23 is formed.

Further, doped polysilicon is deposited by the CVD method to form the other upper electrode 24,
A capacitor 2 is formed on the other MOS transistor 1b region.
A stack type memory cell 3B in which b is stacked is formed. Thereafter, the interlayer insulating film 25 and the bit line 26 are formed thereon by a generally known method, thereby completing the stack type memory cell structure as shown in the drawing. The same or corresponding parts in the drawings are denoted by the same reference numerals.

The DR of this embodiment manufactured in this way
AM is formed by stacking a capacitor 2a forming one stack type memory cell 3A of adjacent memory cells with a capacitor 2b forming another stack type memory cell 3B via an interlayer insulating film 20. You can
As a result, the area of the overlapping portion of both capacitors is shared, and therefore, compared with the conventional cell structure shown in FIG.
It is possible to increase the memory cell area.

Although the memory cell structure overlapping in the bit line direction is shown in the embodiment of FIG. 1, a memory cell structure overlapping in the word line direction can be similarly formed.

[0019]

As described above, according to the present invention, in the DRAM composed of the stack type memory cells, the capacitors of the adjacent memory cells are superposed, so that the effective memory cell area is reduced. There is an effect that it can be expanded and the capacity of the capacitor can be increased.

[Brief description of drawings]

FIG. 1 is a process sectional view illustrating an embodiment of a method of manufacturing a DRAM according to the present invention.

FIG. 2 is a structural cross-sectional view showing an example of a conventional DRAM memory cell.

[Explanation of symbols]

 1a, 1b Switching MOS transistors 2a, 2b Capacitors 3A, 3B Stack type memory cell 11 Semiconductor substrate 12 Element isolation field oxide film 20 Interlayer insulating film

Claims (2)

[Claims] 1. A memory array in which a stack type memory cell composed of a transistor element and a capacitor stacked on the transistor element is arranged in an array on a semiconductor substrate, and one of the memory cells in the adjacent memory cells is provided. A semiconductor memory device having a structure in which a capacitor of another memory cell is superposed on an upper surface of a capacitor of the cell with an interlayer insulating film interposed. 2. A method of manufacturing a semiconductor memory device according to claim 1, wherein after forming each transistor element on a semiconductor substrate, one capacitor of adjacent memory cells is stacked and formed on the transistor element. A step of forming an interlayer insulating film on the upper surface of the one capacitor with the lower electrode for the capacitor of the other memory cell, and a step of forming the capacitor of the other memory cell on the interlayer insulating film in an overlapping manner. And a method for manufacturing a semiconductor memory device.