JPH0613524A - Package - Google Patents
PackageInfo
- Publication number
- JPH0613524A JPH0613524A JP4193214A JP19321492A JPH0613524A JP H0613524 A JPH0613524 A JP H0613524A JP 4193214 A JP4193214 A JP 4193214A JP 19321492 A JP19321492 A JP 19321492A JP H0613524 A JPH0613524 A JP H0613524A
- Authority
- JP
- Japan
- Prior art keywords
- package
- external connection
- printed wiring
- wiring board
- pins
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/79—Apparatus for Tape Automated Bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、電子部品を搭載し、外
部接続ピンを介してプリント配線板上に表面実装される
パッケージに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package on which electronic parts are mounted and which is surface-mounted on a printed wiring board via external connection pins.
【0002】[0002]
【従来の技術】従来から電子部品を搭載し、外部接続ピ
ンを介してプリント配線板上に表面実装されるパッケー
ジとしては、数百本の外部接続端子となる導体ピンを有
するパッケージが使用されている。2. Description of the Related Art Conventionally, a package having several hundreds of conductor pins to be external connection terminals has been used as a package on which electronic parts are mounted and which is surface-mounted on a printed wiring board through external connection pins. There is.
【0003】[0003]
【発明が解決しようとする課題】上記従来の導体ピンを
有するパッケージでは、その搭載された電子部品と電気
的に接続したリードは、個別に形成された外部接続用の
導体ピンを介してプリント配線板上の回路に接続され
る。すなわち、ほぼ電子部品の端子数だけ外部接続用の
導体ピンが必要となり、導体ピンの品質管理の困難化、
パッケージへの取付け工数の増加、さらにはそのパッケ
ージをプリント配線板上に実装する技術の困難化を招い
ている。In the conventional package having the conductor pins, the leads electrically connected to the mounted electronic components are printed wiring through the individually formed conductor pins for external connection. Connected to the circuit on the board. That is, as many conductor pins for external connection as the number of terminals of electronic parts are required, which makes quality control of conductor pins difficult.
This increases the number of man-hours for mounting the package and further makes it difficult to mount the package on a printed wiring board.
【0004】本発明は、搭載する電子部品の大型化・高
集積化、さらにはマルチチップ化によるパッケージの大
型化・高集積化により顕著に現れる微小かつ膨大な数の
導体ピンの品質管理の困難化、パッケージへの取付け工
数の増加、さらにはそのパッケージをプリント配線板上
に実装する技術の困難化を改善することを目的とする。According to the present invention, it is difficult to control the quality of a minute and enormous number of conductor pins, which remarkably appears due to the increase in the size and the degree of integration of the electronic parts to be mounted and the increase in the size and the degree of integration of the package by the multichip. The purpose is to improve the number of man-hours required for mounting the package on a printed wiring board, and to increase the number of man-hours for mounting the package on a printed wiring board.
【0005】[0005]
【課題を解決するための手段】本発明は、電子部品を搭
載し、外部接続ピンを介してプリント配線板上に表面実
装されるパッケージにおいて、前記電子部品と電気的に
接続したリードの外端部と接続する前記外部接続ピンを
互いに絶縁された複数の芯導体を形成したフレキシブル
なピンとしたことを特徴とするパッケージを構成とす
る。SUMMARY OF THE INVENTION According to the present invention, in a package in which an electronic component is mounted and surface-mounted on a printed wiring board via an external connection pin, outer ends of leads electrically connected to the electronic component. A package is characterized in that the external connection pin connected to the portion is a flexible pin formed with a plurality of core conductors insulated from each other.
【0006】[0006]
【作用】本発明は、電子部品と電気的に接続したリード
の外端部と接続する外部接続ピンを互いに絶縁された複
数の芯導体を形成したピンとしたことにより、電子部品
の複数の端子に個別に接続された複数のリードが一つの
外部接続ピンに収集されるから、パッケージに形成せね
ばならない外部接続用の導体ピン数を極めて少なくでき
る。しかも、電子部品と電気的に接続したリードの外端
部と接続する前記外部接続ピンを互いに絶縁された複数
の芯導体を形成したフレキシブルなピンとしたことによ
り、膨大な総端子数を持つ電子部品を搭載しながらも、
プリント配線板上に容易に実装ができ、電子機器に与え
られる機械的衝撃やパッケージとこれを実装するプリン
ト配線板との間の熱膨張率の差による応力歪みに影響さ
れないため、搭載する電子部品の大型化・高集積化、さ
らにはマルチチップ化によるパッケージの大型化・高集
積化に対応できる。According to the present invention, the external connection pins connected to the outer ends of the leads electrically connected to the electronic parts are formed with a plurality of core conductors which are insulated from each other. Since the plurality of leads that are individually connected are collected in one external connection pin, the number of external connection conductor pins that must be formed in the package can be extremely reduced. Moreover, since the external connection pin connected to the outer end of the lead electrically connected to the electronic component is a flexible pin formed with a plurality of core conductors insulated from each other, an electronic component having an enormous total number of terminals While mounting
It can be easily mounted on a printed wiring board, and is not affected by mechanical shock given to electronic equipment or stress strain due to the difference in coefficient of thermal expansion between the package and the printed wiring board on which it is mounted. It is possible to cope with the large size and high integration of the package, and also the large size and high integration of the package due to the multi-chip.
【0007】[0007]
【実施例】以下実施例をあげて、本発明を具体的に説明
する。EXAMPLES The present invention will be specifically described with reference to the following examples.
【0008】(実施例1)この実施例はLSI搭載用パ
ッケージであり、これを図1および図2に基づき説明す
る。図1は、完成したパッケージの縦断面図であり、図
2は、この実施例に使用した外部接続ピンの上面図、側
面図、底面図である。まず、この実施例は、以下の工程
により形成された。 1:厚さ50ミクロンメータのフレキシブルな弗素系樹
脂材からなる中絶縁層を介して上下に厚さ35ミクロン
メータの銅箔からなるリードを形成するとともに、上下
リードを保護する厚さ50ミクロンメータの弗素系樹脂
からなる上下の絶縁層を形成した基板をリール トゥ
リール(reel to reel)法により複数連続
して形成する工程、2:パッケージ外に熱を放散する表
面を陽極酸化したアルミニウムキャップにLSIを搭載
し、キャップを下リードを保護する下絶縁層上に接着す
るとともに、中絶縁層を介して上下に形成した上リード
と下リードの内端部とLSI上の端子とを金−錫合金結
合あるいははんだ等の接続導体を介して電気的に接続す
る工程、3:キャップ内に封止樹脂を充填し、LSIと
上記上下リードの内端部を樹脂封止する工程。4:上下
に2分された金型でパッケージ外周の中絶縁層を挟みこ
み、この金型内にフィラー等を入れて前記キャップに熱
膨張率を合わせた弗素系樹脂を加圧・加熱充填すること
により、キャップの側面と封止樹脂を覆うとともに、パ
ッケージの四隅にプリント配線板上の接続パッドと外部
接続ピン下端面との間隔を制御する凸部をもつ図1の成
形樹脂が示す構造とする工程、5:100本の外部接続
ピンを挿入し、各外部接続ピンの上端部に露出させた4
本の芯導体と上下リードの4本の外端部とを接続導体を
介して電気的に接続する工程、6:外部接続ピンの挿入
・接続部に、前記3の工程で使用した封止樹脂か、前記
4の工程で使用した成形樹脂と同種であってフィラー含
有量が少なく若干柔軟性のある封止樹脂を充填し、接続
部を封止するとともに外部接続ピンを固定する工程、
7:複数連続した基板を個々に分離し、端子数400と
なるLSI2個を搭載した外部接続ピン数100のパッ
ケージを完成する工程。なお、上記外部接続ピンは、図
2に示すように、直径0.3ミリメートルの銅線からな
る4本の芯導体を各々が電気的に絶縁されるように柔軟
性のある弗素系樹脂で覆い、全体としては、直径1.5
ミリメートル、長さ5.0ミリメートルの柔軟性のある
フレキシブルな円筒構造となっている。特に、外部接続
ピン上端部には、上記上下リードの外端部との電気的接
続のために個々の芯導体上面が絶縁体の壁を介して露出
している。また、外部接続ピン下端部には、上記プリン
ト配線板上の接続パッドと電気的接続のために芯導体下
面が露出するとともに側面が絶縁体の壁を介して露出し
ている。なお、上記外部接続ピンは、電線コード状に線
として形成しリールに巻かれた材料を、適当な寸法に切
断するとともに、絶縁体や芯導体の素材に合わせ波長・
出力を調節できるレーザで所望の形状に加工した。(Embodiment 1) This embodiment is an LSI mounting package, which will be described with reference to FIGS. 1 and 2. FIG. 1 is a vertical sectional view of the completed package, and FIG. 2 is a top view, a side view, and a bottom view of an external connection pin used in this embodiment. First, this example was formed by the following steps. 1: A 50-micrometer-thick structure that protects the upper and lower leads by forming the upper and lower leads made of copper foil with a thickness of 35-micrometers through the middle insulating layer made of a flexible fluorine-based resin material with a thickness of 50-micrometers. Reel to the substrate with the upper and lower insulating layers made of fluorine resin
Step of forming a plurality of continuous reel-to-reel methods, 2: LSI is mounted on an aluminum cap whose surface that dissipates heat outside the package is anodized, and the cap is on the lower insulating layer that protects the lower lead. A step of bonding and electrically connecting the inner ends of the upper and lower leads formed above and below via the middle insulating layer and the terminals on the LSI via a gold-tin alloy bond or a connecting conductor such as solder. 3: A step of filling the cap with the sealing resin and sealing the LSI and the inner ends of the upper and lower leads with the resin. 4: The middle insulating layer of the package outer periphery is sandwiched between the upper and lower molds, and a filler or the like is put into the molds to pressurize and heat-fill the cap with a fluorine-based resin having a matched coefficient of thermal expansion. As a result, the structure shown by the molding resin in FIG. 1 is provided, which covers the side surface of the cap and the sealing resin, and has convex portions at four corners of the package for controlling the distance between the connection pad on the printed wiring board and the lower end surface of the external connection pin. Step 5: Insert 100: 100 external connection pins and expose the upper end of each external connection pin 4
Step of electrically connecting the core conductor of the four and the four outer ends of the upper and lower leads through the connecting conductor, 6: the sealing resin used in the step 3 at the insertion / connection part of the external connection pin Or a step of filling a sealing resin having the same kind as the molding resin used in the above step 4 but a small amount of filler content and a little flexibility to seal the connection portion and fix the external connection pin,
7: A step of individually separating a plurality of continuous substrates and completing a package having two external LSIs having 100 terminals and 100 external connection pins. As shown in FIG. 2, the external connection pins are formed by covering four core conductors made of a copper wire having a diameter of 0.3 mm with a flexible fluorine resin so as to electrically insulate each of the four core conductors. , Overall, diameter is 1.5
It has a flexible cylindrical structure with a millimeter and a length of 5.0 millimeters. In particular, the upper surfaces of the external connection pins are exposed at the upper surfaces of the individual core conductors through the walls of the insulator for electrical connection with the outer ends of the upper and lower leads. Further, at the lower end portion of the external connection pin, the lower surface of the core conductor is exposed for electrical connection with the connection pad on the printed wiring board, and the side surface is exposed through the wall of the insulator. In addition, the external connection pin is formed into a wire in the shape of an electric wire cord and wound on a reel, and cut into a suitable size.
It was processed into a desired shape with a laser whose output could be adjusted.
【0009】[0009]
【発明の効果】本発明は、微小かつ膨大な数の導体ピン
の品質管理の困難化、パッケージへの取付け工数の増
加、さらにはそのパッケージをプリント配線板上に実装
する技術の艱難化を改善し、搭載する電子部品の大型化
・高集積化、さらにはマルチチップ化によるパッケージ
の大型化・高集積化を可能とする顕著な効果を奏する。Industrial Applicability The present invention improves the difficulty in quality control of minute and enormous numbers of conductor pins, the increase in the number of man-hours for mounting to a package, and the difficulty in mounting the package on a printed wiring board. However, there is a remarkable effect that the size and the degree of integration of the mounted electronic components can be increased, and the size and the degree of integration of the package can be increased by the multi-chip.
【図1】本発明の実施例であるパッケージの拡大断面図
である。FIG. 1 is an enlarged cross-sectional view of a package that is an embodiment of the present invention.
【図2】本発明の実施例で使用した外部接続ピンの上面
図、側面図、底面図である。FIG. 2 is a top view, a side view, and a bottom view of an external connection pin used in an example of the present invention.
Claims (1)
プリント配線板上に表面実装されるパッケージにおい
て、前記電子部品と電気的に接続したリードの外端部と
接続する前記外部接続ピンを互いに絶縁された複数の芯
導体を形成したフレキシブルなピンとしたことを特徴と
するパッケージ。1. A package in which an electronic component is mounted and which is surface-mounted on a printed wiring board via an external connection pin, wherein the external connection pin is connected to an outer end portion of a lead electrically connected to the electronic component. Is a flexible pin having a plurality of core conductors insulated from each other.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19321492A JP3146288B2 (en) | 1992-06-26 | 1992-06-26 | package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19321492A JP3146288B2 (en) | 1992-06-26 | 1992-06-26 | package |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0613524A true JPH0613524A (en) | 1994-01-21 |
JP3146288B2 JP3146288B2 (en) | 2001-03-12 |
Family
ID=16304206
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19321492A Expired - Fee Related JP3146288B2 (en) | 1992-06-26 | 1992-06-26 | package |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3146288B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007080863A1 (en) * | 2006-01-16 | 2007-07-19 | Nec Corporation | Semiconductor device, printed wiring board mounted with such semiconductor device, and connection structure for those |
US8178226B2 (en) | 2005-03-17 | 2012-05-15 | Nec Corporation | Film-covered electric device and method of manufacturing same |
US9954087B2 (en) | 2005-12-28 | 2018-04-24 | Renesas Electronics Corporation | Field effect transistor, and multilayered epitaxial film for use in preparation of field effect transistor |
-
1992
- 1992-06-26 JP JP19321492A patent/JP3146288B2/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8178226B2 (en) | 2005-03-17 | 2012-05-15 | Nec Corporation | Film-covered electric device and method of manufacturing same |
US9954087B2 (en) | 2005-12-28 | 2018-04-24 | Renesas Electronics Corporation | Field effect transistor, and multilayered epitaxial film for use in preparation of field effect transistor |
WO2007080863A1 (en) * | 2006-01-16 | 2007-07-19 | Nec Corporation | Semiconductor device, printed wiring board mounted with such semiconductor device, and connection structure for those |
US8125081B2 (en) | 2006-01-16 | 2012-02-28 | Nec Corporation | Semiconductor device, printed wiring board for mounting the semiconductor device and connecting structure for these |
Also Published As
Publication number | Publication date |
---|---|
JP3146288B2 (en) | 2001-03-12 |
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