JPH06133293A - Highly efficient coding device - Google Patents

Abstract

PURPOSE:To prevent a dynamic range from being increased as required or over by detecting the dynamic range based on coefficient data converted into an absolute value when the coefficient data generated at cosine transformation are subject to ADRC coding. CONSTITUTION:An absolute value processing circuit 12 converts coefficient data into an absolute value. The absolute value coefficient data are fed to a detection circuit 14, in which a maximum value MAX and a minimum value MIN of a block comprising coefficient data of the same degree are detected. A subtractor circuit 15 detects a dynamic range DR of the block. The coefficient data with the minimum value MIN eliminated therefrom at a subtractor circuit 16 are fed to a quantization circuit 17, in which the data are quantized in response to the dynamic range DR. Then the quantization code DT and the dynamic range DR from the quantization circuit 17 are sent (recorded).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid high efficiency coding apparatus for ADRC coding coefficient data obtained by transform coding such as cosine transform.

[0002]

2. Description of the Related Art A digital VTR for recording a digital video signal on a magnetic tape by a rotary head is known. Since the amount of information in a digital video signal is large,
High-efficiency coding for compressing the amount of transmitted data is often adopted. ADRC (Adaptive Dynamic Range)
Various high-efficiency codings such as Coding) and DCT (Discrete Cosine Transform) have been proposed.

ADRC is disclosed in, for example, JP-A-61-1449.
As disclosed in Japanese Patent Publication No. 89, a high-efficiency coding is performed in which a dynamic range defined by the maximum value and the minimum value of a plurality of pixels included in a two-dimensional block is obtained, and coding is performed in accordance with this dynamic range. is there. ADRC
As one of the above, variable length ADRC has been proposed. AD
RC is calculated for each two-dimensional block in which the dynamic range DR (difference between the maximum value MAX and the minimum value MIN) is (8 lines × 8 pixels = 64 pixels), for example. Further, the minimum level (minimum value) in the block is removed from the input pixel data. The pixel data after this minimum value removal is converted into a representative level. This quantization is performed by the dynamic range D detected in four level ranges corresponding to a bit number smaller than the original quantization bit number, for example, 2 bits.
This is a process of dividing R, detecting the level range to which each pixel data in the block belongs, and generating a code signal indicating this level range. Therefore, the 8-bit data of each pixel is compressed into 2 bits and transmitted.

The variable length ADRC prepares, for example, 0, 1, 2, 3 bits (0 bit means not transmitting a quantization code) as the number of quantization bits, and when the dynamic range DR is large, The number of quantization bits is increased, and when it is small, the number of quantization bits is reduced.

A digital VTR using a magnetic tape,
In a disc recording device or the like using a disc-shaped recording medium, it is usual that one field or one frame of video data is recorded on a plurality of tracks. However, as described above, when the variable length output is formed, the amount of data in these predetermined periods varies. Therefore, a buffering process is required to keep the amount of data in the predetermined period below the target value.

As a buffering system of variable length ADRC, the applicant of the present application forms a frequency distribution of a cumulative dynamic range as described in Japanese Patent Application No. 61-257586, and this frequency distribution is used. , A threshold value for determining the number of allocated bits prepared in advance is applied to obtain the amount of generated information for a predetermined period, for example, one frame period, and control is performed so that the amount of generated information does not exceed the target value. Are proposing things.

As another method of high-efficiency coding, there is known transform coding in which a screen is divided into blocks each having a predetermined number of pixels and a linear transformation is performed for each block on a transform axis that matches the characteristics of the original image signal. ing. Hadamard transform, discrete cosine transform, and the like are known as transform coding. The coefficient data obtained by the cosine transform is quantized, and the quantized output is converted into a code signal of a predetermined number of bits by run length coding and Huffman coding.

In order to make it easier to further compress the coefficient data obtained by the cosine transform and to make the coefficient data into data of a predetermined bit rate that matches the capacity of the transmission line, the applicant of the present application has adopted the cosine transform. A hybrid high-efficiency coding which combines ADDR and ADRC is proposed (Japanese Patent Application No. 62-270564 and Japanese Patent Application No. 63-245227).
No.).

In the previously proposed hybrid high efficiency coding, the coefficient data is quantized based on human visual characteristics. In other words, for the DC component in the coefficient data, the maximum allowable distortion is fixedly determined, and the DC component is quantized so that the distortion falls below this, and the AC component deteriorates when the distortion is applied. Is quantized in small steps for coefficient data (low-frequency components) that are easily noticeable, and is quantized in coarse steps for coefficient data (high-frequency components) in which deterioration is less noticeable.

[0010]

FIG. 4A shows (4 × 4).
It is an example of the value of each pixel of DCT block BL1 and BL2 of a pixel. The properties of the two blocks are similar,
The phase is reversed. Therefore, when the blocks BL1 and BL2 are cosine transformed, coefficient data blocks CB1 and CB2 as shown in FIG. 4B are obtained. That is, the polarities of the AC coefficients of the same order in both blocks are (-3
7, 37) and (15, -15), the polarities are inverted. When ADRC encoding collectively the coefficient data of the same degree, these opposite polarity coefficient data are collected. In ADRC, the dynamic range of the assembled coefficient data is detected, and quantization is performed by adapting to this dynamic range. When the dynamic range DR is large, the quantization step is large and the quantization error is large in the case of fixed length ADRC, and the coefficient data is (-37, 37) or (in the case of variable length ADRC. 1
Although there are only two types (5, -15), the number of allocated bits increases.

Therefore, an object of the present invention is to achieve high efficiency in which the problem that the detected dynamic range becomes large due to the phase inversion in the hybrid coding in which the transform coding and the ADRC coding are combined is prevented. An object is to provide an encoding device.

[0012]

SUMMARY OF THE INVENTION According to the present invention, a block forming circuit for dividing image data into sub-blocks consisting of a predetermined number of pixel data and dividing the image data into main blocks consisting of a plurality of sub-blocks. And an orthogonal transform coding circuit that generates coefficient data by orthogonal transform coding the output data of the block formation circuit for each sub block, and a sub block that collects coefficient data from the orthogonal transform circuit that has the same degree in the main block. A circuit forming an ADRC block having a block size, and at least A in the coefficient data.
An AD that converts the C component into an absolute value, detects the dynamic range of the ADRC block based on the absolute value coefficient data, and quantizes the coefficient data by adapting to the dynamic range.
A high-efficiency coding apparatus having an RC coding circuit.

[0013]

The coefficient data from the cosine transform circuit 3 is supplied to the coefficient separation circuit 4, and in the coefficient separation circuit 4, the DC component coefficient data DC and the AC component coefficient data AC1 to AC15.
And separated. Within the main block, coefficient data of the same degree are collected to form a sub block. AC coefficient data of this sub-block is ADRC encoders 5 _{1 to} 5
_Is supplied to ₁₅ and the dynamic range DR of the sub-block
And ADRC encoded. In this case, the dynamic range is detected from the coefficient data converted into the absolute value, and it is prevented that the dynamic range becomes large due to the polarity inversion.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1 showing the overall configuration of this embodiment, 1 is an input terminal to which a digital image signal is supplied. The digital image signal is supplied to the blocking circuit 2, and the order of the input digital image signal is changed to the block configuration for the cosine transform. For example, one frame image is divided into DCT blocks of (4 × 4) pixels. A main block (hereinafter referred to as a hybrid block) is composed of a plurality of DCT blocks. The size of the hybrid block is, for example, (4 ×
4) It is a DCT block.

The output signal of the blocking circuit 2 is supplied to the cosine transform circuit 3, and the cosine transform circuit 3 carries out a two-dimensional cosine transform by the same processing as the conventional one. A (4 × 4) coefficient table corresponding to the DCT block size from the cosine transform circuit 3 is obtained. Of course, the block size of the cosine transform is not limited to this.

The coefficient data from the cosine transform circuit 3 is supplied to the coefficient separation circuit 4. The coefficient separation circuit 4 separates and outputs a total of 16 pieces of coefficient data of the DC component DC and the AC component of the same order (same order). The sub-block coefficient data from the separation circuit 6 is the ADRC encoder 5 ₁ ,
5 ₂ , ... 5 ₁₆ are supplied respectively. These AD
The encoded output generated by the RC encoders 5 ₁ , 5 ₂ , ... 5 ₁₆ is converted into the form of transmission data by the framing circuit 6, and the data to be transmitted or recorded on the recording medium is taken out to the output terminal 7. Be done.

FIG. 2 shows a flow of processing of the above-mentioned hybrid high efficiency coding. By the blocking circuit 2, (1
A hybrid block of 6 × 16) pixels is constructed.
One hybrid block includes (4 × 4) sub-blocks. The cosine transform circuit 3 transforms the sub-blocks in the hybrid block and generates (4 × 4) coefficient data for each sub-block. In FIG.
DC indicates a direct current component, AC1, AC2, ... AC
15 shows an AC component. The coefficient data is transmitted in a sequence in which each coefficient data is arranged in the zigzag scanning order starting from the DC component.

The coefficient separating circuit 4 collects the same coefficient data among the coefficient data of the 16 sub-blocks in the hybrid block. As a result, 16 blocks (having the same size as the sub-block) of the same-order coefficient data are extracted from the coefficient separation circuit 4. Since the hybrid block is composed of spatially adjacent sub-blocks, the values of the coefficient data of the same order also have a correlation. Therefore, ADRC encoding of this block of coefficient data enables efficient compression.

FIG. 3 shows an example of the ADRC encoder 5 ₂ according to the present invention. The sub-block of the coefficient data AC1 from the input terminal indicated by 11 is supplied to the absolute value conversion circuit 12 and the delay circuit 13. The coefficient data converted into the absolute value by the absolute value conversion circuit 12 is supplied to the detection circuit 14. The detection circuit 14 detects the maximum value MAX and the minimum value MIN for each sub-block. The delay circuit 13 is provided to compensate for the delay that occurs in the absolute value conversion circuit 12 and the detection circuit 14.

The subtraction circuit 15 obtains the dynamic range DR which is the difference between the maximum value MAX and the minimum value MIN. Since the maximum value MAX and the minimum value MIN are detected by using the coefficient data converted into the absolute value, it is possible to prevent the dynamic range DR from increasing due to the difference in polarity. In addition, the subtraction circuit 16 subtracts the minimum value MIN from the coefficient data from the delay circuit 13 and removes the minimum value to obtain normalized coefficient data.

The normalized coefficient data is supplied to the quantization circuit 17. The dynamic range DR is supplied to the quantization circuit 17. The coefficient data is divided by the quantization step defined by the dynamic range DR, and the quotient is made an integer, whereby the code signal (quantized data) D
T is obtained. The quantization circuit 17 includes a division circuit and a ROM
Etc. ADRC for other AC coefficient data
The encoders 5 _{3 to} 5 ₁₆ also have the same configuration as the ADRC encoder 5 ₂ shown in FIG. The ADRC encoder 5 ₁ for the DC component may have the same configuration as that in FIG. 3, but the DC component does not become negative, and therefore the absolute value conversion circuit 12 may not be provided.

Further, the ADRC encoder shown in FIG.
As a coded output, a dynamic range DR and a quantized code DT are generated, and the transmission of the minimum value MIN is omitted.
This is the dynamic range DR after converting to the absolute value.
Is detected, the probability that the minimum value MIN is 0 is high. Therefore, ADRC decoding can be performed on the reproducing side without recording (transmitting) the minimum value MIN as 0. In this way, the amount of transmitted data is reduced and efficiency is improved.

In the case of ADRC, coefficient data may be normalized by the maximum value MAX, and buffering for controlling the generated data amount according to the capacity of the transmission line by obtaining the frequency distribution of the coefficient data in a predetermined period is performed. You can go. Also, AD
In the RC quantization, the number of quantization bits may be controlled by adapting to the local feature of the image of the hybrid block. Furthermore, an orthogonal transform such as a Hadamard transform other than the cosine transform may be used.

[0024]

According to the present invention, in hybrid high efficiency coding, the dynamic range of a block is detected from coefficient data that has been converted into an absolute value. Therefore, the polarity of the coefficient data is inverted, so that the dynamic range becomes large. Can be prevented. Therefore, the quantization error increases,
It is possible to solve the problem that the number of allocated quantization bits increases.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a schematic diagram used to describe a flow of an encoding process according to an embodiment of the present invention.

FIG. 3 is a block diagram of an example of an ADRC encoder according to the present invention.

FIG. 4 is a schematic diagram used to explain a problem of the previously proposed hybrid encoding.

[Explanation of symbols]

3 Cosine transform circuit 4 Coefficient separation circuit 5 _{1 to} 5 ₁₆ ADRC encoder

Claims (3)

[Claims] 1. Blocking means for dividing the image data into sub-blocks consisting of a predetermined number of pixel data and dividing the image data into main blocks consisting of a plurality of the sub-blocks, and the blocking means. Output data of the sub-block is orthogonal-transform coded to generate coefficient data, and orthogonal transform coding means for generating coefficient data and the main block in which the coefficient data from the orthogonal transform means having the same order are collected. Means for forming an ADRC block having a size of at least, and converting at least an AC component in the coefficient data into an absolute value, detecting a dynamic range of the ADRC block based on the absolute value coefficient data, and adapting to the dynamic range. Then, a high efficiency coding apparatus having ADRC coding means for quantizing the coefficient data. 2. Blocking means for dividing the image data into sub-blocks consisting of a predetermined number of pixel data and dividing the image data into main blocks consisting of a plurality of the sub-blocks, and the blocking means. Output data of the sub-block is orthogonal-transform coded to generate coefficient data, and orthogonal transform coding means for generating coefficient data and the main block in which the coefficient data from the orthogonal transform means having the same order are collected. Means for forming an ADRC block having a size of at least, and converting at least an AC component in the coefficient data into an absolute value, detecting a dynamic range of the ADRC block based on the absolute value coefficient data, and adapting to the dynamic range. And ADRC encoding means for quantizing the coefficient data, and Serial and the dynamic range and the minimum value of the ADRC block, high-efficiency encoding apparatus comprising a frame means for configuring the form of the transmission data the quantized output. 3. Blocking means for dividing the image data into sub-blocks consisting of a predetermined number of pixel data and dividing the image data into main blocks consisting of a plurality of the sub-blocks, and the blocking means. Output data of the sub-block is orthogonal-transform coded to generate coefficient data, and orthogonal transform coding means for generating coefficient data and the main block in which the coefficient data from the orthogonal transform means having the same order are collected. Means for forming an ADRC block having a size of at least, and converting at least an AC component in the coefficient data into an absolute value, detecting a dynamic range of the ADRC block based on the absolute value coefficient data, and adapting to the dynamic range. And ADRC encoding means for quantizing the coefficient data, and Serial high-efficiency encoding apparatus comprising a frame means for configuring to the dynamic range and the form of the transmission data the quantized output of the ADRC block.