JPH06132974A - Buffer for packet disassemble - Google Patents
Buffer for packet disassembleInfo
- Publication number
- JPH06132974A JPH06132974A JP28184992A JP28184992A JPH06132974A JP H06132974 A JPH06132974 A JP H06132974A JP 28184992 A JP28184992 A JP 28184992A JP 28184992 A JP28184992 A JP 28184992A JP H06132974 A JPH06132974 A JP H06132974A
- Authority
- JP
- Japan
- Prior art keywords
- buffer
- frame
- frame buffer
- identifier
- pdu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000872 buffer Substances 0.000 title claims abstract description 84
- 230000004044 response Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 12
- 238000006243 chemical reaction Methods 0.000 description 6
- 230000006870 function Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000005856 abnormality Effects 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9047—Buffering arrangements including multiple buffers, e.g. buffer pools
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9042—Separate storage for different parts of the packet, e.g. header and payload
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
- H04Q11/0478—Provisions for broadband connections
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、固定長のパケットを用
い、かつパケットのアセンブリ・ディスアセンブリ間で
タイミングの時間透過性のない通信における、パケット
・ディスアセンブル用バッファに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer for packet disassembling in a communication using fixed-length packets and having no timing time transparency between assembly and disassembly of packets.
【０００２】[0002]
【従来の技術】パケット通信においては、伝送フレ−ム
を固定長のパケット（以下「セル」という。）に分割す
る機能（以下「セル化」という。）と、セルからフレ−
ムを組み立てるパケット・ディスアセンブリ機能（以下
「デセル化」という。）が必要となり、バッファが重要
な役割を果たす。2. Description of the Related Art In packet communication, there is a function of dividing a transmission frame into fixed-length packets (hereinafter referred to as "cells") (hereinafter referred to as "cellization") and a frame from cells.
A packet disassembly function (hereinafter referred to as "decellization") for assembling the system is required, and the buffer plays an important role.
【０００３】まず、セル化・デセル化について図３と図
４により説明する。First, cellization / decellization will be described with reference to FIGS. 3 and 4.
【０００４】図３は、セル・デセル化の説明図である。
セル・デセル化機能は、図３のコンバ−ジェンス（Ｃ
Ｓ）サブレイヤとＳＡＲサブレイヤとからなりＡＴＭプ
ロトコルのアダプテ−ション・レイヤに実装されいる。FIG. 3 is an explanatory diagram of cell decelling.
The cell-decellization function is performed by the convergence (C
S) consists of a sublayer and a SAR sublayer and is implemented in the adaptation layer of the ATM protocol.
【０００５】図３のように、セル化はフレ−ムからＣＳ
サブレイヤ、ＳＡＲサブレイヤを経て最終的なＡＴＭセ
ルになる。フレ−ムは開始デリミタ（ＳＤ）、アドレス
・フィ−ルド（Ａ）、制御フィ−ルド（Ｃ）、情報部、
フレ−ム・チェック・シ−ケンス（ＦＣＳ）、最終デリ
ミタ（ＥＤ）からなる。ＣＳサブレイヤに入力されたフ
レ−ムは、ＣＳサブレイヤのヘッダ（ＣＳＨ）とトレイ
ラ（ＣＳＴ）が付加される。予め既定されたβバイトの
整数倍にフレ−ムがなっていない場合には、図３のＣＳ
サブレイヤのようにＰＡＤの付加（以下「パディング」
という。）を行う。ＣＳサブレイヤから出力されたＣＳ
サブレイヤ・プロトコル・デ−タユニット（ＣＳ−ＰＤ
Ｕ）はＳＡＲサブレイヤに入力され、ＳＡＲヘッダ（Ｓ
ＡＲＨ）とＳＡＲトレイラ（ＳＡＲＴ）を付加した後、
ＡＴＭレイヤへＡＴＭＨに関する情報とともにＡＴＭセ
ルとして出力される。なお、デセル化は、上記セル化の
逆を行う。As shown in FIG. 3, cell formation is performed from the frame to the CS.
A final ATM cell is obtained through the sublayer and the SAR sublayer. The frame is a start delimiter (SD), an address field (A), a control field (C), an information section,
It consists of a frame check sequence (FCS) and a final delimiter (ED). The CS sublayer header (CSH) and trailer (CST) are added to the frame input to the CS sublayer. If the frame is not an integral multiple of the predetermined β bytes, CS in FIG.
Add PAD like sublayer (hereinafter "padding")
Say. )I do. CS output from CS sublayer
Sublayer Protocol Data Unit (CS-PD
U) is input to the SAR sublayer, and the SAR header (S
After adding ARH) and SAR trailer (SART),
It is output to the ATM layer as an ATM cell together with the information about ATMH. It should be noted that the decellization is the reverse of the cellization described above.
【０００６】図４は、ＳＡＲサブレイヤのフォ−マット
例を示す図である。図４において、ＳＴは、セグメント
・タイプであり、ＣＳ−ＰＤＵのセル化を行った時送出
するセルが先頭、中間、最終、単一セルかの識別を示
す。ＳＮは、シ−ケンス番号であり、４ビット長あるた
めモジュロ１６で値が決められる。ＭＩＤは、多重化識
別子である。ＬＩは、パディングする場合があるため、
セル内の有効情報長を示している。ＣＲＣは、誤り検出
符号である。ＳＡＲＨはＳＴ、ＳＮ、ＭＩＤで、ＳＡＲ
ＴはＬＩ、ＣＲＣで構成される各フィ−ルドとなる。Ｓ
ＡＲＨとＳＡＲＴは、ＣＳ−ＰＤＵの組立を行う際に必
要な情報を含んでいる。ＳＡＲサブレイヤのデセル化処
理はこれらのフィ−ルドを用いて行われ、これらのフィ
−ルドに不整合がある場合、セルを廃棄する。FIG. 4 is a diagram showing an example of the format of the SAR sublayer. In FIG. 4, ST is a segment type and indicates whether the cell to be transmitted when the CS-PDU is made into cells is the head, the middle, the last, or a single cell. SN is a sequence number, and since it has a length of 4 bits, its value is determined by modulo 16. MID is a multiplexing identifier. Since LI may be padded,
The effective information length in the cell is shown. CRC is an error detection code. SARH is ST, SN, MID, SAR
T is a field composed of LI and CRC. S
ARH and SART include information necessary for assembling a CS-PDU. The SAR sublayer decelling process is performed using these fields, and if there is a mismatch in these fields, the cell is discarded.
【０００７】次に、デセル化の際使用するバッファ構成
について、二つの従来例を説明する。 図５は、ＣＳ−
ＰＤＵの最大長以上のフレ−ムバッファ構成とした一従
来例を示す機能ブロック図である。この例は固定長バッ
ファをコネクション識別子（ＶＣＩ）、多重化識別子
（ＭＩＤ）ごとにもつものである。まず、ＡＴＭレイヤ
から受信したＳＡＲ−ＰＤＵのコネクション識別子およ
びＳＡＲヘッダ内の多重化識別子により、書き込み制御
部３１はスイッチ３２を制御して、同一のＶＣＩ、同一
のＭＩＤをもつＳＡＲ−ＳＤＵを用いてＣＳ−ＰＤＵを
組み立てる。この際の作業用バッファがＮ個分のＣＳ−
ＰＤＵ長の固定長バッファをもつバッファ３３である。
前述したように、ＣＳ−ＰＤＵの組立て終了はＳＴフィ
−ルドによって把握できる。組立が終了したＣＳ−ＰＤ
Ｕは、スイッチ３４の選択により読み出し制御部３５を
通じて上位レイヤに引き渡される。Next, two conventional examples will be described for the buffer structure used for decelling. FIG. 5 shows CS-
It is a functional block diagram which shows one prior art example which has the frame buffer structure more than the maximum length of PDU. In this example, a fixed length buffer is provided for each connection identifier (VCI) and multiplex identifier (MID). First, the write control unit 31 controls the switch 32 using the connection identifier of the SAR-PDU received from the ATM layer and the multiplexing identifier in the SAR header to use the SAR-SDU having the same VCI and the same MID. Assemble the CS-PDU. At this time, there are N work buffers CS-
The buffer 33 has a fixed length buffer having a PDU length.
As described above, the completion of the assembly of the CS-PDU can be grasped by the ST field. CS-PD assembled
U is delivered to the upper layer through the read control unit 35 by the selection of the switch 34.
【０００８】次に、図６は、ＳＡＲ−ＳＤＵの長さのフ
レ−ムバッファ構成とした一従来例を示す機能ブロック
図である。図５のバッファ３３はＣＳ−ＰＤＵの最大長
以上の長さでかつ固定長のバッファから構成されている
ため、特定のコネクションの利用が多い場合、バッファ
の使用効率が高くないという問題があった。通常、バッ
ファはメモリを用いて構成するため、メモリの使用効率
と等価であるためである。そこで、図５の例を改良し、
メモリの使用効率を高くしたのが、図６の構成である。
図５のバッファ構成がＣＳ−ＰＤＵの最大長の以上の固
定長と長いバッファ長であるのに比し、図６のバッファ
構成は、ＳＡＲ−ＳＤＵサイズと短いバッファ長として
いる。さらに、リリ−ス可能ＳＡＲ−ＳＤＵバッファ４
７の領域を設けることで、ＳＡＲ−ＳＤＵサイズのバッ
ファを異なるコネクション識別子あるいは多重化識別子
で共通に使用することができる。すなわち、書き込み制
御部４１はＳＡＲ−ＳＤＵサイズのバッファ４８である
リリース可能ＳＡＲ−ＳＤＵバッファ４７から割り当て
られたＳＡＲ−ＳＤＵサイズのバッファにＳＡＲ−ＳＤ
Ｕを書き込み、ＡＴＭレイヤから受信したＳＡＲ−ＰＤ
Ｕのコネクション識別子およびＳＡＲヘッダ内の多重化
識別子によりスイッチ４２を制御して、同一のＶＣＩ、
同一のＭＩＤをもつＳＡＲ−ＳＤＵをＣＳ−ＰＤＵの組
立中のバッファ４３においてＣＳ−ＰＤＵを組み立て
る。組み立てられたＣＳ−ＰＤＵはＣＳ−ＰＤＵの組立
終了後のバッファ４４を介して、スイッチ４５によりＣ
Ｓ−ＰＤＵが順に読み出し制御部４６に送られＣＳ−Ｐ
ＤＵとして上位レイヤに引き渡される。Next, FIG. 6 is a functional block diagram showing a conventional example having a frame buffer structure having the length of SAR-SDU. Since the buffer 33 in FIG. 5 is composed of a buffer having a length equal to or longer than the maximum length of the CS-PDU and having a fixed length, there is a problem that the usage efficiency of the buffer is not high when a particular connection is frequently used. . This is because the buffer is usually configured by using a memory, which is equivalent to the usage efficiency of the memory. Therefore, we improved the example in Figure 5,
The structure shown in FIG. 6 improves the memory usage efficiency.
The buffer structure of FIG. 5 has a fixed length longer than the maximum length of the CS-PDU and a long buffer length, whereas the buffer structure of FIG. 6 has a SAR-SDU size and a short buffer length. Furthermore, a releasable SAR-SDU buffer 4
By providing the area of 7, the SAR-SDU size buffer can be commonly used by different connection identifiers or multiplex identifiers. That is, the write control unit 41 stores the SAR-SDU size buffer 48, which is the SAR-SDU size buffer 48, in the SAR-SDU size buffer allocated to the SAR-SDU size buffer.
SAR-PD written U and received from ATM layer
The switch 42 is controlled by the U connection identifier and the multiplexing identifier in the SAR header, and the same VCI,
The SAR-SDU having the same MID is assembled into the CS-PDU in the buffer 43 during the assembly of the CS-PDU. The assembled CS-PDU is switched to C by the switch 45 via the buffer 44 after the completion of the CS-PDU assembly.
S-PDUs are sequentially sent to the read control unit 46 and CS-P
It is delivered to the upper layer as a DU.
【０００９】しかし、上記二つの従来例の構成は、使用
するバッファをコネクション識別子および多重化識別子
で選択しているため、ある識別子のフレ−ム、例えばＣ
Ｓ−ＰＤＵの組立終了後は、上位レイヤ処理部のフレ−
ム引取りが終了しない限り、当該識別子のフレ−ムの組
立てができない。このため、上位レイヤ処理部では、フ
レ−ム引取りが固定長のパケットの最小到来間隔以内に
可能なように、処理能力を大幅に上げる必要があった。However, in the above two conventional configurations, since the buffer to be used is selected by the connection identifier and the multiplexing identifier, the frame of a certain identifier, for example, C
After the S-PDU is assembled, the frame of the upper layer processing unit is
The frame of the identifier cannot be assembled unless the frame collection is completed. For this reason, in the upper layer processing unit, it is necessary to significantly increase the processing capability so that the frame can be collected within the minimum arrival interval of the fixed-length packet.
【００１０】[0010]
【発明が解決しようとする課題】上述のごとく、従来の
装置では、フレ−ムバッファ番号とコネクション識別子
あるいは同一コネクション上の多重化識別子の対応が固
定であるため、ある識別子の組立終了後は、上位レイヤ
処理部のフレ−ム引取りが終了しない限り、当該識別子
のフレ−ム組立てができない。このため、上位レイヤ処
理部のフレ−ム引取りが、固定長のパケットの最小到来
間隔以内に可能なように、上位レイヤ処理部の処理能力
を大幅に上げる必要があった。As described above, in the conventional apparatus, since the correspondence between the frame buffer number and the connection identifier or the multiplex identifier on the same connection is fixed, after the assembly of a certain identifier is completed, the higher order The frame of the identifier cannot be assembled unless the frame processing of the layer processing unit is completed. Therefore, it is necessary to significantly increase the processing capability of the upper layer processing unit so that the upper layer processing unit can receive the frame within the minimum arrival interval of the fixed-length packet.
【００１１】そこで、本発明は、上位レイヤ処理部に過
度のフレーム処理能力を強要しない柔軟なパケット・デ
ィスアセンブル用バッファを提供することを目的とす
る。Therefore, an object of the present invention is to provide a flexible packet disassembling buffer which does not impose an excessive frame processing capability on the upper layer processing section.
【００１２】[0012]
【課題を解決するための手段】固定長のパケットの情報
部バイト長αの整数倍で、かつ同一の長さをもつ複数の
パケット・ディスアセンブリ用バッファをもち、当該パ
ケットのヘッダ内のコネクション識別子あるいは同一コ
ネクション上の多重化識別子ごとに、同一識別子をもつ
パケットのディスアセンブリが完了したか否かの情報、
および当該識別子とフレ−ムバッファの対応を示す情
報、パケット・ディスアセンブルに関する途中情報、例
えば、直前に受信したパケットのシ−ケンス番号、組立
て途中のフレ−ムのバイト長等を有し、フレ−ムバッフ
ァ番号と識別子との対応をフレ−ム組立てごとに可変と
することにより構成される。A connection identifier in a header of a packet having a plurality of packet disassembly buffers each having an integral multiple of the information portion byte length α of a fixed length packet and having the same length. Or, for each multiplexing identifier on the same connection, information on whether or not disassembly of a packet having the same identifier is completed,
And information indicating the correspondence between the identifier and the frame buffer, intermediate information on packet disassembly, such as the sequence number of the packet received immediately before, the byte length of the frame being assembled, and the like. It is configured by making the correspondence between the frame buffer number and the identifier variable for each frame assembly.
【００１３】[0013]
【作用】本発明は、フレ−ムバッファの番号と識別子と
の対応を、クレ−ム組立てごとに可変とすることを特徴
とする。The present invention is characterized in that the correspondence between the frame buffer number and the identifier is variable for each frame assembly.
【００１４】このため、ある識別子上のフレ−ム組立て
終了後で、かつ上位レイヤ処理部のフレ−ム引取りが未
了の場合でも、同一識別子上のフレ−ム組立てが可能と
なり、上位レイヤ処理部に過度の処理能力を要求しな
い。Therefore, even after the frame assembling on a certain identifier has been completed and the frame taking over by the upper layer processing unit has not been completed, the frame assembling on the same identifier can be performed, and the upper layer can be assembled. Does not require excessive processing capacity of the processing unit.
【００１５】[0015]
【実施例】図１は、本発明の一実施例を示すブロック図
である。FIG. 1 is a block diagram showing an embodiment of the present invention.
【００１６】本実施例の各固定長バッファは、図５の従
来例と同様、ＣＳ−ＰＤＵの最大長以上の固定長バッフ
ァであるが、ＦＢ管理テーブル１１により管理されてい
る。すなわち、ＳＡＲ−ＰＤＵ入力線１４より受信され
たあるコネクション上のＳＡＲ−ＰＤＵは、コネクショ
ン識別子（ＶＣＩ）とフレ−ムバッファ番号（ＦＢＮ）
との変換テ−ブル１０により、当該コネクション上のＳ
ＡＲ−ＰＤＵが組立中である場合は使用中のＦＢＮのバ
ッファを、組立は終了したが上位レイヤ、この場合ＣＳ
サブレイヤからの引取りが未了の場合および全くフレー
ムバッファ（ＦＢ）１２になく新規にＣＳ−ＰＤＵを組
み立てる場合には、空きフレ−ムバッファ１３から新た
に供給されるフレームバッファを使用するように、選択
がなされる。この選択されたフレームバッファＦＢＮを
ｉとすると、ＦＢ管理テ−ブル１１を、ｉをキ−にして
検索し、ＦＢｉのアドレスポインタＰｉ、情報長、Ｓ
Ｔ、ＳＮ、ＶＣＩ等の情報を得る。なお、ＣＳ−ＰＤＵ
を組立てはじめる時は、Ｐｉ、情報長、ＳＴ、ＳＮは初
期値とする。ＳＡＲ−ＳＤＵはＦＢｉのバッファに蓄積
されＣＳ−ＰＤＵが組み立てられるとともに、ＦＢ管理
テ−ブル１１も更新される。以上を繰り返してＣＳ−Ｐ
ＤＵを組み立てていく。組立て終了後は、上位レイヤに
引取りの要求を出し、応答があれば当該ＣＳ−ＰＤＵの
アドレスポインタ、情報長を上位レイヤに提示して引取
りをおこなってもらう。引取り終了後は、当該フレ−ム
バッファＦＢｉを空きフレ−ムバッファ１３に入れる。Each fixed-length buffer of this embodiment is a fixed-length buffer having a maximum length of CS-PDU or more, as in the conventional example of FIG. 5, but is managed by the FB management table 11. That is, the SAR-PDU on a certain connection received from the SAR-PDU input line 14 is the connection identifier (VCI) and the frame buffer number (FBN).
With the conversion table 10 for
If the AR-PDU is being assembled, the buffer of the FBN in use is used. If the assembly is completed, the upper layer, in this case CS
When the sub-layer has not been picked up and when a new CS-PDU is not included in the frame buffer (FB) 12, the frame buffer newly supplied from the empty frame buffer 13 is used. A choice is made. If the selected frame buffer FBN is i, the FB management table 11 is searched with i as a key, and the address pointer Pi of FBi, information length, S
Obtain information such as T, SN, and VCI. In addition, CS-PDU
When assembling is started, Pi, information length, ST, and SN are initial values. The SAR-SDU is stored in the FBi buffer to assemble the CS-PDU, and the FB management table 11 is updated. Repeating the above, CS-P
Assemble the DU. After the assembly is completed, a request for taking back is issued to the upper layer, and if there is a response, the address pointer and information length of the CS-PDU concerned are presented to the upper layer and the taking-back is performed. After the end of collection, the frame buffer FBi is put into the empty frame buffer 13.
【００１７】さらに、図２は本発明の一実施例を示す詳
細ブロック図である。図１のコネクション識別子とフレ
ームバッファ番号との変換テーブル１０に相当する部分
が図２のコネクション識別子とフレームバッファ番号と
の変換テーブル２０であり、当該コネクション上のＣＳ
−ＰＤＵが組立中であるかどうか、組立終了であるが上
位レイヤからの引き取り終了および新規にＣＳ−ＰＤＵ
を組み立てる必要があるかどうかの状況を示すテ−ブル
である。また、フレ−ムバッファ管理テ−ブル１１に相
当するのが図２のフレ−ムバッファ管理テ−ブル２１で
あり、その他は、図１の実施例と同じである。すなわ
ち、ＳＡＲ−ＰＤＵ入力線２４より受信されたあるコネ
クション上のＳＡＲ−ＰＤＵは、コネクション識別子
（ＶＣＩ）とフレ−ムバッファ番号（ＦＢＮ）との変換
テ−ブル２０により、当該コネクション上のＳＡＲ−Ｐ
ＤＵが組立中である場合は使用中のＦＢＮのバッファ
を、組立は終了したが上位レイヤ、この場合ＣＳサブレ
イヤからの引取りが未了の場合および全くフレームバッ
ファ（ＦＢ）２２になく新規にＣＳ−ＰＤＵを組み立て
る場合には、空きフレ−ムバッファ２３から新たに供給
されるフレームバッファを使用するように、選択がなさ
れる。ＦＢ管理テ−ブル２１ではＣＳ−ＰＤＵのアドレ
スポインタおよび情報長を付加情報として付加情報部２
５からＣＳ−ＰＤＵの組立終了後、ＣＳサブレイヤに出
力する。また、ＳＴ、ＳＮ、ＣＲＣ等の検査で異常があ
った場合には割り込み部２６より異常の情報を出力す
る。ＣＳサブレイヤへの引取り終了後は、当該使用した
フレ−ムバッファを空きフレ−ムバッファ１３に入れ
る。Further, FIG. 2 is a detailed block diagram showing an embodiment of the present invention. A portion corresponding to the conversion table 10 between the connection identifier and the frame buffer number in FIG. 1 is the conversion table 20 between the connection identifier and the frame buffer number in FIG.
-Whether the PDU is being assembled, completion of assembly but receipt from upper layer and new CS-PDU
It is a table showing the situation of whether or not it is necessary to assemble. Further, the frame buffer management table 11 corresponds to the frame buffer management table 21 of FIG. 2, and the rest is the same as the embodiment of FIG. That is, the SAR-PDU on a certain connection received from the SAR-PDU input line 24 is converted into the SAR-P on the connection by the conversion table 20 between the connection identifier (VCI) and the frame buffer number (FBN).
When the DU is in the process of being assembled, the buffer of the FBN in use is used, and when the assembly is completed but the take-up from the upper layer, in this case, the CS sublayer has not been completed and there is no frame buffer (FB) 22 at all, a new CS is newly created. -When assembling a PDU, the choice is made to use the frame buffer newly supplied from the free frame buffer 23. In the FB management table 21, the additional information section 2 uses the address pointer and the information length of the CS-PDU as additional information.
After completion of assembling the CS-PDU from step 5, it is output to the CS sublayer. Further, when there is an abnormality in the inspection of ST, SN, CRC, etc., the interruption unit 26 outputs the abnormality information. After the completion of taking over to the CS sublayer, the used frame buffer is put into the empty frame buffer 13.
【００１８】なお、図１および図２は図５と同様、ＣＳ
−ＰＤＵの最大長サイズのバッファ長としたが、図６の
ようにＳＡＲ−ＳＤＵ長等の短いバッファ長による構成
としても、同様に適用できる。1 and 2 are the same as those in FIG.
-Although the buffer length is the maximum length size of the PDU, it can be similarly applied to a configuration with a short buffer length such as the SAR-SDU length as shown in FIG.
【００１９】このように、フレ−ムバッファの番号とコ
ネクション識別子との対応をフレ−ムの組立ごとに可変
しているため、ある識別子のフレ−ム組立終了後、上位
レイヤからのフレ−ム引取り未了の状態でも同一識別子
上のフレ−ム組立が可能となり、上位レイヤに過度の処
理能力をもたせる必要がないという利点がある。As described above, since the correspondence between the frame buffer number and the connection identifier is changed for each frame assembly, after the frame assembly of a certain identifier is completed, the frame is drawn from the upper layer. It is possible to assemble a frame on the same identifier even in a state where the process is not completed, and there is an advantage that it is not necessary for the upper layer to have an excessive processing capability.
【００２０】[0020]
【発明の効果】上述したように、本発明はフレ−ムバッ
ファ番号と識別子との対応をフレ−ム組立てごとに可変
とすることにより、ある識別子上のフレ−ム組立て終了
後で、かつ上位レイヤ処理部のフレ−ム引取りが未了の
状態でも、同一識別子上のフレ−ム組立が可能となり、
上位レイヤ処理部に過度の処理能力を要求せず、効率的
なデセル化および通信処理が可能となる。As described above, according to the present invention, the correspondence between the frame buffer number and the identifier is made variable for each frame assembly, so that after the frame assembly on a certain identifier is completed, the upper layer It is possible to assemble frames on the same identifier even if the frame pickup of the processing unit is not completed.
Efficient decelling and communication processing are possible without requiring the upper layer processing unit to have an excessive processing capability.
【図１】本発明の一実施例を示すブロック図。FIG. 1 is a block diagram showing an embodiment of the present invention.
【図２】本発明の一実施例を示す詳細ブロック図。FIG. 2 is a detailed block diagram showing an embodiment of the present invention.
【図３】セル・デセル化の説明図。FIG. 3 is an explanatory diagram of cell-decellization.
【図４】ＳＡＲサブレイヤのフォ−マットの一例を示す
図。FIG. 4 is a diagram showing an example of a format of a SAR sublayer.
【図５】ＣＳ−ＰＤＵの最大長以上のフレ−ムバッファ
構成とした一従来例を示す機能ブロック図。FIG. 5 is a functional block diagram showing a conventional example in which a frame buffer having a maximum length of CS-PDU or more is used.
【図６】ＳＡＲ−ＳＤＵの長さのフレ−ムバッファ構成
とした一従来例を示す機能ブロック図。FIG. 6 is a functional block diagram showing a conventional example having a frame buffer configuration having a length of SAR-SDU.
１０ コネクション識別子（ＶＣＩ）とフレ−ムバッフ
ァ番号（ＦＢＮ）との変換テ−ブル １１ フレ−ムバッファ（ＦＢ）管理テ−ブル １２ フレ−ムバッファ（ＦＢ） １３ 空きフレ−ムバッファ １４ ＳＡＲ−ＰＤＵ入力線 ２０ コネクション識別子（ＶＣＩ）とフレームバッフ
ァ番号（ＦＢＮ）との変換テーブル ２１ フレ−ムバッファ管理（ＦＢ）テ−ブル ２２ フレームバッファ（ＦＢ） ２３ 空きフレームバッファ ２４ ＳＡＲ−ＰＤＵ入力線 ２５ 付加情報部 ２６ 割り込み部 ３１ 書き込み制御部 ３２ スイッチ ３３ Ｎ個分のＣＳ−ＰＤＵ長のバッファ ３４ スイッチ ３５ 読み出し制御部 ４１ 書き込み制御部 ４２ スイッチ ４３ ＣＳ−ＰＤＵの組立中のバッファ ４４ ＣＳ−ＰＤＵの組立終了後のバッファ ４５ スイッチ ４６ 読み出し制御部 ４７ リリ−ス可能ＳＡＲ−ＳＤＵバッファ ４８ ＳＡＲ−ＳＤＵサイズのバッファ10 Connection identifier (VCI) and frame buffer number (FBN) conversion table 11 Frame buffer (FB) management table 12 Frame buffer (FB) 13 Free frame buffer 14 SAR-PDU input line 20 Conversion table of connection identifier (VCI) and frame buffer number (FBN) 21 Frame buffer management (FB) table 22 Frame buffer (FB) 23 Free frame buffer 24 SAR-PDU input line 25 Additional information section 26 Interrupt section 31 write control unit 32 switch 33 buffer for N CS-PDU length 34 switch 35 read control unit 41 write control unit 42 switch 43 buffer during CS-PDU assembly 44 switch after completion of CS-PDU assembly 45 switch 46 read Out control unit 47 releases - scan enable SAR-SDU buffer 48 SAR-SDU size buffer
Claims (1)
用いる通信のパケット・ディスアセンブリにおいて、 前記所定固定長の整数倍でかつ同一長の複数のパケット
・ディスアセンブル用固定長バッファと、 前記パケットのヘッダ部内のコネクション識別子あるい
は同一コネクション上の多重化識別子ごとに、当該同一
識別子をもつパケットのディスアセンブリが完了したか
否かの情報と、当該識別子とフレ−ムバッファの対応を
示す情報をもとに識別子とフレームバッファの番号の対
応を可変するフレーム管理手段と、 を具備することを特徴とするパケット・ディスアセンブ
ル用バッファ。1. A packet disassembly for communication using a packet having an information part byte length of a predetermined fixed length, and a plurality of fixed length buffers for packet disassembling which are integral multiples of the predetermined fixed length and have the same length, For each connection identifier in the header part of the packet or for each multiplexing identifier on the same connection, information indicating whether disassembly of the packet having the same identifier is completed and information indicating the correspondence between the identifier and the frame buffer are also included. And a frame management means for varying the correspondence between the identifier and the number of the frame buffer, and a packet disassembling buffer.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28184992A JPH06132974A (en) | 1992-10-20 | 1992-10-20 | Buffer for packet disassemble |
| US08/137,927 US5414702A (en) | 1992-10-20 | 1993-10-19 | Packet disassembler for use in a control unit of an asynchronous switching system |
| CA002108863A CA2108863C (en) | 1992-10-20 | 1993-10-20 | Packet disassembler |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28184992A JPH06132974A (en) | 1992-10-20 | 1992-10-20 | Buffer for packet disassemble |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06132974A true JPH06132974A (en) | 1994-05-13 |
Family
ID=17644864
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28184992A Pending JPH06132974A (en) | 1992-10-20 | 1992-10-20 | Buffer for packet disassemble |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US5414702A (en) |
| JP (1) | JPH06132974A (en) |
| CA (1) | CA2108863C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08137773A (en) * | 1994-11-11 | 1996-05-31 | Nippon Denki Ido Tsushin Kk | Data transmission/reception system for mobile communication system |
| KR100920651B1 (en) * | 2001-12-21 | 2009-10-09 | 에이저 시스템즈 인크 | A method and apparatus for reassembly of data blocks within a network processor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0649234B1 (en) * | 1993-10-14 | 2001-09-19 | International Business Machines Corporation | Method and apparatus of transferring data in an ATM network |
| US5446726A (en) * | 1993-10-20 | 1995-08-29 | Lsi Logic Corporation | Error detection and correction apparatus for an asynchronous transfer mode (ATM) network device |
| FR2716278B1 (en) * | 1994-02-14 | 1996-05-03 | Guigner Marc Le | Method for processing data from a transmission adaptation layer according to an ATM type asynchronous transfer mode. |
| US5566170A (en) * | 1994-12-29 | 1996-10-15 | Storage Technology Corporation | Method and apparatus for accelerated packet forwarding |
| US5598410A (en) * | 1994-12-29 | 1997-01-28 | Storage Technology Corporation | Method and apparatus for accelerated packet processing |
| US5546390A (en) * | 1994-12-29 | 1996-08-13 | Storage Technology Corporation | Method and apparatus for radix decision packet processing |
| US5577039A (en) * | 1995-06-07 | 1996-11-19 | Samsung Electronics, Inc. | System and method of signal transmission within a plesiochronous digital hierarchy unit using ATM adaptation layers |
| US5796735A (en) * | 1995-08-28 | 1998-08-18 | Integrated Device Technology, Inc. | System and method for transmission rate control in a segmentation and reassembly (SAR) circuit under ATM protocol |
| US5848068A (en) * | 1996-03-07 | 1998-12-08 | Lsi Logic Corporation | ATM communication system interconnect/termination unit |
| US5841772A (en) * | 1996-03-07 | 1998-11-24 | Lsi Logic Corporation | ATM communication system interconnect/termination unit |
| US6535512B1 (en) | 1996-03-07 | 2003-03-18 | Lsi Logic Corporation | ATM communication system interconnect/termination unit |
| US5982749A (en) * | 1996-03-07 | 1999-11-09 | Lsi Logic Corporation | ATM communication system interconnect/termination unit |
| US5920561A (en) * | 1996-03-07 | 1999-07-06 | Lsi Logic Corporation | ATM communication system interconnect/termination unit |
| FI103456B (en) * | 1996-03-29 | 1999-06-30 | Nokia Telecommunications Oy | Speech transmission over packet network |
| US5757796A (en) * | 1996-04-26 | 1998-05-26 | Cascade Communications Corp. | ATM address translation method and apparatus |
| US5987024A (en) * | 1997-05-09 | 1999-11-16 | Motorola, Inc. | Self synchronizing network protocol |
| FI974020A0 (en) * | 1997-10-21 | 1997-10-21 | Nokia Telecommunications Oy | Optimization of the resource and the packet processor system |
| CA2282441C (en) * | 1997-12-25 | 2004-07-27 | Kabushiki Kaisha Toshiba | Atm relay device and network including same |
| US6836483B1 (en) * | 1998-06-24 | 2004-12-28 | Research Investment Network, Inc. | Message system for asynchronous transfer |
| FI106504B (en) * | 1998-10-06 | 2001-02-15 | Nokia Networks Oy | Data segmentation method in a communication system |
| US6567378B1 (en) * | 1998-12-24 | 2003-05-20 | Genuity Inc. | Cell discard scheme for IP traffic over a cell relay infrastructure |
| WO2002014998A2 (en) * | 2000-08-11 | 2002-02-21 | Storage Technology Corporation | Method and apparatus for transferring data in a data processing system |
| US7515611B2 (en) * | 2000-08-24 | 2009-04-07 | Tellabs Reston, Inc. | Unified data packet for encapsulating data packets having diverse formats |
| US20020154647A1 (en) * | 2001-02-16 | 2002-10-24 | Hanan Potash | Frame handler for high-speed fiber optic communication interface |
| US7042886B2 (en) * | 2001-12-06 | 2006-05-09 | P-Cube Ltd. | Apparatus, method, and computer program for wire-speed classification and pre-processing of data packets in an ATM network |
| KR20040059662A (en) * | 2002-12-28 | 2004-07-06 | 삼성전자주식회사 | Device and method for communicating moving picture using streaming |
| EP1526701A1 (en) * | 2003-10-22 | 2005-04-27 | Mitsubishi Denki Kabushiki Kaisha | Methods and devices for transferring and for recovering data packets |
| WO2005053170A2 (en) * | 2003-11-24 | 2005-06-09 | Interdigital Technology Corporation | Method and apparatus for compiling a protocol data unit |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5101404A (en) * | 1988-08-26 | 1992-03-31 | Hitachi, Ltd. | Signalling apparatus for use in an ATM switching system |
| US5214642A (en) * | 1989-02-21 | 1993-05-25 | Hitachi, Ltd. | ATM switching system and adaptation processing apparatus |
| JP3085391B2 (en) * | 1989-06-19 | 2000-09-04 | 株式会社日立製作所 | Communication device |
| JPH03182140A (en) * | 1989-12-11 | 1991-08-08 | Mitsubishi Electric Corp | Common buffer type exchange |
| DE3942977A1 (en) * | 1989-12-23 | 1991-06-27 | Standard Elektrik Lorenz Ag | METHOD FOR RESTORING THE CORRECT SEQUENCE OF CELLS, ESPECIALLY IN AN ATM SWITCHING CENTER, AND OUTPUT UNIT THEREFOR |
| US5233606A (en) * | 1991-08-02 | 1993-08-03 | At&T Bell Laboratories | Arrangement for controlling shared-buffer-memory overflow in a multi-priority environment |
-
1992
- 1992-10-20 JP JP28184992A patent/JPH06132974A/en active Pending
-
1993
- 1993-10-19 US US08/137,927 patent/US5414702A/en not_active Expired - Fee Related
- 1993-10-20 CA CA002108863A patent/CA2108863C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08137773A (en) * | 1994-11-11 | 1996-05-31 | Nippon Denki Ido Tsushin Kk | Data transmission/reception system for mobile communication system |
| KR100920651B1 (en) * | 2001-12-21 | 2009-10-09 | 에이저 시스템즈 인크 | A method and apparatus for reassembly of data blocks within a network processor |
Also Published As
| Publication number | Publication date |
|---|---|
| CA2108863C (en) | 1999-09-28 |
| US5414702A (en) | 1995-05-09 |
| CA2108863A1 (en) | 1994-04-21 |
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