JPH0613279U - Clamp pulse generation circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] An object of the present invention is to provide a clamp pulse generation circuit that can maintain a stable DC level regardless of the level of the horizontal frequency and can stably maintain the brightness. [Structure] When the horizontal frequency is high, the clamp pulse width is reduced so that the clamp pulse does not overlap the video period. Further, when the video signal does not include the sync signal, the rising timing of the clamp pulse is set. The trailing edge of the sync signal is switched to the leading edge.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a clamp pulse generation circuit, and more specifically, to stability of a DC clamp section of a video circuit such as a display monitor.

[0002]

[Prior art]

 FIG. 2 is a circuit configuration diagram of a conventional clamp pulse generation circuit, and the operation of this circuit will be described below. (5) is an input terminal of the clamp pulse generation circuit, to which a positive polarity pulse P1 having the same timing as the horizontal synchronizing signal is added. The positive pulse P1 is differentiated by a differentiating circuit composed of a capacitor C1 and a resistor R1, and a differential pulse P3 is added to the base of the transistor Q1.

In the transistor Q1, a collector current flows when the base voltage drops by VBE (about 0.7V) from VCC, so that the positive pulse P4 of the same timing as the downward pulse of the differential pulse P3 is generated by the transistor Q1. It is input to the clamp circuit as a collector output pulse.

In the clamp circuit, the positive polarity pulse P4 operates as a gate pulse to charge the clamping capacitor only during the positive polarity pulse P4, and hold the charging voltage of this capacitor for a period other than the positive polarity pulse P4. Operates to keep the DC level of the video signal constant.

FIG. 3 is a timing chart showing a timing relationship between a video signal (video signal) and a clamp pulse.

FIG. 1A shows a timing relationship between the video signal (a) and the clamp pulse (b). A sync signal is added to the video signal (a), but a normal GR EEN signal is added. Only a composite signal like this.

As described above, the clamp pulse (b) is generated later than the trailing edge of the horizontal sync signal, so that the clamp pulse (b) is synchronized with the video signal (a) as can be understood from FIG. 3 (A). It is located behind the part. Therefore, the clamp circuit keeps the voltage of the back porch portion of the video signal (a) constant.

As described above, since the clamp circuit operates so as to fix the DC voltage by observing a part of the video signal, if the clamp pulse overlaps with the timing of the horizontal synchronizing signal or overlaps with the video period. , DC voltage will fluctuate. In the former case, the DC voltage rises only for the GREEN signal, and the screen turns green, and in the latter case, the brightness at the left end of the screen becomes dark, which adversely affects the image quality.

[0009]

[Problems to be solved by the device]

 Therefore, in order to prevent the clamp pulse from overlapping the horizontal synchronizing signal, it is usual to apply a clamp on the back porch as shown in FIG. 3 (A), but as shown in FIG. 3 (B). In the mode with high horizontal frequency, the back porch period is short and the clamp pulse (d) overlaps with the video period of the video signal (c).

In the case of a multi-sync type monitor, it is necessary to support from a low horizontal frequency to a high horizontal frequency, and in the conventional clamp pulse generation circuit, it is possible to prevent the above-mentioned influence on the image quality. At the back porch timing, the pulse width was made as narrow as possible so that it would not overlap the video period (see Fig. 3 (C)).

However, if the clamp pulse width is narrowed in accordance with the mode in which the horizontal frequency is high, in the mode in which the horizontal frequency is low, the amount of charge of the clamping capacitor is reduced, so that the fluctuation amount of the clamp level becomes large and the luminance change. Was occurring.

The clamp pulse generation circuit of the present invention has been made in view of such circumstances, and a clamp that can maintain a stable DC level and maintain a stable brightness regardless of the level of the horizontal frequency. An object is to provide a pulse generation circuit.

[0013]

[Means for Solving the Problems]

 The clamp pulse generation circuit of the present invention is a clamp pulse generation circuit for operating a clamp circuit for fixing the DC level of a video amplifier, and a frequency discriminating means for discriminating the level of the horizontal frequency and a discrimination output of the frequency discriminating means. The pulse width control means controls the pulse width of the clamp pulse, and further determines the level of the horizontal frequency in the clamp pulse generation circuit that operates the clamp circuit for fixing the DC level of the video amplifier. A frequency discriminating means, a pulse width controlling means for controlling the pulse width of the clamp pulse based on the discriminating output of the frequency discriminating means, and a synchronizing signal discriminating means for discriminating the presence or absence of a synchronizing signal added to the blanking period of the video signal. , The timing of the rising edge of the clamp pulse is controlled by the discrimination output of the synchronizing signal discrimination means. In which the more the rising control means.

[0014]

[Action]

 As shown in FIGS. 3 (A) and 3 (C), when the horizontal frequency is high, the clamp pulse width is reduced so that the clamp pulse does not overlap the video period, and further, as shown in FIG. 3 (D). When the sync signal is not included in the video signal at a low horizontal frequency, the rising edge of the clump pulse is switched from the trailing edge to the leading edge of the sync signal.

[0015]

【Example】

 FIG. 1 is a block diagram of a clamp pulse generation circuit of the present invention. In the figure, (3) is a Gon Sync determination circuit that determines whether or not a sync signal is added to the video signal, and (4) is a mode switching circuit that outputs a control signal depending on the level of the horizontal frequency. .

The positive pulse P1 and the negative pulse P2 are input to the input terminals (1) and (2) of the switch SW1, and the switch SW1 is controlled by the control signal output from the Gon Sync discriminating circuit (3). Is switched and the sync signal is added to the video signal (video signal (a), (c), (e)), positive polarity pulse P1 is output, and when the sync signal is not added (video signal The signal (g) outputs a negative pulse P2.

Further, the mode switching circuit (4) outputs a Hi signal when the horizontal frequency is high (video signals (c) and (e)) and outputs a low horizontal frequency (video signals (a) and (b)). G)) outputs the LOW signal.

Therefore, when the horizontal frequency is high, the transistor Q2 is turned on, and when the horizontal frequency is low, the transistor Q2 is turned off. In the former case, the capacitor C2 is grounded to GND, and in the latter case, one side of the capacitor C2 is connected. Is open. Table 1 summarizes the above circuit operations.

[0019]

[Table 1]

By the way, in the circuit including the resistor R2, the capacitor C2, and the transistor Q2, when the transistor Q2 is off (when the horizontal frequency is low), the output pulse of the switch SW1 is differentiated by the capacitor C1 and the resistor R1. Further, when the transistor Q2 is on (when the horizontal frequency is high), the resistor R2 is grounded AC through the capacitor Q2, so that the output pulse of SW1 is generated by the parallel resistance of the capacitor C1, the resistor R1, and the resistor R2. Differentiated. Therefore, in the latter case, since the time constant is shorter than that in the former case, the output pulse width appearing at the collector of the transistor Q1 becomes narrower. Considering the above, the timing of the clamp pulse is summarized in the lower part of Table 1.

As the Gon Sync discriminating circuit (3), an amplitude separating circuit using a comparator can be considered as an example. The most accurate method is to count the horizontal frequency by using a microcomputer for the mode switching circuit (4).

[0022]

[Effect of device]

 As described above, the clamp pulse generation circuit of the present invention has a high horizontal frequency by switching the pulse width of the clamp pulse, and when the back porch portion is narrow, the clamp pulse width is narrowed to prevent overlapping with the video period. When the horizontal frequency is low and the back pouch is wide, the clamp pulse width can be widened to perform stable DC level holding operation. Furthermore, by switching the rising timing of the clamp pulse, it is possible to clamp at the same level regardless of whether the video signal contains a sync signal, so a stable DC level with no change in brightness can be obtained. Can hold.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a clamp pulse generation circuit of the present invention.

FIG. 2 is a circuit configuration diagram of a conventional clamp pulse generation circuit.

FIG. 3 is a timing chart showing a timing relationship between a video signal and a clamp pulse.

[Explanation of symbols]

 1 SW1 Input Terminal 2 SW1 Input Terminal 3 Gon Sync Discrimination Circuit 4 Mode Switching Circuit SW1 Switching Switch Q2 Transistor P1 Positive Pulse P2 Negative Pulse

Claims (2)

[Scope of utility model registration request] 1. A clamp pulse generating circuit for operating a clamp circuit for fixing the DC level of a video amplifier, wherein a frequency discriminating means for discriminating the level of a horizontal frequency and a pulse of a clamp pulse by a discriminative output of the frequency discriminating means. A clamp pulse generation circuit comprising: a pulse width control means for controlling a width. 2. A clamp pulse generating circuit for operating a clamp circuit for fixing a DC level of a video amplifier, wherein a frequency discriminating means for discriminating the level of a horizontal frequency and a discriminative output of the frequency discriminating means determines a clamp pulse The pulse width control means for controlling the pulse width, the synchronization signal determination means for determining the presence or absence of a synchronization signal added to the blanking period of the video signal, and the output of the synchronization signal determination means for the rising timing of the clamp pulse. And a rising control means for controlling the above.