JPH06132744A - Electric power amplifier device - Google Patents

Abstract

PURPOSE:To provide an electric power amplifier device curtailed in the number of SW power sources and reduced in power consumption. CONSTITUTION:This device is constituted of first and second transistors 2 and 3 driven 2 and 3 driven in accordance with a first power amplifier 1, third and fourth transistors 15 and 16 driven in accordance with a second power amplifier 13, first and second full wave rectifier circuits 17 and 18 and first and second SW power sources 4 and 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power amplifying device capable of reducing collector loss of an output transistor and having a simple structure.

[0002]

2. Description of the Related Art An example of a conventional power amplifier is shown in FIG. 2 and explained. FIG. 2 shows a commonly used OCL complementary SEPP (complementary symmetrical single ended push-pull) circuit. In the figure, IN is an input terminal to which an input signal from the previous stage is applied, A is an amplifier, and one input terminal + is connected to the input terminal IN and a resistor R
It is grounded via g and the other input terminal-is grounded via a resistor Re.

+ B and -B are power supplies of opposite polarities,
Q _1, Q ₂ is the output transistor of the opposite polarity, respectively, Q ₁
Is an NPN type transistor, and Q ₂ is a PNP type transistor. The power supply + B, -B is connected to the collector in correspondence as comprising a forward polarity to the transistors Q _1, Q _2. OUT is an output terminal, and RL is a load connected to the output terminal OUT.

In the complementary symmetric circuit composed of the transistors Q ₁ and Q ₂ , the bases are commonly connected to serve as an input end, the input end is connected to the output end of the amplifier A, and the emitter is commonly connected to serve as an output end. The output terminal is connected to the input terminal-of the amplifier A through the resistor Rf and serves as an output terminal. In this circuit, the transistor Q ₁ or Q ₂ operates as an emitter follower according to the positive / negative polarity of the input. is there.

That is, the input signal from the previous stage applied to the input terminal IN is amplified by the amplifier A and further power-amplified by the output transistors Q ₁ and Q _{2 in the} next stage, and the output is supplied to the load RL. However, in such a power amplifier, the power supply voltage is required to have a value obtained by adding a voltage loss component such as a transistor to the maximum output voltage. Then, a voltage of a value obtained by subtracting the output voltage from the power supply voltage is applied between the collector and the emitter of the output transistor, and power of a value obtained by multiplying this value by the output current is the loss of the output transistor. Further, the collector-emitter voltage V _CE fluctuates between the maximum output and the normal state, and the loss of the output transistor is large, which causes the output transistor to generate heat. For this reason, an expensive transistor or cooling means that can endure this heat generation is required. Further, there is a drawback that the collector-emitter breakdown voltage of the output transistor needs to be at least twice the power supply voltage.

In view of the above, it has been proposed that the power supply voltage from the power supply, which has been a fixed value in the past, can be varied to supply the power supply voltage according to the input signal level to reduce the collector loss. FIG. 3 shows such a positive and negative dual power source power amplifying device, in which the collector of the first and second transistors (2) and (3) to which the output signal of the power amplifier (1) is applied is the first. And the second SW (switching) power supplies (4) and (5) are connected. The output signal generated at the terminal (7) of the load (6) is supplied to the first or second through the level shift DC power supply (8) or (9).
It is applied to the control circuit (10) or (11). Now, it is assumed that an output signal indicated by a dotted line in FIG. 4 is generated in the load (6).
During the positive half cycle of the output signal, the first control circuit (1
0) turns on / off the switch (12) so that a power supply voltage (V _BA ) having a magnitude corresponding to the level of the output signal is generated as shown by the solid line in FIG. At this time, the second control circuit (1
1) keeps the value of the output power supply voltage (V _BB ) small and constant in response to the positive output signal. Conversely, when the output signal generated in the load (6) is in the negative half cycle period, the first control circuit (10) causes the power supply voltage V
_BA is kept constant, and the second control circuit (11) controls the power supply voltage V _BB.
Is changed according to the output signal level. As a result, the power supply voltages V _BA and V _BB change as shown by the solid line in FIG. Figure 4
As is clear from the figure, since the power supply voltage changes following the level of the output signal shown by the dotted line, the collector-emitter voltage V _{CE of} the first and second transistors (2) and (3)
Is always a constant value V _X (values of DC power supplies (8) and (9))
Therefore, the collector loss can be kept low.

By the way, in power amplifiers for automobiles,
A single power supply and output transformer-less configuration is required to reduce weight. Therefore, BTL (Balanced Tran)
Sformerless) drives are commonly used. FIG. 5 shows a single-power-supply power amplifying device using a SW power supply in a BTL drive. The power amplification device of FIG. 5 basically has two sets of the devices of FIG. 3 arranged on the left and right.
The second power amplifier (13) generates an inverted signal of the input signal and applies it to the load (6), so that alternating signals having opposite phases are applied to both ends of the load (6). This is shown in FIGS. 6 and 7. The signal shown by the dotted line in FIG. 6 is generated at the terminal (7) side of the load (6), and the signal shown by the dotted line in FIG. 7 is generated at the terminal (14) side of the load (6). Shows. The power supply voltages V _BA and V _BB generated at the collectors of the first and second transistors (2) and (3) are shown by solid lines in FIG. Also, the power supply voltages V _BC and V generated at the collectors of the third and fourth transistors (15) and (16).
_BD is shown by the solid line in FIG.

Therefore, according to the circuit of FIG. 5, it is possible to perform power amplification of a BTL drive that consumes less power.

[0009]

However, the device of FIG. 5 requires four SW power supplies. The choke coil required in the SW power supply is expensive and generates a strong magnetic field during the switching operation, which becomes a noise source. Therefore, reduction of the number of SW power supplies has been desired.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned points, and provides a positive power supply in accordance with a first power amplifier for amplifying an input signal and an output signal of the first power amplifier. A first transistor that generates an output signal, a second transistor that generates an output signal in the negative direction according to the output signal of the first power amplifier, and a second power amplifier that amplifies an inverted input signal of the input signal. A third transistor for generating a negative output signal in response to the output signal of the second power amplifier; and a fourth transistor for generating a positive output signal in response to the output signal of the second power amplifier. A transistor and the first
To a load connected to the fourth transistor and a first full-wave rectifier circuit that full-wave rectifies the output voltage applied to the load and generates a positive full-wave rectified output, and the output voltage applied to the load is full-wave rectified A second full-wave rectification circuit that generates a negative full-wave rectification output; A second switching power supply that supplies a power supply voltage that changes according to the output signal of the second full-wave rectifier circuit to the second transistor.

[0011]

According to the present invention, the positive full-wave rectified output of the output signal generated in the load is detected, and the first signal is detected according to the detected signal.
Control the SW power supply. Further, the negative full-wave rectified output of the output signal is detected, and the second SW power source is controlled according to the detected signal. The output voltage of the first SW power supply is applied to the first and third transistors driven by the negative phase signal, and the output voltage of the second SW power supply is applied to the second and fourth transistors. ing.

[0012]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.
(17) is a first full-wave rectifier circuit in which alternating-current AC signals generated at the terminals (7) and (14) of the load (6) are applied, and only the positive-direction signal component of both signals is extracted, 1
8) is a second full-wave rectifier circuit to which the AC signal is applied and which extracts only the signal component in the negative direction from both signals.

In FIG. 1, the same circuit elements as those in FIG. 5 are designated by the same reference numerals and the description thereof will be omitted. The input signal from the input terminal IN is amplified by the first power amplifier (1) and drives the first and second transistors (2) and (3). The input signal is inverted and amplified by the second power amplifier (13) to drive the third and fourth transistors (15) and (16). Therefore, if a positive input signal is applied, the first and fourth transistors (2) and (1
6) turns on and the second and third transistors (3) and (15) turn off. On the contrary, when a negative input signal is applied, the second and third transistors (3) and (15) are turned on, and the first and fourth transistors (2) and (16) are turned off. Therefore, if the signal of FIG. 8 (a) is generated at the terminal (7), the signal of FIG. 8 (b) is generated at the terminal (14), and the load (6) is driven with double the amplitude. It Figure 8
The signals of (a) and (b) are the first full-wave rectifier circuit (17).
Applied to. FIG. 10 shows a specific circuit diagram of the first full-wave rectifier circuit (17). Input terminals (19) and (2 in FIG.
0) signals of opposite phases applied to the output terminal (2)
1) is full-wave rectified in the positive direction and output. Therefore, the signal shown in FIG. 8C is generated from the first full-wave rectifier circuit (17), and the first SW power supply (4) operates in response to the signal. The first SW power supply (4) generates a power supply voltage V _BA similar to the signal of FIG. 8 (c) as shown by the solid line in FIG. 12 (a), and supplies it to the collectors of the first and third transistors (2) and (15). Apply. Since the dotted line in FIG. 12A shows the output signal generated at the terminal (7), it is clear that the power supply voltage fluctuates according to the output signal level and the first transistor (2) has a small collector loss. is there.

On the other hand, the second full-wave rectifier circuit (18) is shown in FIG.
When the signals of FIGS. 9 (a) and 9 (b) are applied to the input terminals (22) and (23), the output terminal (24) of the negative direction of FIG. Generates full-wave rectified output. Therefore, the second SW power supply (5) generates the power supply voltage V _BB indicated by the solid line in FIG. 12 (a) and applies it to the collectors of the second and fourth transistors (3) and (16).

Therefore, in this case as well, since the power supply voltage V _BB changes according to the output signal level, the second transistor (3) has a small collector loss. A signal having a phase opposite to that of the output signal indicated by the dotted line in FIG. 12A is generated at the terminal (14). The signal is as shown by the dotted line in FIG. 12B, but the power supply voltages V _BA and V _BB also change as shown by the solid line, so that the third signal is the same as in the case of FIG. 12A. And the collector loss of the fourth transistors (15) and (16) is small.

By the way, as described above, the power supply voltages V _BA and V
_{When BB} is changed, the power supply voltage is unnecessarily applied to the non-operating transistor. For example, in FIG.
During the period T of (b), the positive power supply voltage V _BA applied to the collector of the third transistor (15) is wasted. However, in this case, the third transistor (15)
Is almost off (about idling current), and no current flows, so there is almost no power consumption. For that reason,
Virtually no problem.

Therefore, according to the circuit of FIG. 1, two SWs are provided.
BTL type power amplification can be performed with the power supply.

[0018]

As described above, according to the present invention, it is possible to provide a power amplification device having a BTL structure that consumes less power only by using two SW power supplies. Therefore, it is possible to perform power amplification with a simple configuration, a low cost, and a low noise generation.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a power amplification device of the present invention.

FIG. 2 is a circuit diagram showing a conventional power amplification device.

FIG. 3 is a circuit diagram showing a conventional power amplification device.

FIG. 4 is a waveform diagram for explanation of FIG.

FIG. 5 is a circuit diagram showing a conventional power amplification device.

FIG. 6 is a waveform diagram for explanation of FIG.

FIG. 7 is a waveform diagram for explaining FIG.

FIG. 8 is a waveform diagram for explaining FIG.

9 is a waveform diagram for explaining FIG. 1. FIG.

10 is a specific circuit diagram of the first full-wave rectifier circuit of FIG.

11 is a specific circuit diagram of the second full-wave rectifier circuit of FIG.

FIG. 12 is a waveform diagram for explanation of FIG. 1.

[Explanation of symbols]

 (1) First power amplifier (2) First transistor (3) Second transistor (4) First SW power supply (5) Second SW power supply (6) Load (13) Second power amplifier (15) Third transistor (16) ) Fourth transistor (17) First full-wave rectifier circuit (18) Second full-wave rectifier circuit

Claims (2)

[Claims] 1. A first power amplifier for amplifying an input signal, a first transistor for generating an output signal in a positive direction in response to an output signal of the first power amplifier, and an output signal for the first power amplifier. A second transistor for generating an output signal in the negative direction, a second power amplifier for amplifying an inverted input signal of the input signal, and a second transistor for the negative direction in accordance with the output signal of the second power amplifier. A third transistor generating an output signal, a fourth transistor generating a positive output signal in response to the output signal of the second power amplifier, a load connected to the first to fourth transistors, A first full-wave rectifier circuit that full-wave rectifies the output voltage applied to the load to generate a positive full-wave rectified output, and a full-wave rectification of the output voltage applied to the load to generate a negative full-wave rectified output. A second full-wave rectifier circuit, and A first switching power supply that supplies a power supply voltage that changes according to the output signal of the first full-wave rectifier circuit to the first transistor; A second switching power supply for supplying the transistor, and a power amplification device. 2. A positive direction output to the load, comprising: the first switching power supply that supplies a power supply voltage to the third transistor; and the second switching power supply that supplies a power supply voltage to the fourth transistor. The first and fourth transistors are operated when generating a signal, and the third and second transistors are operated when generating a negative output signal to the load.
The power amplification device described.