JPH06132322A - Charge detecting circuit - Google Patents
Charge detecting circuitInfo
- Publication number
- JPH06132322A JPH06132322A JP4280006A JP28000692A JPH06132322A JP H06132322 A JPH06132322 A JP H06132322A JP 4280006 A JP4280006 A JP 4280006A JP 28000692 A JP28000692 A JP 28000692A JP H06132322 A JPH06132322 A JP H06132322A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- wiring
- conductor
- charge detection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims abstract description 19
- 238000001514 detection method Methods 0.000 claims description 24
- 230000003321 amplification Effects 0.000 claims 1
- 238000003199 nucleic acid amplification method Methods 0.000 claims 1
- 230000035945 sensitivity Effects 0.000 abstract description 14
- 229920006395 saturated elastomer Polymers 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 230000011664 signaling Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、ＣＣＤ遅延素子や固
体撮像素子の出力部に用いられる電荷検出回路に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge detection circuit used in an output section of a CCD delay element or a solid-state image pickup element.
【０００２】[0002]
【従来の技術】映像信号の遅延に使われるＣＣＤ遅延素
子やビデオカメラに使われるＣＣＤ固体撮像素子の出力
部は、電位変化ΔＶ＝電荷量変化ΔＱ÷容量Ｃの関係を
利用して信号電荷を検出するようにしている。図３は、
従来のＣＣＤ固体撮像素子の出力部の構成を示す概略図
である。同図において、１は半導体基板である。２は電
荷検出部で、半導体基板１内に電位的に浮いた基板とは
反対導伝型の浮遊拡散層３と浮遊拡散層３の電位を定期
的にリセットするリセット用ＦＥＴ４とから構成されて
いる。５は出力バッファ回路で、ＭＯＳＦＥＴを用いた
２段ソースフォロワで形成されている。６は電荷検出部
２と出力バッファ回路５とを接続する配線である。2. Description of the Related Art An output portion of a CCD delay element used for delaying a video signal or a CCD solid-state image sensor used for a video camera uses a relationship of potential change ΔV = charge amount change ΔQ ÷ capacitance C to store signal charge. I'm trying to detect. Figure 3
It is the schematic which shows the structure of the output part of the conventional CCD solid-state image sensor. In the figure, 1 is a semiconductor substrate. Reference numeral 2 denotes a charge detection unit, which is composed of a floating diffusion layer 3 of a conduction type opposite to the substrate floating in the semiconductor substrate 1 and a reset FET 4 for periodically resetting the potential of the floating diffusion layer 3. There is. Reference numeral 5 is an output buffer circuit, which is formed by a two-stage source follower using MOSFETs. Reference numeral 6 is a wiring that connects the charge detection unit 2 and the output buffer circuit 5.
【０００３】また、ＣFDは浮遊拡散層３の容量、ＣLNは
配線６の配線容量、ＣINは出力バッファ回路５の入力容
量を示し、ＶＤＤは出力バッファ回路５の電源、ＶＧは
出力バッファ回路５を構成する２段ソースフォロワのロ
ードＦＥＴ用ゲート電圧、ＶＲＤは電荷検出部２のリセ
ット電位を示す。φＲはリセット用ＦＥＴを制御するリ
セットパルスである。C FD is the capacitance of the floating diffusion layer 3, C LN is the wiring capacitance of the wiring 6, C IN is the input capacitance of the output buffer circuit 5, VDD is the power supply of the output buffer circuit 5, and VG is the output buffer. The load FET gate voltage of the two-stage source follower that constitutes the circuit 5, VRD indicates the reset potential of the charge detection unit 2. φR is a reset pulse for controlling the reset FET.
【０００４】上記のように構成された従来のＣＣＤ固体
撮像素子の出力部動作について以下説明する。まず、リ
セット用ＦＥＴ４をオンにして浮遊拡散層３の電位を一
定のリセット電位ＶＲＤに保つ。その後、このリセット
用ＦＥＴ４をオフにする。ホトダイオードで光電変換さ
れて生じた信号電荷は，図示しない垂直転送ＣＣＤおよ
び水平転送ＣＣＤによって順次浮遊拡散層３に転送され
る。浮遊拡散層３の電位は信号電荷によってリセット電
位ＶＲＤから変化し、この電位変化が、出力バッファ５
を通して出力される。The operation of the output section of the conventional CCD solid-state image pickup device constructed as described above will be described below. First, the reset FET 4 is turned on to keep the potential of the floating diffusion layer 3 at a constant reset potential VRD. After that, the reset FET 4 is turned off. The signal charges generated by photoelectric conversion by the photodiode are sequentially transferred to the floating diffusion layer 3 by a vertical transfer CCD and a horizontal transfer CCD (not shown). The potential of the floating diffusion layer 3 changes from the reset potential VRD due to the signal charge, and this change in potential is caused by the output buffer 5
Is output through.
【０００５】図４に示すように、出力信号波形は、浮遊
拡散層３がリセット電位ＶＲＤにリセットされるリセッ
ト期間ＴＲ、リセットから信号電荷が流入するまでのフ
ィードスルー期間Ｔ１、信号電荷が流入する信号期間Ｔ
２からなる。信号電荷は、水平転送期間Ｔｃを１画素分
（ホトダイオード１個分）として、全画素が時系列的に
出力される。As shown in FIG. 4, the output signal waveform has a reset period TR in which the floating diffusion layer 3 is reset to the reset potential VRD, a feed-through period T1 from resetting until signal charges flow in, and signal charges flow in. Signal period T
It consists of two. With respect to the signal charge, all pixels are output in time series with the horizontal transfer period Tc as one pixel (one photodiode).
【０００６】このような出力部において、信号電荷をＱ
S と出力信号ＶＯの関係は、センス容量をＣS 、出力バ
ッファ回路の電圧ゲインをＧとすると、( 数１) に示す
ようになる。In such an output section, the signal charge is Q
The relationship between S and the output signal VO is as shown in (Equation 1) where C S is the sense capacitance and G is the voltage gain of the output buffer circuit.
【０００７】[0007]
【数１】ＶＯ＝Ｇ・ＱS ／ＣS また、センス容量ＣS は、浮遊拡散層３の容量ＣFD、配
線６の配線容量ＣLN、出力バッファ回路の入力容量ＣIN
との間に（数２）に示す関係がある。[Formula 1] VO = G · Q S / C S Further , the sense capacitance C S is the capacitance C FD of the floating diffusion layer 3, the wiring capacitance C LN of the wiring 6, and the input capacitance C IN of the output buffer circuit.
And the relationship shown in (Equation 2).
【０００８】[0008]
【数２】ＣS ＝ＣFD＋ＣLN＋ＣIN したがって、ＣＣＤ固体撮像素子の出力部の感度は（数
３）に示すようになる。[Number 2] Thus C S = C FD + C LN + C IN, the sensitivity of the output portion of the CCD solid-state image pickup device is as shown in equation (3).
【０００９】[0009]
【数３】感度＝ＶＯ／ＱS ＝Ｇ／ＣS ＝Ｇ／（ＣFD＋Ｃ
LN＋ＣIN）[Expression 3] Sensitivity = VO / Q S = G / C S = G / (C FD + C
LN + C IN )
【００１０】[0010]
【発明が解決しようとする課題】上記した従来のＣＣＤ
固体撮像素子の出力部の構成では、低照度時のＳ／Ｎを
改善するためにセンス容量ＣS を小さくして感度を上げ
ると、標準照度や飽和照度の時に出力信号が大きくなり
すぎ、ＣＣＤ固体撮像素子の出力信号を処理する外部回
路の入力レンジが飽和し、ダイナミックレンジが低下す
るという問題点があった。SUMMARY OF THE INVENTION The conventional CCD described above.
In the configuration of the output unit of the solid-state image sensor, if the sense capacitance C S is reduced to improve the sensitivity in order to improve the S / N at low illuminance, the output signal becomes too large at the standard illuminance or saturated illuminance, and the CCD There is a problem that the input range of the external circuit that processes the output signal of the solid-state image sensor is saturated and the dynamic range is reduced.
【００１１】したがって、この発明の目的は、出力部の
感度を照度に対応して調整することができ、外部回路の
入力レンジの飽和を防止してダイナミックレンジを拡大
することができる電荷検出回路を提供することである。Therefore, an object of the present invention is to provide a charge detection circuit capable of adjusting the sensitivity of the output section in accordance with the illuminance, preventing the saturation of the input range of the external circuit, and expanding the dynamic range. Is to provide.
【００１２】[0012]
【課題を解決するための手段】この発明の電荷検出回路
は、電荷検出部と、電荷検出部の出力信号を入力する出
力バッファ回路と、出力信号を入力し外部から利得制御
可能な増幅回路と、電荷検出部と出力バッファ回路とを
接続する配線と並行に形成された導体を備え、この導体
と増幅回路の出力側とを接続している。A charge detection circuit according to the present invention comprises a charge detection section, an output buffer circuit for inputting an output signal of the charge detection section, and an amplifier circuit for inputting the output signal and controlling a gain from the outside. A conductor that is formed in parallel with the wiring that connects the charge detection unit and the output buffer circuit is provided, and the conductor is connected to the output side of the amplifier circuit.
【００１３】[0013]
【作用】この発明の構成によれば、出力信号を入力し外
部から利得制御可能な増幅回路と、電荷検出部と出力バ
ッファ回路とを接続する配線と並行に形成された導体を
備え、この導体と増幅回路の出力側とを接続しているの
で、出力信号に対する配線と導体間の等価的な配線容量
を増幅回路の電圧ゲインによって変化させてセンス容量
を変化させることができ、出力部の感度を照度に対応し
て調整することができる。According to the structure of the present invention, it is provided with an amplifier circuit for inputting an output signal and capable of gain control from the outside, and a conductor formed in parallel with a wiring connecting the charge detection unit and the output buffer circuit. Since the amplifier and the output side of the amplifier circuit are connected, the equivalent wiring capacitance between the wiring and the conductor for the output signal can be changed by the voltage gain of the amplifier circuit to change the sense capacitance. Can be adjusted according to the illuminance.
【００１４】[0014]
【実施例】以下この発明の実施例を図面を参照しながら
説明する。図１は、この発明の実施例であるＣＣＤ固体
撮像素子の出力部を形成する電荷検出回路の構成を示す
概略図で、同図において、従来例を示す図３と同符号を
付したものは同じものを示す。この実施例は、従来例に
対して外部から利得制御可能な増幅回路７と電荷検出部
２と出力バッファ回路５の入力を接続する配線６と並行
に形成された導体８が別途設けられ、この導体８と増幅
回路７の出力側とを接続している。この実施例の場合、
導体８は配線６の下層に形成されている。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram showing a configuration of a charge detection circuit forming an output portion of a CCD solid-state image pickup device according to an embodiment of the present invention. In FIG. 1, the same reference numerals as those in FIG. Show the same. In this embodiment, an amplifier circuit 7 whose gain can be controlled from the outside, a conductor 6 formed in parallel with a wiring 6 for connecting the inputs of the charge detection unit 2 and the output buffer circuit 5 are provided separately from the conventional example. The conductor 8 and the output side of the amplifier circuit 7 are connected. In this example,
The conductor 8 is formed in the lower layer of the wiring 6.
【００１５】図１において、従来例を示す図３と同様
に、ＣFDは浮遊拡散層３の容量、ＣLNは配線６と導体８
間の配線容量、ＣINは出力バッファ回路５の入力容量を
示し、ＶＤＤは出力バッファ回路５の電源、ＶＧは出力
バッファ回路５を構成する２段ソースフォロワのロード
ＦＥＴ用ゲート電圧、ＶＲＤは電荷検出部２のリセット
電位、φＲはリセット用ＦＥＴを制御するリセットパル
ス、ＶＧＣは増幅回路７の利得を制御する利得制御信号
を示す。In FIG. 1, similarly to FIG. 3 showing the conventional example, C FD is the capacitance of the floating diffusion layer 3, and C LN is the wiring 6 and the conductor 8.
The wiring capacitance between them, C IN indicates the input capacitance of the output buffer circuit 5, VDD is the power supply of the output buffer circuit 5, VG is the gate voltage for the load FET of the two-stage source follower configuring the output buffer circuit 5, and VRD is the charge. The reset potential of the detection unit 2, φR is a reset pulse for controlling the reset FET, and VGC is a gain control signal for controlling the gain of the amplifier circuit 7.
【００１６】以上のように構成された電荷検出回路を用
いたＣＣＤ固体撮像素子の出力部の動作について説明す
る。まず、この発明の原理となる容量についての考え方
を図２を用いて説明する。図２（ａ）に示すように、容
量Ｃの他端子をＤＣ電位に固定したとき、信号ＶＩＮか
らみた等価容量Ｃeq1 は（数４）に示すようになる。The operation of the output section of the CCD solid-state image pickup device using the charge detection circuit configured as described above will be described. First, the concept of the capacity, which is the principle of the present invention, will be described with reference to FIG. As shown in FIG. 2A, when the other terminal of the capacitance C is fixed to the DC potential, the equivalent capacitance C eq1 seen from the signal VIN becomes as shown in ( Equation 4).
【００１７】[0017]
【数４】 Ｃeq1 ＝ΔＱ／ΔＶＩＮ＝Ｃ・（ＶＩＮ−０）／ＶＩＮ＝Ｃ 一方、図２（ｂ）に示すように、容量Ｃの他端子にＡ・
ＶＩＮの信号が接続されたとき、信号ＶＩＮからみた容
量Ｃeq2 は（数５）に示すようになる。[ Equation 4] C eq1 = ΔQ / ΔVIN = C · (VIN−0) / VIN = C On the other hand, as shown in FIG.
When the VIN signal is connected, the capacitance C eq2 seen from the signal VIN becomes as shown in ( Equation 5).
【００１８】[0018]
【数５】 Ｃeq2 ＝ΔＱ／ΔＶＩＮ＝Ｃ・（ＶＩＮ−Ａ・ＶＩＮ）／ＶＩＮ ＝（１−Ａ）・Ｃ 電荷検出の基本動作は従来例と同様であるが、増幅回路
７の電圧ゲインをＢ（Ｂ≧０）とすると、増幅回路７の
出力はＢ・ｖs となる。したがって、（数５）により出
力信号ｖs に対する配線６と導体９問の等価的な配線容
量は（１−Ｂ）・ＣLNとなり、センス容量は（数６）、
感度は（数７）に示すようになる。[ Equation 5] C eq2 = ΔQ / ΔVIN = C · (VIN−A · VIN) / VIN = (1−A) · C The basic operation of charge detection is the same as the conventional example, but the voltage gain of the amplifier circuit 7 is Is B (B ≧ 0), the output of the amplifier circuit 7 is B · v s . Therefore, according to (Equation 5), the equivalent wiring capacitance of the wiring 6 and the conductor 9 for the output signal v s is (1-B) · C LN , and the sense capacitance is (Equation 6),
The sensitivity is as shown in (Equation 7).
【００１９】[0019]
【数６】ＣS ＝ＣFD＋（１−Ｂ）・ＣLN＋ＣIN [Equation 6] C S = C FD + (1-B) ・ C LN + C IN
【００２０】[0020]
【数７】 感度＝Ｇ／［ＣFD＋（１−Ｂ）・ＣLN＋ＣIN］ したがって、照度に応じて利得制御信号ＶＧＣで増幅回
路７のでんあるゲインＢを０から１まで変化させること
により、ＣＣＤ固体撮像素子の出力部の感度を（数３）
から（数８）まで変化させることができる。[Expression 7] Sensitivity = G / [C FD + (1−B) · C LN + C IN ] Therefore, the gain B of the amplifier circuit 7 is changed from 0 to 1 by the gain control signal VGC according to the illuminance. Therefore, the sensitivity of the output section of the CCD solid-state image sensor is
To (Equation 8).
【００２１】[0021]
【数８】感度＝Ｇ／［ＣFD＋ＣIN］ 上記したように、この実施例によれば、出力信号を入力
し外部から利得制御可能な増幅回路７と、電荷検出部２
と出力バッファ回路５とを接続する配線６と並行に形成
された導体８を備え、この導体８と増幅回路７の出力側
とを接続しているので、出力信号に対する配線６と導体
８間の等価的な配線容量を増幅回路７の電圧ゲインによ
って変化させてセンス容量を変化させることができ、出
力部の感度を照度に対応して調整することができる。し
たがって、この実施例回路によれば、照度に対応して感
度を制御することができるので、外部回路の入力レンジ
の飽和を防止することができ、システムのダイナミック
レンジを拡大することができる。このため、利得制御可
能なＣＣＤ固体撮像素子の出力部を構成することができ
る。[Equation 8] Sensitivity = G / [C FD + C IN ] As described above, according to this embodiment, the amplifier circuit 7 that receives the output signal and can control the gain from the outside, and the charge detection unit 2 are provided.
Since the conductor 8 formed in parallel with the wiring 6 for connecting the output buffer circuit 5 to the output buffer circuit 5 is connected to the output side of the amplifier circuit 7, the conductor 8 is connected between the wiring 6 and the conductor 8 for an output signal. The equivalent wiring capacitance can be changed by the voltage gain of the amplifier circuit 7 to change the sense capacitance, and the sensitivity of the output section can be adjusted according to the illuminance. Therefore, according to the circuit of this embodiment, the sensitivity can be controlled according to the illuminance, so that the saturation of the input range of the external circuit can be prevented and the dynamic range of the system can be expanded. Therefore, the output part of the CCD solid-state image sensor capable of gain control can be configured.
【００２２】[0022]
【発明の効果】この発明の電荷検出回路によれば、出力
信号を入力し外部から利得制御可能な増幅回路と、電荷
検出部と出力バッファ回路とを接続する配線と並行に形
成された導体を備え、この導体と増幅回路の出力側とを
接続しているので、出力信号に対する配線と導体間の等
価的な配線容量を増幅回路の電圧ゲインによって変化さ
せてセンス容量を変化させることができ、出力部の感度
を照度に対応して調整することができる。したがって、
この実施例回路によれば、照度に対応して感度を制御す
ることができるので、利得制御可能なＣＣＤ固体撮像素
子の出力部を構成することができる。According to the charge detection circuit of the present invention, an amplifier circuit capable of inputting an output signal and controlling the gain from the outside, and a conductor formed in parallel with the wiring connecting the charge detection unit and the output buffer circuit are provided. Since the conductor is connected to the output side of the amplifier circuit, the equivalent capacitance between the wiring for the output signal and the conductor can be changed by the voltage gain of the amplifier circuit to change the sense capacitance. The sensitivity of the output unit can be adjusted according to the illuminance. Therefore,
According to the circuit of this embodiment, the sensitivity can be controlled according to the illuminance, so that the output section of the CCD solid-state image sensor capable of gain control can be configured.
【図１】この発明の実施例である電荷検出回路をＣＣＤ
固体撮像素子の出力部に使用した場合の構成を示す概略
図である。FIG. 1 is a block diagram showing a charge detection circuit according to an embodiment of the present invention as a CCD.
It is a schematic diagram showing composition when used for an output part of a solid-state image sensing device.
【図２】この発明の原理となる容量に対する考えを説明
する図である。FIG. 2 is a diagram for explaining an idea of a capacity, which is the principle of the present invention.
【図３】従来のＣＣＤ固体撮像素子の出力部の構成を示
す概略図である。FIG. 3 is a schematic diagram showing a configuration of an output unit of a conventional CCD solid-state imaging device.
１ 半導体基板 ２ 電荷検出部 ３ 浮遊拡散層 ４ リセット用ＦＥＴ ５ 出力バッファ回路 ６ 配線 ７ 増幅回路 ８ 導体 1 Semiconductor Substrate 2 Charge Detection Section 3 Floating Diffusion Layer 4 FET for Reset 5 Output Buffer Circuit 6 Wiring 7 Amplifier Circuit 8 Conductor
Claims (1)
号を入力する出力バッファ回路と、前記出力信号を入力
し外部から利得制御可能な増幅回路と、前記電荷検出部
と前記出力バッファ回路とを接続する配線と並行に形成
された導体とを備え、前記導体と前記増幅回路の出力側
とを接続したことを特徴とする電荷検出回路。1. A charge detection unit, an output buffer circuit for inputting an output signal of the charge detection unit, an amplifier circuit for inputting the output signal and capable of gain control from the outside, the charge detection unit and the output buffer circuit. A charge detection circuit, comprising: a wiring formed in parallel with a wiring for connecting to each other, and connecting the conductor to an output side of the amplification circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4280006A JPH06132322A (en) | 1992-10-19 | 1992-10-19 | Charge detecting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4280006A JPH06132322A (en) | 1992-10-19 | 1992-10-19 | Charge detecting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06132322A true JPH06132322A (en) | 1994-05-13 |
Family
ID=17618994
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4280006A Pending JPH06132322A (en) | 1992-10-19 | 1992-10-19 | Charge detecting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06132322A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003101882A (en) * | 2001-09-19 | 2003-04-04 | Sony Corp | Solid-state image pickup element |
-
1992
- 1992-10-19 JP JP4280006A patent/JPH06132322A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003101882A (en) * | 2001-09-19 | 2003-04-04 | Sony Corp | Solid-state image pickup element |
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