JPH06131870A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To keep the operating speed and accurate operation by selecting a word line or a bit line and a row or a column selection signal so as to keep a drive voltage to a prescribed value at all times when the performance of an operation speed and read, write or the like is deteriorated resulting from a dropped power supply voltage. CONSTITUTION:A word line WL and a bit line are selected by row and column selection signals inverse of RAS, inverse of CAS even when a power supply voltage Vcc is lower than a prescribed voltage in the semiconductor integrated circuit 14. Then the drive voltage for the word line WL in the write and read state is not less than a prescribed voltage and a voltage over the prescribed voltage is provided at all times. Thus, even when a potential of a transfer gate NMOS9 is decreased, the storage capacitance of a capacitor 94 is decreased, the read write speed is not deteriorated and no software error and the deterioration in a sense margin are not caused. Thus, the accurate operating speed and the accurate operation are maintained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit which prevents a decrease in operating speed due to a decrease in power supply voltage level.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit, the power supply voltage used is constant, for example, in TTL, V _CC = 5V ±.
It was used only in the range of 10%, and the circuit was also optimized under this power supply voltage condition. In recent years, device miniaturization has progressed due to high capacity and high integration, and reliability cannot be guaranteed at conventional operating voltages. Also, in terms of power consumption, there is a tendency toward lower voltage.

However, at present, this power supply voltage is not standardized, and the market is also mixed. For example, the external power supply is 5V, but the internal voltage is reduced to 3V, or both internal and external are 3V or 3.3V, 5V to 2.V.
There are various usage conditions such as 7V or 6V to 2V.

For example, as devices such as CMOS LSI are miniaturized, the gate length,
Of course, the gate oxide film thickness is also small. Therefore, it is necessary to reduce the power supply voltage with the miniaturization.
The MOS LSI uses a 5V power source for compatibility with TTL and the like.

Therefore, if the power supply voltage is used as it is without being scaled, the electric field inside the device, for example, near the drain of the CMOS becomes high, and if the scaling ratio is 1 / K, it becomes K times. For example, the power supply voltage is 5V
As it is, when the channel length of the NMOS becomes submicron, a high electric field is generated near the drain and accelerated there,
Hot carriers that have obtained high energy are trapped in the thinned gate oxide film, or form interface states, and
The most serious problem is that the threshold voltage V _TH (V _TN ) of the S FET is changed to cause a change over time, resulting in device deterioration due to hot carriers. There is also a problem of breakdown voltage deterioration of the gate oxide film thinned by the electric field K times and dielectric breakdown over time. Further, since both the current density and the power consumption density increase with K ³ , there are problems of reliability due to electromigration and destruction due to heat generation.

Therefore, even if the voltage supplied from the outside is 5V as described above, the above-mentioned problems are solved by using the method of preparing the power supply voltage conversion circuit on-chip and operating the internal circuit at 3V. Has been resolved. Further, as described above, if the internal power supply voltage and the external power supply voltage are lowered to 3 V or 3.3 V, various problems of the device such as the CMOS LSI can be solved, but this time, the systemization with the TTL circuit is realized. The problem arises.

[0007]

As described above, since the usage conditions are constant, the device performance can be secured to some extent by optimization, but when used in a wide range like Optimized with the mainstream 5V center system. That is, since the 5V system is mainly considered, the performance is inevitably deteriorated when the power supply voltage is lowered. This is especially noticeable in terms of access speed.

An object of the present invention is to solve the above-mentioned problems of the prior art, and in a semiconductor integrated circuit used in a wide range of power supply voltage, performance degradation when the power supply voltage is lowered, for example, D
It is an object of the present invention to provide a semiconductor integrated circuit capable of suppressing or preventing deterioration of read and write performances when a voltage level of a word line of a semiconductor memory such as a RAM is lowered and a potential of a transfer gate transistor is lowered.

[0009]

To achieve the above object, the present invention provides a means for detecting a power supply voltage level, and a means for setting a drive voltage level of a predetermined circuit set with respect to the power supply voltage level. And a means for boosting the drive voltage level of the circuit when the power supply voltage level is below a predetermined value.

[0010]

The semiconductor integrated circuit of the present invention detects a drop in the power supply voltage, and when the voltage drops below a certain voltage, partially boosts the voltage of the circuit in which performance degradation such as speed is remarkable due to the drop in voltage. To use. In a conventional semiconductor integrated circuit, for example, when the voltage level of a word line or the like becomes lower than a certain voltage (for example, 4.0 V), the voltage is boosted to ensure the read / write speed. In particular, 1 of NMOS (N channel MOS transistor)
In the case of a dynamic RAM composed of a cell formed of a transistor and one capacitor, the storage capacitance decreases when the potential of the transfer gate decreases, causing a soft error or a decrease in sense margin. However, in the semiconductor integrated circuit of the present invention, , The occurrence of these problems can be eliminated. Therefore, according to the present invention, the voltage level of the signal line such as the word line is not lowered, and the performance deterioration when the power supply voltage is reduced can be prevented.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit according to the present invention will be described in detail with reference to the preferred embodiments shown in the accompanying drawings.

FIG. 1 is a basic configuration diagram of an embodiment of a semiconductor integrated circuit of the present invention. Semiconductor integrated circuit 10 shown in FIG.
Is a word line drive voltage generation circuit (hereinafter, referred to as a generation circuit) 12 and a dynamic random access memory (hereinafter, referred to as DRAM) to which the present invention is applied, which is a feature of the present invention.
14). The DRAM 14 includes a memory cell array 16, a row address buffer 18, a row decoder 20 including a predecoder 21 and a word decoder and driver 22, a column address buffer 24, a column decoder 26, a bit driver 28, and a sense amplifier 3.
0, an input circuit 32, an output circuit 34, and a control circuit 36.

The word line drive voltage generating circuit 12 is shown in FIG.
Power supply voltage level detection as shown in (a) and (b)
The circuit (hereinafter referred to as a detection circuit) 38 and the booster circuit 40
Have Here, the detection circuit 38 is connected to the power supply 39.
Power supply voltage level V_CCFor detecting fluctuations in
Then, as shown in FIG. 2A, one end has a power source 39 (voltage V
_CC) And the other end is grounded (potential V_SS), Multiple
N-channel MOS transistors (three in the illustrated example)
Voltage (hereinafter called NMOS) 42 connected in series
A node N in the middle of the limiter 44 and the voltage limiter 44₁ Or
And an inverter 46 connected to a detection line 45 extending from
And 48.

A plurality of NMs constituting the voltage limiter 44
All of the OSs 42 have their gates connected to one electrode, for example, a drain (or source). N at the top of the figure
The connection between the gate and drain (or source) of the MOS 42a is connected to the power supply 39 (V _CC ). Top NMO
The connection between S42a and the next NMOS 42b becomes the node N ₁ . The other electrode of the lowermost NMOS 42c, for example, the source (or drain) is grounded (V _SS ). The inverters 46 and 48 are connected in series to the detection line 45 extending from the node N ₁ , and the inverter 48 outputs the output signal φ _s bar. Output signal φ from between inverters 46 and 48
_The detection line 47 for extracting _s extends. Where power supply 39
If the voltage V _CC of the output signal is greater than or equal to a predetermined value, the output signal φ _s is “H” and the output signal φ _s bar is “L”,
When the power supply voltage V _CC drops and falls below a predetermined value, the output signal φ
_s becomes "L" and the output signal φ _s bar becomes "H".

Here, in the illustrated example, the number of the NMOSs 42 constituting the voltage limiter 44 is represented by 3, but the number is not limited to this, and the threshold voltage V _{TN of the} NMOS 42, the power supply voltage V _CC and It is determined according to the ground voltage V _SS and may be appropriately selected according to these values.
Further, the position of the node N ₁ for extracting the detection line 45 is not particularly limited to the example shown in the figure, and the fluctuation of the power supply potential V _CC may be changed to the node N _1.
The potential may be taken out as a change in the potential of 1 and the inverter 46 can be driven anywhere.

The booster circuit 40 includes two NMOSs 50 and 52 connected in series, as shown in FIG.
It has a MOS capacitor 54, an NMOS 56 connected in series with the MOS capacitor 54, a P-channel MOS transistor (hereinafter referred to as a PMOS) 58 and an NMOS 60 that form a transmission gate 57. Here, one end of the two NMOSs 50 and 52 connected in series, for example, the drain of the NMOS 50 is a power source (power source voltage V _CC ) 49.
The other end, for example, the source of the NMOS 52 is grounded (V _SS ). Here, the voltage V _CC of the power supply 49 is the same as the power supply 39 measured by the detection circuit 38 and is preferably the same voltage V _CC , but the present invention is not limited to this, and there is a certain relationship. They can be different. Also,
To the gate electrodes of the NMOSs 50 and 52, an internal synchronization (control) signal φ _R having an “H” potential higher than the power supply voltage V _CC and its inverted signal φ _R bar are input. From the connection point (node N ₂ ) of the NMOSs 50 and 52, the word drive line 5
1 is output and outputs the required word drive voltage W _D. That is, if the internal clock signals φ _R and φ _R are H and L, respectively, the NMOS 50 turns on and the NMOS 50 turns on.
When 52 is off, the potential of the node N ₂ becomes the power supply voltage V _CC and the word line drive voltage W _D is output. On the contrary, if L and H, respectively, the NMOS 50 is off and the NMOS 50 is off.
52 is turned off, the voltage of the node N ₂ is 0, and the voltage V _CC is not output to the word drive signal line 51.

The signal line 5 is connected in parallel from the word drive line 51.
3 is branched, and a MOS capacitor 54 is connected to the signal line 53.
Of the NMOS 56, the source of the NMOS 56, for example, is grounded (V _SS ) and the output signal φ _S of the detection circuit 38 is input to the gate. MOS capacitor 54 and NMO
The node N ₃ between the S56, the output is connected to the transmission gate 57, a delay signal itself (the word drive voltage signal W _D) in order to boost the word drive voltage signals W _D to the input of the transmission gate 57 voltage signal W _P is is input. The transmission gate 57 is called a transmission gate or an analog switch, and has a PMOS 58 and an NMO.
The output signals φ _S and φ _{S of the} detection circuit 38, which serve as control signals, are connected to S60 in parallel and are supplied to the respective gates. Here, the capacity and the number of the MOS capacitors 54 that store the charges to be pushed up in accordance with the decrease in the power supply voltage V _CC are not particularly limited, and may depend on the amount of decrease in the power supply potential V _CC , the predetermined voltage value V _0, and the amount of push-up. It may be selected as appropriate.

The row address buffer 18 and the column address buffer 24 of the DRAM 14 are used in the memory cell array 16
In order to access the memory cell of the selected address among them, the address signals A _{0 to} A _n are synchronized with the chip enable signal CE bar or the row select signal (RAS bar) and the column select signal (CAS bar), respectively. Is input from the row address input terminal and the column address input terminal in a time division manner to latch the row address signal and the column address signal.The row address buffer 18 has a chip enable signal CE bar as shown in FIG. 2-input NO with address signal A _i (i = 0, ..., N) as input
It has inverters 64 and 66 connected in series to the outputs of the R gate 62 and the NOR gate 62 and inverting the output signals. The row address signal a _i (i = 0, ..., M) latched between the inverter 64 and the inverter 66 and its inverted output a _i bar are output from the inverter 66.
Here, the column address buffer 24 may have the same configuration as the row address buffer 18 shown in FIG.

The row decoder 20 is for selectively driving the word line WL to access the memory cell at the selected address. The row decoder 20 is shown in FIG.
As shown in (a) and (b), it comprises a predecoder 21 and a word decoder and driver 22. As shown in FIG. 4A, the predecoder 21 uses the row address signal a
3-input NAND gate 6 to which _i and a _i bars are input
, And inverters 70, 74, ..., which invert their outputs, respectively, and output predecode signals RAA0-RAA7, RAB0-RAB7 ,.

The word decoder and driver 22
4B includes a word decoder 76 and a word driver 78 as shown in FIG. 4B. The word decoder 76 is for selectively driving the word lines. The predecode signals RAA0, RAB0, RAC0 ,. Has a 3-input NAND gate 80 to which three signals are input and an inverter 82 which inverts its output, and selects the selected word line W.
The word driver 78 for driving L0 includes an NMOS 84 to which the output of the inverter 82 is connected, and an NMOS 8
It has two series-connected NMOSs 86 and 88 whose gate inputs are the output of 4 and the output of the NAND gate 80. Here, the gate of the NMOS 84 is connected to the power supply (V _CC ). Also, two NMOS 86 connected in series
One end of each of the NMOSs 88 and 88, for example, the drain of the NMOS 86 is connected to the output signal line 51 (output signal W _D ) of the word line drive voltage generating circuit 12, which is a feature of the present invention, and the other end, for example, the source of the NMOS 88, is grounded. And NMOS 86 and 8
The connection portion of 8 is connected to the word line WL0 and is selectively driven.

The memory cell array 16 of the DRAM 14 is
For example, the required number of memory cells 90 shown in FIG. 5 are arranged. The memory cell 90 is a one-transistor type memory cell including one NMOS 92 that functions as a transfer gate and one capacitor (planar type, trench type, stack type, etc.) 94. Where N
The gate of the MOS 92 is connected to the word line WL, its drain is the bit line BL, and its source is the capacitor 9
4 and the other end of the capacitor 94 is grounded (or connected to the memory cell substrate reference potential).

A buffer (input / output amplifier) 30 including a sense amplifier and a write amplifier is selectively driven by the input circuit 32 to write to the memory cell 90 accessed by the word line WL selectively driven at the time of writing. In order to amplify the data transferred via the (data line) BL, and at the time of reading, the data held in the accessed memory cell 90 is read out via the selectively driven bit line BL and output to the output circuit 34. belongs to. The input circuit 32 and the output circuit 34 are controlled by the control circuit 36. A series of operations such as the write operation and the read operation are controlled by an internal synchronization signal in order to prevent the data in the memory cell 90 from being destroyed, and are performed in a predetermined order and timing.

The DRAM 14 is configured as described above, but the present invention is not limited to this and may be any conventionally known DRAM. That is, conventionally known circuits can be used as well as various circuits constituting the DRAM. In the above-mentioned example, the example in which the DRAM 14 using one transistor / one capacitor type cell as a memory cell is applied as the semiconductor integrated circuit 10 of the present invention has been described, but the present invention is not limited to this, and the memory is limited to the DRAM. Not, SRAM, ROM, PROM, mask RO
M, EPROM, E ² PROM, CCD memory, CA
It may be M, an image memory, or the like.

The semiconductor integrated circuit of the present invention is basically configured as described above, and its operation will be described below. In the semiconductor integrated circuit 10 shown in FIG. 1, the DR is changed by the row and column selection signals RAS and CAS.
When AM14 is in the write or read state,
In the word line drive voltage generation circuit 12, a case where the power supply voltage V _CC is higher than a predetermined value V ₀ set in advance and a case where it is lower than the predetermined value V ₀ will be described separately.

First, when the power supply voltage V _CC is equal to or higher than a preset predetermined value V ₀ , the output signals φ _S and φ _S are H and L, respectively, so that the NMOS 56 is turned on and the transmission gate 57 is turned on. The push-up voltage signal W _P is not transmitted from the OFF state. Therefore, as shown in FIG. 7A, when the internal synchronizing signals φ _R and φ _R become H and L, respectively, the NMOS 50 is turned on, the NMOS 52 is turned off, and the potential W _D of the word drive line 51 rises. , Power supply 4
It becomes a voltage V _{CC of} 9.

On the other hand, the internal synchronizing signal φ_R And φ_R 
The bars become H and L respectively, and the NMOS 50 turns off.
Power supply to the word drive line 51.
Pressure V _CCIs applied to the potential W, as shown in FIG.
_D Rises, V_CCHowever, the power supply voltage V_CCIs a predetermined value
V₀ Lower, the output signal φ_S And φ_S That's the bar
Becomes L and H, the NMOS 56 turns off, and the transmission gate
To 57 turns on. Therefore, the MOS capacitor 54
Push-up voltage signal W_P Is charged by. For this reason,
The word drive line 51 is charged in the MOS capacitor 54
Its potential W due to electric charge_D Is V_CCPushed up from
Fixed value V₀ The above voltage is required.

Thus, in the semiconductor integrated circuit 10 of the present invention, even if the power supply voltage V _CC becomes lower than the predetermined value V ₀ , as shown in FIG. 8, row and column selection signals RAS and When the word line WL or the bit line BL is selected by the CAS bar and the write state is in the read state, the drive voltage W _D for driving the word line WL does not fall below a predetermined value and always has a voltage equal to or higher than the predetermined value. The potential of the transfer gate (NMOS) 92 is not lowered, the storage capacity of the capacitor 94 is reduced, the read / write speed is not reduced, and the soft error and the sense margin are not reduced. Therefore, implementing the present invention in a memory such as a DRAM is
It has a great effect in terms of operation speed and accuracy of operation.

[0028]

As described above in detail, according to the present invention, in a semiconductor integrated circuit used in a wide range of power supply voltages, the performance is deteriorated when the power supply voltage is lowered, for example, the operation speed is lowered and reading and writing are performed. It is possible to prevent performance deterioration.

[Brief description of drawings]

FIG. 1 is a basic configuration diagram of an embodiment of a semiconductor integrated circuit according to the present invention.

2A and 2B are circuit diagrams of an embodiment of a power supply voltage level detection circuit and a booster circuit of a word line drive voltage generation circuit of the semiconductor integrated circuit shown in FIG. 1, respectively.

3 is a circuit diagram of an embodiment of a row address buffer of the semiconductor integrated circuit shown in FIG.

4A and 4B are circuit diagrams of an embodiment of a predecoder and a word decoder and driver of the semiconductor integrated circuit shown in FIG. 1, respectively.

5 is a circuit diagram of an example of a memory cell as a constituent unit of the memory cell array of the semiconductor integrated circuit shown in FIG.

6A and 6B are examples of time charts of voltages of respective parts of the word line drive voltage generation circuit shown in FIG. 2 when the power supply voltage is higher and lower than a predetermined value, respectively.

7 is an example of a time chart of row and column selection signals RAS bar and CAS bar and word line drive voltage W _D of the semiconductor integrated circuit shown in FIG. 1. FIG.

[Explanation of symbols]

10 semiconductor integrated circuit 12 word line drive voltage generation circuit 14 dynamic random access memory (DRA
M) 16 memory cell array 18 row address buffer 20 row decoder 21 predecoder 22 word decoder and driver 24 column address buffer 26 column decoder 28 bit driver 30 input / output amplifier 32 input circuit 34 output circuit 36 control circuit 38 power supply voltage level detection circuit 39 , 49 power supply 40 booster circuit 42, 42a, 42b, 42c, 50, 52, 56, 6
0, 84, 86, 88, 92 N-channel MOS transistor (NMOS) 44 Voltage limiter 46, 48, 64, 66, 70, 74, 82 Inverter 54 MOS capacitor 58 P-channel MOS transistor (PMOS) 62 NOR gate 68, 72 , 80 NAND gate 76 Word decoder 78 Word driver 90 Memory cell 94 Capacitor (planar type, trench type, stack type, etc.)

Claims (1)

[Claims] 1. A means for detecting a power supply voltage level, a means for setting a drive voltage level of a predetermined circuit set to the power supply voltage level, and a circuit for setting the drive voltage level of the circuit when the power supply voltage level is below a predetermined value. And a means for boosting a drive voltage level.