JPH0612605B2 - Semiconductor integrated memory - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor integrated memory, and more particularly to a highly integrated and large-capacity semiconductor integrated random access memory (hereinafter, referred to as “semiconductor integrated memory”).
It is referred to as RAM. ) Concerning.

(Prior Art) Among conventional semiconductor integrated memories, RA using MIS transistors is the most highly integrated RAM.
M is a dynamic RA using a one-transistor cell
It is M. As a conventional example of the arrangement of the memory cell, word line, digit line and sense amplifier of the one-transistor type MISRAM, see, for example, Nikkei Electronics magazine, July 14, 1986, pages 189 to 208, “Groove type”. In a paper published under the title "Prototype of 4 Mbit Peripheral CMOS Dynamic RAM Using Transistor Cell", digit line layouts as shown in FIGS. 3 and 4 are shown. FIG. 3 shows a case of a so-called open digit line, in which two digit line pairs connected to the sense amplifier 3 extend in both directions, one pair on each side. A plurality of memory cells and one dummy cell are connected to each digit line. For example, if the word line W1 is selected, the memory cell 1 is connected to the digit line D1 and the dummy cell 9 is connected to the other digit line D0. Dummy cell 9
Is an intermediate voltage between the memory cell information "1" and "0". In this way, the sense amplifier 3 operates differentially to determine whether the signal from the cell is "1" or "0". On the other hand, FIG. 4 shows the case of a so-called folded digit line,
Digit lines forming a pair are adjacent to each other and extend in the same direction. When the word line W1 is selected, the actual cell 1 is connected to only one of the two digit lines, the dummy cell 9 is connected to the other digit line, and the sense amplifier 3 operates differentially.

These two methods differ in the arrangement of the memory cells, word lines and digit lines in the cell array as well as the position of the sense amplifier. In the open digit line, as shown in FIG. 5, cells are arranged at all intersections of word lines and digit lines. To place. Therefore, when a certain word line is selected, signals are simultaneously read out from cells connected to it to all digit lines. On the other hand, in the folded digit line,
As shown in FIG. 6, every other cell is arranged at the intersection of the word line and the digit line so that the dummy cells are connected to every other digit line.

The advantages and disadvantages of both methods are that the open digit line method has a smaller cell area, but one sense amplifier is required for each digit line, so the layout pitch of the sense amplifier is larger than the cell pitch, and if the peripheral circuit is included, memory is increased. While the array does not become smaller, the folded digit line method increases the cell area but makes a pair.
Since only one sense amplifier needs to be arranged for each digit line, the layout pitch of the sense amplifier can be set within the cell pitch of two, so that the memory array is smaller than the open digit line method. is there.

(Problems to be Solved by the Invention) In the case of realizing a megabit class MISRAM, it is necessary to arrange the memory array in the smallest size, and the sense amplifiers are arranged in the open digit line system in which the area of the cell is the smallest. As a result, the layout in which one sense amplifier is arranged with two digit lines reduces the area of the entire memory array including peripheral circuits.

As an example of such an arrangement, a digit line arrangement diagram as shown in FIG. 7 is shown in the cited document of the conventional example. In FIG. 7, a conventional memory cell on one digit line is divided into a plurality of sets and connected to segment digit lines D11, D12, D01, D02. Depending on which word line is selected, only the segment digit line connected to the selected cell is the segment selected word line 81 or
It is connected to the main digit lines D1 and D0 by 82 and inputted to the sense amplifiers 31 and 32 arranged at both ends. Here, a section selection transistor is connected in series to the main digits D1 and D0, and the section selection word line 91
Or by selecting one of 92, one main digit line is divided into two and the upper cell (11, 12, 13, 1) is divided.
4, ...) Signals are transmitted to the left sense amplifier 31, and signals of the lower cells (21, 22, 23, 24, ...) Are transmitted to the right sense amplifier. In other words, the function of the section selection word line results in the two folded digit lines facing each other.

In this conventional example, cells are always arranged at the intersections of word lines and digit lines, as in the open digit line system.
Moreover, the sense amplifiers are arranged so that one digit amplifier is composed of two digit lines, and the area of the entire memory array is reduced.

However, in the digit line arrangement shown in FIG. 7, a plurality of transistors are required to connect the plurality of segment digit lines and the main digit line, and further a plurality of transistors are required to divide the main digit line into a plurality of sections. Since an extra layout area is used for many of these transistors, there is a drawback that the area of the entire memory array is not reduced even if the cell size is reduced.

As is clear from the above description, the cells are always arranged at the intersections of the word lines and the digit lines in the open digit line system, and the sense amplifier is arranged so that the number of the two sense lines is one. There is a strong demand for a semiconductor integrated memory that does not require extra transistors and reduces the area of the entire memory array.

An object of the present invention is to provide a semiconductor integrated memory that satisfies the above conditions, reduces the layout pitch of word lines, digit lines, and sense amplifiers and reduces the chip area in a highly integrated and large capacity semiconductor integrated memory. To provide.

(Means for Solving the Problems) Means provided by the present invention for solving the above problems are: memory cells arranged in a matrix and a plurality of memory cells connecting select gates of these memory cells in a column direction. And at least a plurality of digit lines that connect the digit terminals of the memory cells in the row direction and are formed of a first wiring layer; the memory cells are provided at the intersections of the word lines and the digit lines. Arranged semiconductor integrated memory, wherein a digit line pair is formed for every two adjacent first and second digit lines which are arranged in parallel among the digit lines; Of the first and second digit line pairs, which are arranged adjacent to each other in the row direction, of the two digit line pairs, one end of the first digit line pair is opposed to both ends of the two digit line pairs. A first sense amplifier is arranged at the other end of the second digit line pair, and a second sense amplifier is arranged at the other end of the second digit line pair; the first sense amplifier is arranged at a first input terminal forming a pair, The first digit line of the second digit line pair is the first digit line.
Connected via a first wiring composed of a second wiring layer arranged in parallel with the digit line pair of the first digit line pair of the first digit line pair to the second input terminal of the pair. The digit line and a second wiring formed of a second wiring layer arranged in parallel with the first wiring and having a substantially equal length are connected to each other; and to the second sense amplifier. Is a third wiring layer in which a second digit line of the first digit line pair is arranged in parallel to the second digit line pair at a first input terminal forming a pair. Connected via a wire; paired to the second input terminal,
A fourth digit line of the second digit line pair, which is formed of a second wiring layer which is arranged in parallel with the second digit line and has a substantially equal length to the third wiring. It is characterized in that it is connected to wiring.

(Operation) In the semiconductor integrated memory according to the present invention, the cells are arranged in the open digit line system, and the cells are always arranged at the intersections of the word lines and the digit lines. Further, the first and second sense amplifiers are arranged opposite to both ends of two pairs of digit lines arranged adjacent to each other in the row direction, as in the folded digit line system. When a memory cell pair connected to one of the pairs of digit lines is selected, one of the cell signals outputs the first signal.
The other cell signal is separately input to the second sense amplifiers arranged facing each other.
A signal to be a pair to the sense amplifier is inputted as a differential signal from the other unselected digit line pair to each sense amplifier via the first and third wirings. Moreover, since the imbalance of the digit line capacitance caused by the first or third wiring is compensated by the second or fourth wiring, the input capacitances forming a pair to each sense amplifier are equal, and the sensitivity is high. Differential amplification can be realized. As a result, in the memory of the present invention, cells can be arranged at the highest density, one sense amplifier is arranged in the layout pitch of two digit lines, and an extra transistor for dividing the digit lines is required. Therefore, there is an advantage that the area of the entire memory array is reduced.

(Examples) Hereinafter, the present invention will be described using examples so that the present invention can be better understood.

(Embodiment 1) FIG. 1 is a layout diagram of sense amplifiers and digit lines of a MISRAM showing a first embodiment of the present invention. In the RAM of this embodiment, the memory cells 11, 12, 21, 22, ... Are word lines W1, W2, ... And digit lines D11, D12, D0.
The cells are always arranged at the intersection of 1 and D02, and the cells are arranged at the highest density as in the conventional open digit line. 2 with digit lines D11 and D01 and D12 and D02
A set of digit line pairs is constructed. Sense amplifiers 31 and 32
Are arranged facing each other at both ends of the digit line pair,
The digit line D11 is connected to the sense amplifier 31 as one input, and the digit line D12 is connected to the sense amplifier 31 as the other input via the first wiring 4, and the digit line D11 is connected to the sense amplifier 32.
02 is connected as one input, and the digit line D ₀₁ is connected as the other input through the third wiring 6. Therefore, for example, when the word line W1 which activates the memory cell connected to the left digit line pair in FIG. 1 is selected, the signal of the memory cell 11 is transmitted to the sense amplifier 31.
The signal of the memory cell 21 is transmitted to the sense amplifier 32. A pair of signals to the sense amplifier 31 is differentially input from the digit line D12 as an intermediate voltage between the memory cell information "1" and "0" by a dummy cell similar to the conventional example. The paired signals to the sense amplifier 32 are also differentially input from the digit line D02 in the same manner as above. When the right half digit line side word line W2 is selected, the signal of the memory cell 12 is transmitted to the sense amplifier 31, and the signal of the memory cell 22 is transmitted to the sense amplifier 32. The paired signals to the sense amplifiers 31 and 32 are differentially input from the digit lines D11 and D01, respectively.

In the embodiment shown in FIG. 1, the digit line D11 is connected to the second wiring 5 having a length substantially the same as that of the first wiring 4, and the digit line D02 has a length substantially the same as that of the third wiring 6. It is connected to the fourth wiring 7 that it has. Here, the digit lines D11, D12, D01, D02 drawn by thin lines
Is formed by the first wiring layer and the first to fourth wirings 4, 5, 6, 7 drawn with thick lines are formed by the second wiring layer, the pair of sense amplifiers 31, 32 is The input signal lines formed are both digit lines formed of the first wiring layer and wiring formed of the second wiring layer, and since their lengths are almost the same, the input signal line capacitances are also substantially the same. Therefore, in the RAM of the present embodiment, the word line is selected, the signals are read out from the pair of memory cells, and the signals are separately input to the sense amplifiers at both ends, while the pair of the two sense amplifiers is input. The differential input of the reference voltage from the unselected digit line pair to the input terminals that make up the input signal line capacitances forming the pair to the sense amplifier are almost equal to each other when performing the amplifying operation. Can be realized.

In the layout diagram of FIG. 1, when the lower wiring layer is used as the first wiring layer and the upper wiring layer is used as the second wiring layer, the wirings 4, 5, 6, 7 and the digit line are overlapped. Therefore, in the present embodiment, one sense amplifier can be arranged at the layout pitch of two digit lines or wirings. Moreover, the RAM of this embodiment
Has the advantage that the area of the cell array is smaller than that of the conventional example because no extra transistor (which was necessary in the conventional example of FIG. 7) for dividing and selecting the digit line is required.

As described above, in the RAM of this embodiment, the cell array of the memory can be arranged at the highest density, and one sense amplifier can be arranged for every two digit lines, so that the area of the entire memory array is also increased. Smaller, larger capacity
It is very useful for realizing a highly integrated semiconductor integrated memory.

(Embodiment 2) FIG. 2 is a layout diagram of sense amplifiers and digit lines of a MISRAM showing a second embodiment of the present invention. In the MISRAM of the present embodiment, the digit line D11 is connected to the sense amplifier 31 as one input and the digit D02 is connected to the sense amplifier 32 as the other input, and the digit line D12 is connected to the sense amplifier 32 as one input. , The digit line D01 is connected as the other input through the third wiring 6, and the digit line D11 and the line D12 are parallel to the first and third wirings 4 and 6 and have substantially the same length. The arrangement of the memory cells and sense amplifiers is the same as in the first embodiment of FIG. 1 except that the wirings 5 and 7 are respectively connected, and the same circuit blocks are designated by the same numbers and symbols. ing. The circuit operation is similar to that of the first embodiment,
Signals are read out from the selected memory cell pair,
The above signals are separately input to the sense amplifiers arranged at both ends of the two digit line pairs.

In this embodiment, the connection method of the first to fourth wirings and the digit lines is different from that of the first embodiment, but the emollient cell array can be arranged at the highest density, and the two digit lines are used. Since one sense amplifier can be provided, the area of the entire memory array is reduced.

Incidentally, the embodiment shown here is an example of the semiconductor integrated memory of the present invention, and the way of connecting the digit line made of the first wiring layer and the wiring made of the second wiring layer can be arbitrarily selected. The wiring may be arranged at any position within the layout pitch of the digit line pair. Further, it goes without saying that the wiring layers for the first to fourth wirings can be arbitrarily selected.

(Effects of the Invention) As described above, according to the present invention, the open digit line type cell arrangement, which has been difficult in the past, is used.
Only one sense amplifier is arranged at a layout pitch of two digit lines, and an extra transistor for dividing the digit lines is not required, so that a semiconductor integrated memory in which a memory array and a chip area are significantly reduced can be realized.

[Brief description of drawings]

1 and 2 are layout diagrams of sense amplifiers and digit lines of the MISRAM according to the first and second embodiments of the present invention, respectively. FIG. 3 is a conventional MISRAM open gate line type sense amplifier and digit line. FIG. 4 is a diagram showing a circuit and arrangement of a folded digit line type sense amplifier and a digit line in a conventional MISRAM, and FIG. 5 is an arrangement diagram of an open digit line type memory cell. FIG. 6 is a layout diagram of a folded digit line type memory cell, and FIG. 7 is a conventional MIS.
FIG. 3 is a diagram showing a circuit and an arrangement of a sense amplifier and a digit line in which an open digit line type cell arrangement is provided in a RAM, and one sense amplifier is arranged at two digit line layout pitches. The symbols in the figure are 1, 2, 11, 12, 13, 14, 21, 22, 23,
24 is a memory cell, 3, 31 and 32 are sense amplifiers 4 to
7 is the first to second wirings, 8 and 9 are dummy cells, 81,
82 is a segment selection word line, 91 and 92 are section selection word lines, and W1, W2, W3 and W4 are word lines,
DW1 and DW0 are dummy word lines, D1, D0 and D1
1, D12, D01 and D02 are digit lines, respectively.

Claims (1)

[Claims] 1. Memory cells arranged in a matrix,
At least a plurality of word lines connecting the select gates of these memory cells in a column orientation and a plurality of digit lines connecting the digit terminals of the memory cells in the row direction and comprising the first wiring layer are provided. A semiconductor integrated memory in which the memory cell is arranged at an intersection of the word line and the digit line: every two first and second digit lines which are arranged in parallel among the digit lines and which are adjacent to each other; A digit line pair is formed on each of the two pairs of the first and second digit line pairs, which are arranged adjacent to each other in the row direction, of the digit line pair. A first sense amplifier is arranged at one end of the first digit line pair, and a second sense amplifier is arranged at the other end of the second digit line pair. A first digit line of the second digit line pair is formed on a first input terminal forming a pair and is formed of a second wiring layer arranged in parallel to the first digit line pair. A second digit line of the first digit line pair, which is connected to the second input terminal forming a pair, in parallel with the first digit line;
And a second wiring composed of a second wiring layer arranged so as to have substantially the same length, and connected to the second sense amplifier, the first input terminal forming a pair, A second digit line of the first digit line pair is connected through a third wiring formed of a second wiring layer arranged in parallel with the second digit line pair; and forming a pair. A second wiring arranged with the input terminal 2 as being parallel to the second digit line of the second digit line pair and the third wiring and having substantially the same length. A semiconductor integrated memory, which is connected to a fourth wiring formed of a layer.