JPH06125464A - Picture processing method and device - Google Patents

Abstract

PURPOSE:To provide a picture processing method and device coding a color picture while keeping high quality with a high efficiency. CONSTITUTION:The device is provided with a color space converter 112 which divides color picture data into mXn sets (m, n are natural numbers) of picture blocks and converts the inputted picture block data into brightness data and chromaticity data, with an encoder 113 separating the brightness data into a DC component and an AC component in the picture block, quantizing them, and calculating an amplitude of the AC component of the brightness data in a picture element block, and an encoder 114 calculating the amplitude of the AC component of the chromaticity information, calculating a ratio of the amplitude of the AC component of the chromaticity information to the amplitude of the AC component of the brightness information and coding the result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an image processing method and apparatus,
For example, the present invention relates to an image processing method and apparatus for performing processing of encoding (compression) and decoding (decompression) of full-color image data.

[0002]

2. Description of the Related Art Conventionally, for example, Japanese Patent Application No. 63-141826 has been proposed as a device for separating full-color image data into lightness information and chromaticity information for each pixel block and encoding (compressing) them.

[0003]

In such a conventional example, when the chromaticity information is encoded, it is linearly encoded.

The amplitude ratio of the chromaticity information to the lightness information has the same tendency in the existing range and the frequency distribution regardless of the type of image information to be read.

If the biased information is linearly quantized as in the conventional case, the error due to the quantization of the information having a high frequency of appearance by the quantization and the error due to the quantization of the information having a low frequency are the same. There is a problem that you can not do.

[0006]

SUMMARY OF THE INVENTION Therefore, the present invention is to provide an image processing method and apparatus for efficiently encoding a color image while maintaining high quality.

In order to achieve this object, the image processing method of the present invention comprises the following steps. That is, a division process of dividing the color image data into m × n (m and n are natural numbers) image blocks, and a color space conversion process of converting the input color image data into lightness data and chromaticity data,
A quantization step of separating the brightness data in the image block into a DC component and an AC component, and quantizing, and a first calculation step of calculating the amplitude of the AC component of the brightness data in the pixel block, A second calculation step of calculating the amplitude of the AC component of the chromaticity data in the pixel block, and a ratio of the amplitude of the AC component of the luminosity data to the amplitude of the AC component of the chromaticity data are calculated. , A first encoding step for encoding, and a second encoding step for nonlinearly encoding the amplitude ratio of the AC component of the chromaticity data and the AC component of the brightness data.

The image processing apparatus of the present invention has the following structure.

Dividing means for dividing the color image data into image blocks of m × n (m and n are natural numbers); color space converting means for converting the input color image data into lightness data and chromaticity data; Quantizing means for separating and quantizing the brightness data in the image block into a direct current component and an alternating current component; first calculating means for calculating the amplitude of the alternating current component of the brightness data in the pixel block; Second calculating means for calculating the amplitude of the AC component of the chromaticity data in the pixel block, and the ratio of the amplitude of the AC component of the lightness data to the amplitude of the AC component of the chromaticity data, The first encoding means for encoding and the second encoding means for nonlinearly encoding the amplitude ratio of the AC component of the chromaticity data and the AC component of the lightness data are provided.

In addition to the first aspect of the present invention, another aspect of the present invention is an image processing which makes it possible to generate code data corresponding to the state of each minute area and to make the code data a single length. The present invention seeks to provide a method and apparatus.

In order to achieve the above object, the image processing method of the present invention includes the following steps. That is, a division process for dividing the color image data into m × n (m and n are natural numbers) image blocks, a determination process for determining the image attributes of the image blocks, and input color image data for the lightness data and the chromaticity data. A color space conversion step of converting into data, a first encoding step of encoding lightness data corresponding to the divided image block, and a second encoding step of encoding chromaticity data corresponding to the divided image block. An encoding process, and a data length control process for controlling the data length of each encoded data encoded in the first encoding process and the second encoding process based on the determination result of the determination process, Equipped with.

The image processing apparatus of the present invention has the following configuration.

Dividing means for dividing the color image data into image blocks of m × n (m and n are natural numbers), determining means for determining the image attribute of the image block, and input color image data as lightness data and color data. Color space conversion means for converting into chromaticity data, first encoding means for encoding lightness data corresponding to the divided image blocks, and second encoding means for chromaticity data corresponding to the divided image blocks. And the data length control means for controlling the data length of each of the encoded data encoded by the first encoding means and the second encoding means based on the determination result of the determining means. With.

[0014]

In the structure of the present invention, for example, the input image data is divided into n × m pixel blocks, and the brightness information corresponding to the divided pixel blocks is separated into a DC component and an AC component. , Quantize. Further, the amplitude of the AC component of the lightness component of the pixel block is calculated, and the amplitude of the AC component of the chromaticity data is calculated. Then, for the AC line segment of the chromaticity data, the amplitude of the AC component of the brightness data is calculated and encoded. Then, the AC components of the chromaticity data and the amplitude components of the AC component of the brightness data are non-linearly encoded.

[0015]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In addition, although an example in which the present invention is applied to a full-color copying apparatus will be described in the embodiment, the present invention is not limited to this.

[Explanation of Device Outline] FIG. 3 shows a sectional structure of the device in the embodiment. In the figure, 201 is a platen glass on which a document 202 to be read is placed. The original 202 is illuminated by the illumination 203, passes through the mirrors 204, 205, 206, and by the optical system 207.
An image is formed on the CCD 208. In addition, the motor 209
Thus, the mirror unit 210 including the mirror 204 and the illumination 203 is mechanically driven at the speed V, and the mirror 205,
The second mirror unit 211 including 206 has a speed of 1/2 V
The original 2 is driven with the optical path length kept constant.
The entire area of 02 can be scanned.

Reference numeral 212 denotes an image processing circuit section, which controls the entire apparatus and also a section which processes the read image information as an electric signal and outputs it as a print signal.

Reference numerals 213 to 216 denote semiconductor laser elements, which are driven by the print signals output from the image processing circuit section 212. Each laser beam emitted by each semiconductor laser element scans and exposes the surface of each photosensitive drum 225 to 228 by the polygon mirrors 217 to 220 rotating at a constant speed to form a latent image. 221 to 224 are black (B
k), yellow (Y), cyan (C), magenta (M)
Is a developing device for developing the latent image with the toner of (1), and the developed toner of each color is transferred to the paper, and full-color printout is performed.

Recordings of different sizes are set in the paper cassettes 229 to 231, and the papers fed from either the paper cassettes 229 to 231 or the manual feed tray 232 are supplied to the registration rollers 223. After a predetermined timing, the transfer belt 234 is adsorbed onto the transfer belt 234 (the transfer belt has a plurality of holes on the surface thereof so that the recording paper is adsorbed by the action of a fan (not shown). Is supplied to the photosensitive drum 225. At this time, the photosensitive drum 220 is already developed, and the magenta toner adhered to the surface of the photosensitive drum 220 is transferred onto the sheet. After that, the photosensitive drum 219
˜213, cyan, yellow, and black toners are superimposed and transferred. Then, the sheet after the final transfer of the black toner is separated from the conveyor belt by the action of a peeling claw (not shown), is fixed by the fixing device 235, and is discharged to the discharge tray 236.

[Description of Image Signal Flow] FIGS. 1 and 2 show the signal flow in the image processing circuit section 212.

Reference numerals 101, 102 and 103 denote red (R), green (G) and blue (B) CCD sensors, respectively. The signals output from the respective sensors are amplified by analog amplifiers 104 to 106. The amplified analog signals of the respective color components are A / D converters 107 to 109.
Is converted into digital data by. 110,111
Each of them is a delay memory, and corrects a physical space shift of the three CCD sensors 101, 102, 103.

151, 152, 153, 154, 15
Reference numerals 5 and 156 denote tristate gate circuits, the input and output of which are controlled by a CPU (not shown). The CPU basically controls the control signals OE1 to the gate circuits 151 to 156 according to the contents of the scaling process.
The logic level of the signal of OE6 is set to "0" or "1". Each gate outputs the signal supplied to the input terminal from the output terminal when the supplied control signal is at "0" level. Table 1 shows the relationship between the signals OE1 to OE6 and the scaling process.

[0023]

[Table 1] Reference numerals 157, 158, 159, and 160 denote scaling circuits, which scale the image signals in the main scanning direction (interpolation processing, thinning processing, etc.).

Reference numeral 112 denotes a color space converter, which is R, G, B.
The signal is converted into a lightness signal L ^* and chromaticity signals a ^* and b ^* . Here, the L ^* , a ^* , and b ^* signals are signals that represent chromaticity components defined as the L ^* a ^* b ^* space as an international standard in CIE, and the L ^* , a ^* , and b ^* signals are as follows. Calculated by the formula.

[0025]

[Equation 1] However, α _ij , X0, Y0, and Z0 are constants.

Here, X, Y and Z are signals which are calculated and generated by the R, G and B signals, and are given by the following equations.

[0027]

[Equation 2] However, β _ij is a constant.

Reference numeral 113 is an encoder for the lightness signal L _* ,
The input L ^* signal is encoded in units of 4 × 4 pixel blocks and is output as a code L-code signal. 11
Reference numeral 4 denotes a chromaticity signal encoder, which encodes the input a ^* and b ^* signals in units of 4 × 4 pixel blocks and outputs the code ab.
-Output as a code signal.

On the other hand, reference numeral 115 is a feature extraction circuit, which inputs a K1 'signal and a black pixel detection circuit 115-1 for generating a determination signal K1' signal for determining whether or not the pixel is a black pixel. A 4 × 4 area processing circuit 115-11 for determining whether or not the inside of the × 4 pixel block is a black pixel area,
And a determination signal K2 indicating whether or not the pixel is in the character area
'A character area detection circuit 115-2 for generating a signal, and a 4 × 4 area processing circuit 115-2 for inputting a K2' signal described above to determine whether or not a 4 × 4 pixel block is a character area. It consists of 21.

Reference numeral 116 denotes an image memory, which is an L-code signal which is a code of lightness information and ab which is a code of chromaticity information.
-Code signal and determination signal K that is the result of feature extraction
The 1 and K2 signals are stored.

Reference numerals 141, 142, 143, and 144 are density signal generating means for magenta (M), cyan (C), yellow (Y), and black (Bk), and have substantially the same configuration. Therefore, here, the density signal generating unit 141 for magenta will be described. The other density signal generation means 142 to 144 only differ in the target color.

Reference numeral 117 denotes a lightness information decoder, which uses the L-code signal read from the image memory 116 to obtain 4 bits.
Decode to a ^* 4 L ^* signal. Reference numeral 118 denotes a chromaticity information decoder, which is a read from the image memory 116.
The b-code signal is used to decode the 4 ^* 4 a ^* and b ^* signals.

Reference numeral 119 denotes a color space converter, which is a magenta M signal (4 × 4 magenta signal) which is a toner developing color based on the L ^* , a ^* , b ^* signals in the decoded 4 × 4 pixel block. To generate. The other color space converters 119 ′, 1
19 ″ and 119 ″ ′ generate a cyan C signal, a yellow Y signal, and a black Bk signal, respectively.

Reference numeral 120 denotes a density conversion means, which converts the density level of the magenta signal from the color space converter 119.
In the embodiment, it is constituted by a look-up table of ROM or RAM.

A spatial filter 121 corrects the spatial frequency of the output image.

Reference numeral 122 denotes a pixel correction means for correcting the decoded image data (correction in consideration of the sensitivity characteristic of the scanner, etc.), which is also constituted by a look-up table such as ROM or RAM.

[Explanation of Enlarging Processing] In the first mode of performing the enlarging processing, the scaling processing is performed before the encoding (compression) processing. Therefore, as shown in Table 1 above, OE1, OE
Logic level "0" for each of the three signals of 3 and OE6
Is set, and the logic level "1" is set to each of the three signals OE2, OE4, and OE5. Accordingly, among the tri-state gates, 151, 153,
Only 156 is valid and 152, 154, 155 are invalid.

As a result, the R, G and B input image signals synchronized by the delay elements 110 and 11 first pass through the tri-state gate 151 and the scaling processing circuits 157 and 15 respectively.
8, 159 enlarges in the main scanning direction. still,
The scaling processing of the image in the sub-scanning direction is performed by controlling the scanning speed of the document (moving speed of the mirror unit 210). This makes it possible to obtain a scaling result as shown in FIG. For example, if the document is scanned at half the scanning speed in the normal size processing, a doubled image can be obtained in the sub-scanning direction.

The scaling process itself is described in Japanese Patent Application No. 1-1.
Since it is proposed as No. 99344, the description here is omitted.

The enlarged R, G, and B image signals are sent to the color space converter 112 and the feature extraction circuit 115 via the tristate gate 153.

The image code L-code and ab-code signals coded through the encoders 113 and 114 and the characteristic signals K ₁ and K ₂ signals extracted by the characteristic extraction circuit 115 are sent to the memory 116. Retained.

The signals read from the memory are decoded (expanded) as density image signals by density information decoders for magenta (M), cyan (C), yellow (Y) and black (Bk), respectively. , Tristate gate 1
56, magenta (M), cyan (C),
It is sent to the yellow (Y) and black (Bk) laser drivers.

[Explanation of Reduction Processing] In the second mode for performing reduction processing, scaling processing in the main scanning direction is performed before and after the encoder (compression) processing. However, the reduction processing in the sub-scanning direction is performed by increasing the scanning speed for reading the original.

Then, as shown in Table 1, OE2 and OE
Logic level "0" for each of the three signals of 4 and OE5
And OE1, OE3, and OE6 are set to logic level "1", respectively. This allows
Of the tristate gates, 152, 154, 155
Only valid, 151, 153, 156 are invalid.

As a result, the R, G, and B input image signals synchronized by the delay elements 110 and 111 are first sent to the color space converter 112 and the feature extraction circuit 115 via the tristate gate 152.

The image code L-code and ab-code signals encoded via the encoders 113 and 114 and the characteristic signals K ₁ and K ₂ signals extracted by the characteristic extraction circuit 115 are sent to the memory 116. Retained.

The signals read from the memory are decoded (expanded) as density image signals by density information decoders for magenta (M), cyan (C), yellow (Y) and black (Bk), respectively. , Tristate gate 1
After 56, the scaling processing circuits 157, 158, 159, 1
Reduction processing is performed at 60. Then, the reduced magenta (M), cyan (C), yellow (Y), and black (Bk) laser drivers are sent. Since this reduction processing itself has already been proposed in Japanese Patent Application No. 1-199344, its details will be omitted.

[Explanation of Lightness Component Encoder 113] Next,
FIG. 13 shows a block configuration of the brightness information encoder 113 in the embodiment, and FIG. 34 shows a timing chart thereof. Then, FIG. 14 shows a conceptual diagram of the brightness information encoding.

Here, the encoding (compression) of the image data is
As shown in FIG. 26, a total of 16 pixels of 4 pixels in the main scanning × 4 lines in the sub-scanning are processed in one block unit. Here, XPHS is a 2-bit signal indicating the main scanning position and is counted up in synchronization with a pixel clock (not shown) such as 0, 1, 2, 3, 3, 0, 1. Also, Y
PHS is a 2-bit signal indicating the sub-scanning position, and also takes values 0, 1, 2, 3. These XPHS and YP
The HS signal is used to cut out a 4 × 4 pixel block in the circuit shown in FIG.

First, the concept of brightness information encoding will be described with reference to FIG. As shown by reference numeral 71101, the lightness information cut out into a 4 × 4 pixel block is represented by X _ij (however,
i, j = 1,2,3,4)
The 4 × 4 Hadamard transform shown in the equation (3) is applied, and the code 7
Y _ij (i, j = 1, 2, 3, 4) shown at 1102 is obtained. Hadamard transform is a kind of orthogonal transform, and is 4 × 4.
Data is expanded by a two-dimensional Walsh function, which is equivalent to converting a signal in the time domain or the spatial domain into the frequency domain or the spatial frequency domain by Fourier transform. That is, the matrix Y _ij (i, i, after Hadamard transformation)
j = 1,2,3,4) is the matrix of input signals X _ij (i, j
= 1, 2, 3, 4) is a signal corresponding to each component of the spatial frequency.

[0051]

[Equation 3]Here, as in the case of the two-dimensional Fourier transform, this
Output Y of Damar conversion _ij(I, j = 1,2,3,4)
In this case, the larger the value of i (that is, the row position),
The high frequency component in the sub-scanning direction is arranged, and the value of j
The larger the column position, the higher the height in the main scanning direction.
A spatial frequency component is placed, and especially when i = j = 1
If Y₁₁= (1/4) ΣXij, and the input data X
_ijDC component of (i, j = 1, 2, 3, 4), that is, average
A signal corresponding to the value (strictly speaking, a signal with a value four times the average value)
Is output.

In addition, generally read images are CC
It is said that there are few high spatial frequency components due to the reading resolution of the reading sensor such as D and the transmission characteristics of the optical system. Using this characteristic, the data in the code 71102, which is the signal Y _ij (i, j = 1, 2, 3, 4) after Hadamard transform, is scalar-quantized, and Zij
(I, j = 1, 2, 3, 4) is obtained.

Reference numeral 71105 denotes X _ij (i, j = 1, 2,
The number of bits of each element of (3, 4) is represented by Y _ij (i, j = 1, 2, 3, 4) indicated by reference numeral 71106 and reference numeral 71102.
, The number of bits of each element of Z _ij (i, j = 1, 2, 3, 4) indicated by reference numeral 71103 is indicated by reference numeral 71107. As shown in the drawing, Y ₁₁ , that is, Z ₁₁ of 8-bit quantization having the largest DC component is set, and each Y _ij is quantized with a smaller number of bits as the spatial frequency _becomes higher. Further, reference numeral 71
The 16 elements of Z _ij (i, j = 1, 2, 3, 4) of 103 are grouped into a DC component and four AC components, as indicated by reference numeral 71104. That is, as shown in Table 2, AV
Z ₁₁ is assigned to E as a direct current component, Z ₁₂ , Z ₁₃ and Z ₁₄ are assigned to L1 as a main scanning AC component in a group, and Z ₂₁ , Z ₃₁ , Z ₄₁ are assigned to L2 as a sub scanning AC component in a group. , M are grouped and assigned Z ₂₂ , Z ₂₃ , Z ₃₂ , and Z ₃₃ as middle-range AC components of the main scanning and sub-scanning, and Z is assigned to H as high-frequency components of main scanning and sub-scanning
₃₄ , Z ₃₄ , Z ₄₂ , Z ₄₃ , Z ₄₄ are grouped and assigned.

[0054]

[Table 2] Now, in FIG. 13, line memories 701, 702, and 703 delay image data by one line. Then, the held contents are shifted and output in synchronization with a predetermined clock. Reference numeral 704 denotes a Hadamard transform circuit, which performs the transform represented by the equation (3) described above. That is, as shown in FIG. 34, the input terminal X1 of the Hadamard conversion circuit 704 is synchronized with the CLK signal and the XPHS signal.
X11, X12, X13, X14 signals are sequentially input to the input terminal X2, X21, X22, X23, X24 signals are input to the input terminal X3.
X31, X32, X33, X34 signals to the input terminal X4
X41, X42, X43, and X44 signals are sequentially input to. The Hadamard-converted signal is delayed by 8 CLK signals, and output units Y1 to Y11, Y12, Y13, and Y14 are sequentially output, and similarly, output terminals Y2 to Y21, Y22, Y23,
Y24 is the output unit Y3 to Y31, Y32, Y33, Y34
Then, the output units Y4 to Y41, Y42, Y43, and Y44 are sequentially output. Reference numerals 705, 706, 707, and 708 are look-up tables (ROMs), which perform scalar quantization described in FIG. That is, the Hadamard-transformed output is quantized into the number of bits as indicated by reference numeral 71107 in FIG. Lookup tables 705, 706, 7
The output after the Hadamard conversion and the XPHS signal are input to the addresses of the respective ROMs 07 and 708. Since the scalar-quantized result according to each address is written inside, the output terminal outputs the scalar amount specified by the address. Reference numeral 709 is a circuit for performing grouping for vector quantization, and its detailed block configuration is as shown in FIGS. 15 and 16.

15 and 16, reference numeral 7120
1 to 71216 are flip-flops, and C
A delay synchronized with the LK signal is provided. Therefore, these flip-flops have a 4 × 4 size as shown by reference numeral 71103 in FIG.
Holds each data in the block of
104 and AVE, L1, L2 as shown in Table 2
Data grouped into M and H are extracted. 7
Reference numerals 1217 to 71221 denote selectors for selecting one of the input terminals A and B, respectively. When "0" is input to S, the value of the A input is output to the Y output and S is input to S. When "1" is input, B is output to Y output.
The input value is output. In addition, 71222 to 71226
Is a flip-flop which gives a delay synchronized with the CLK signal.

The XD0 signal is synchronized with the CLK signal and the XPHS signal as shown in FIG. 34, and the XPHS signal is "0".
Is a signal that becomes “0” only in the case of, and becomes “1” in other cases. As a result, for each 4 × 4 block, Table 2
The scalar quantization result of each group shown in FIG.
One pulse of the CLK signal is delayed by 222 to 71226, and output from the Q output of each flip-flop at the timing shown in FIG. Furthermore, 71227-71
231 is also a flip-flop, and the CLK4 signal (CL
The input data is held at the rising edge of the 1/4 frequency of the K signal), and AVE, L1, L are held at the timing shown in FIG.
2, M, and H signals are output.

Returning to FIG. 13 again. In the figure, 71
Reference numerals 0, 711, 712, and 713 are look-up tables (ROMs), which are L of the grouping circuit 709.
Signals output from 1, L2, M, and H are quantized by known vector quantization. The L1 group is 9 bits, the L2 group is 9 bits, the M group is 8 bits, and the H group is 8 bits, respectively. Of 8 bits are quantized and a total of 42 bits of signal are flip-flop 714
At the rising edge of the CLK4 signal at
It is output as an L-code at the timing shown in.

On the other hand, 715 in FIG. 13 is LGAIN.
It is a calculator, and the respective input terminals of A, B, C, D are connected to the respective input terminals X1, X2, X3 of the Hadamard conversion circuit 704.
L in 4 × 4 block units at the same timing as X4
^{* The} LGAIN signal, which is the amplitude (maximum value-minimum value) of the brightness signal L ^* in the 4x4 block when the signal is input, and the position when L ^* takes the maximum value (coordinates in the 4x4 pixel block ) Position (4 when LMX and L ^* take the minimum value)
Calculate and output LMN (coordinates in a × 4 pixel block).

17 and 18, the LGAIN calculator 71 is shown.
5 shows a block diagram of No. 5. In the figure, 71301 to 7
Reference numeral 1304 is a flip-flop, which inputs data CL
Hold at the rising edge of the K signal. Reference numeral 71305 denotes a search circuit for the maximum value and the minimum value in the sub-scanning direction.
It is as shown in 9.

Reference numerals 71401 and 71402 denote selectors, which select one of the data supplied to the input terminals A and B based on the signal level supplied to the selection terminal S. 71
Reference numeral 403 is a comparator, and 71404 is an inverter. If A> B, the output Y of the comparator 71403 becomes "1", the A signal is output from the Y output of the selector 71401, and the B signal is output from the Y output of the selector 71402.

On the other hand, if A ≦ B, the comparator 714
The output Y of 03 becomes "0", and the Y of the selector 71401
The B signal is output from the output, and the A signal is output from the Y output of the selector 71402. That is, as a result, the value of max (A, B) is output from the Y output of the comparator 71401, and the value of min (A, B) is output from the Y output of the comparator 71042.
The value of B) is output.

Similarly, selectors 71405, 714
06 is the supplied signal C (supplied to terminal A), D
At C (supplied to the terminal B), if C> D, the output Y of the comparator 71407 becomes "1", and the C signal from the Y output of the selector 71405 becomes the selector 7
A D signal is output from the Y output of 1406. On the other hand, C
If ≦ D, the output Y of the comparator 71407 becomes “0”, the D signal is output from the Y output of the selector 71405, and the C signal is output from the Y output of the selector 71406. Therefore, as a result, the value of max (C, D) is output from the Y output of the comparator 71405, and the comparator 7
From the Y output of 1404, the value of min (C, D) is output.

Further, max (A, B) is supplied to the input terminal A of the selector 71409, max (C, D) is supplied to the terminal B, and min is input to the input terminal A of the selector 71411.
(A, B) and B are supplied with min (C, D).
Then, in the comparator 71410, max (A, B)
And max (C, D) are compared. And if ma
When x (A, B)> max (C, D), the output of the comparator 71410 becomes “1”, and max (A, B).
Is output from the Y output of the selector 71409. When max (A, B) ≦ max (C, D), the output of the comparator 71410 becomes “0”,
The value of max (C, D) is output from the Y output of the selector 71409. Therefore, as a result, max (A, B, C,
The value of D) is data ma from the Y output of the selector 71409.
It is output as x. Furthermore, imx (0) and imx
In (1), a code indicating which of A, B, C and D has the maximum value is output as follows. That is, when A has the maximum value, imx (1) = 0 and imx (0) = 0,
When B has the maximum value, imx (1) = 0 and imx
When (0) = 1, C takes the maximum value, imx (1) = 1 and imx (0) = 0, when D takes the maximum value, imx
(1) = 1 and imx (0) = 1.

Similarly, by the selector 71415 and the comparator 71416, min which is the minimum value of A, B, C and D input from the selector 71415.
(A, B, C, D) will be output. And
The comparators 71416 and the selector 71417 output signals imn (0) and imn (1) indicating which of the inputted A, B, C and D is the smallest. The relationship between these imn (0) and min (1) and the pixel position having the minimum value is as follows.

When A has the minimum value, imn (1) = 0 and imx (0) = 0, and when B has the minimum value, imn (1) = 0 and imx (0) = 0.
(1) = 0 and imx (0) = 1, when C has a minimum value, imn (1) = 1 and imx (0) = 0, when D has a minimum value, imn (1) = 1 and imx (0) = 1.

With the above configuration, the processing of the maximum / minimum value search circuit in the sub-scanning direction in FIGS. 17 and 18 is realized.

Returning to FIGS. 17 and 18, 71306-
Reference numeral 71313 denotes a flip-flop, which outputs max, min, imx, imn, which are output signals of the maximum / minimum value search circuit 71305 in the sub-scanning direction, respectively to CLK.
The signal is delayed by one pulse. In other words, these flip-flops 71306 to 71313 have 4
The maximum and minimum values for four vertical columns in the × 4 block, and the existing positions of these maximum and minimum values are held.

The data held here is supplied to the main scanning direction maximum value searching circuit 71314 and the main scanning direction minimum value searching circuit 71315, respectively, and finally the maximum value max and its existing value in the 4 × 4 block. imx, the minimum value mi
n and its existing position inm will be detected.

FIG. 20 shows details of the maximum value search circuit 71314 in the main scanning direction. Basically, it is the same as the maximum / minimum value search circuit 71305 in the sub-scanning direction described above, but this maximum value search circuit 71314 in the main-scanning direction detects the maximum value of the four input max data. Then, a process of outputting 4-bit position data in the main scanning direction is performed.

In the figure, the signal or data A is 4
Indicates the maximum value of the first sub-scan row of × 4 blocks, and B is the second
The sub-scanning row, C shows the maximum value of the third sub-scanning row, and D shows the maximum value of the fourth sub-scanning row. Further, iA is a signal or data indicating the location of the maximum value in the first sub-scanning column, and will be referred to as iB, i below.
It is data indicating the location of the maximum value of the second to fourth sub-scanning columns in the order of C and iD.

The selector 71501, the comparator 71502, and the inverter 71503 select the larger max (A, B) of the input A and B, and the selector 715.
09 and the comparator 71510, respectively. Also, along with this, from the selector 71504,
One of iA and iB corresponding to the data selected by max (A, B) is selected and supplied to the input terminal A of the selector 71511. For example, in the selector 71501, when the data A (the maximum value of the first sub-scanning column) is selected, the data iA indicating the location of the maximum value is selected.

On the other hand, selectors 71505, 71508,
The comparator 71506 and the inverter 71507 perform similar processing. That is, the third from the selector 1705,
The maximum value max (C, D) of the fourth sub-scanning column is selected and output, and one of iC and iD corresponding to the selected one of the inputs C and D is selected and output from the selector 71508.

Now, the selector 71509 and the comparator 71
The max (A, B) and max (C, D) are supplied to 510. The comparator 71510 compares max (A, B) with max (C, D), and the selector 71509 selects and outputs the larger one based on the comparison result (inverted by the inverter 71512).

As is apparent from the above description, the comparator 71510 eventually outputs a signal indicating which of the input data (A, B) and the input data (C, D) is selected. Will be. A 1-bit signal indicating which one of the first and second sub-scanning columns is selected is input to the input terminal A of the selector 71513, and one of the third and fourth sub-scanning columns is selected to the input terminal B. A 1-bit signal indicating whether it is high is supplied. Therefore, if it is known which of the input terminals A and B of the selector 71513 has been selected, the first to fourth
It becomes clear which of the sub-scanning directions is selected. This becomes clear by examining the output signal of the comparator 71510.

Therefore, a signal indicating which sub-scan column has the maximum value by the output signal of the comparator 71510 (correctly, the output signal of the inverter 71512) and the signal from the selector 71513 selected based on the output signal. imx (1) and imx (0) are generated. Further, since the actual position of the maximum value in the sub-scanning direction is output from the selector 71511, the output from this selector 71511 is i
When used together as mx (2) and imx (3), 4x
The location of the maximum value in the block of 4 can be specified.

The relationship between the data output from the selector 71509 and imx (0) to imx (3) indicating the location of the data is as follows.

When A has the maximum value, imx (3 to 2)
= IA & imx (1) = 0 & imx (0) = 0 When B has the maximum value, imx (3 to 2) = iB &
imx (1) = 0 & imx (0) = 1 When C takes the maximum value, imx (3-2) = iC &
imx (1) = 1 & imx (0) = 0 When D takes a maximum value, imx (3-2) = iD &
imx (1) = 1 & imx (0) = 1 However, as described above, imx (0) to (3) are positions (coordinates) where the L ^* signal has the maximum value in the pixel block of 4 × 4.
(The lower 2 bits indicate the position in the main scanning direction, and the upper 2 bits indicate the position in the sub-scanning direction).

On the other hand, the details of the minimum value search circuit 71315 in the main scanning direction in FIGS. 17 and 18 are as shown in FIG. The basic idea is the maximum value search circuit 7
Same as 1314, but described below.

In the figure, the signal or data A is 4
Shows the minimum value of the first sub-scan row of × 4 blocks, and B is the second
The sub-scanning row, C the third sub-scanning row, and D the minimum value of the fourth sub-scanning row. Further, iA is a signal or data indicating the location of the minimum value in the first sub-scanning column, and hereinafter, iB, i
It is data indicating the position of the minimum value of the second to fourth sub-scanning columns in the order of C and iD.

The smaller one of A and B input by selector 71601 and comparator 71602 min (A, B)
Is selected, the selector 71607 and the comparator 71608 are selected.
It is supplied to each input terminal A. Along with this, either iA or iB corresponding to the data selected in min (A, B) is selected from the selector 71503 and supplied to the input terminal A of the selector 71609. For example, when the data A (minimum value of the first sub-scanning column) is selected by the selector 71601, the data iA indicating the location of the minimum value is selected.

On the other hand, the selectors 71604 and 71606 and the comparator 71605 perform similar processing. That is,
The selector 71604 selectively outputs the minimum values min (C, D) of the third and fourth sub-scanning columns, and the selector 71606
From iC, which corresponds to the selected one of inputs C and D,
One of the iDs is selected and output.

Now, the selector 71607 and the comparator 71
Min (A, B) and min (C, D) are supplied to 608. The comparator 71608 compares min (A, B) with min (C, D), and based on the comparison result,
The selector 71607 selects and outputs the smaller one.

At this time, the comparator 71608 finally outputs the input data (A, B) and the input data (C,
A signal indicating which one of D) is selected is output. A 1-bit signal indicating which of the first and second sub-scanning columns is selected is input to the input terminal A of the selector 71610, and which of the third and fourth sub-scanning columns is selected to the input terminal B. A 1-bit signal indicating whether it is high is supplied.
Therefore, if it is known which of the input terminals A and B of the selector 71610 has been selected, it becomes clear which of the first to fourth sub-scanning directions has been selected. This is the comparator 716
It is found by examining the output signal of 08.

Therefore, the output signal of the comparator 71608,
The signals imn (1) and imn (0) indicating which sub-scanning column has the minimum value are generated by the signal from the selector 71610 selected based on this. In addition, the actual position of the minimum value in the sub-scanning direction is the selector 716.
09. Since the output from the selector 71609 is also used as imn (2) and imn (3), the location of the minimum value in the 4 × 4 block can be specified.

The relationship between the data output from the selector 71607 and imn (0) to (3) indicating the location of the data is as follows.

When A has the maximum value, imn (3-2)
= IA & imn (1) = 0 & imn (0) = 0 When B has the maximum value, imn (3 to 2) = iB &
imn (1) = 0 & imn (0) = 1 When C has the maximum value, imx (3-2) = iC &
imn (1) = 1 & imn (0) = 0 When D has the maximum value, imx (3-2) = iD &
imn (1) = 1 & imn (0) = 1 However, as described above, imn (0) to (3) indicate positions (coordinates) where the L ^* signal takes the minimum value in the 4 × 4 pixel block. It becomes a signal (the lower 2 bits indicate the position in the main scanning direction and the upper 2 bits indicate the position in the sub scanning direction).

Returning to FIGS. 17 and 18, the maximum value search circuit 71314 indicates that the maximum value ma in the 4 × 4 block is ma.
x and its existing position imx are output, and the minimum value search circuit 7
From 1315, the L ^* minimum value min in the 4 × 4 block and its existing position imn are output.

The subtractor 71316 inputs the maximum value max and the minimum value min of the 4 × 4 L ^* signal, and outputs the maximum value max.
A value obtained by subtracting the minimum value min is output. 71317〜
Reference numeral 71319 is a selector, and 71320 to 71322 are flip-flops. Further, the XD1 signal is synchronized with the XPHS signal and the CLK signal as shown in FIG.
The signal has a logical level “0” only when the value of the XPHS signal (takes a value of 0 to 3) is “1”, and is a logical level “1” in other cases. LGAIN signal which is the maximum value-minimum value of the L ^* signal in the pixel block, LMX signal which shows the position (coordinates) in the 4x4 block when the L ^* signal has the maximum value, and L ^* signal has the minimum value LMN indicating the position (coordinates) in the 4 × 4 block in the case
The signal is output at the timing shown in FIG.

Returning to FIG. 13, the LGAIN signal obtained by the above processing is supplied to the input terminal A of the comparator 716, and the signal (certain constant) from the CPU (not shown) is input to the input terminal B thereof. It

If A> B in the comparator 716, 71
The output LFLG from 6 becomes "1", and if A <B, it becomes "0". This LFLG signal is input as a determination signal of a quantization circuit (reference numeral 7208 in FIG. 22) described later inside the chromaticity information encoder 114 in FIG.

[Explanation of Chromaticity Component Encoder 114] FIG.
FIG. 35 shows a block diagram of the chromaticity information encoder 114, and FIG. 35 shows its timing chart.

In FIG. 22, 7201, 7202, 7
Reference numeral 203 is a line memory that gives a delay of one line,
The chromaticity information is for processing the a ^* signal in a 4 × 4 pixel block. Reference numeral 7204 is a four-quantization circuit for the a ^* signal. Similarly, 7205, 7206, 7207
Is a line memory that gives a delay of one line and is for processing the b ^* signal in a 4 × 4 pixel block of the chromaticity information. Reference numeral 7208 denotes a circuit similar to 7204, which is a b ^* signal quantization circuit. The output signals a _mean , a _{gain of} the quantizers 7204 and 7208, respectively,
b _mean and b _gain are integrated and output as an ab-code. Where a _mean signal is the direct current component of a ^* , a _gain
Signal is a ^* AC component, b _mean signal is b ^* DC component, b
_gain represents the AC component of b ^* .

23, 24 and 25, the a ^* quantizer 7 is shown.
A block diagram of 204 is shown. However, a ^* quantizer 720
Since 4 and b ^* quantizer 7208 have the same configuration,
The description of the b * quantizer 7208 is omitted.

In FIG. 23 and FIG. 24, 72101-
72124 is a flip-flop, CLK
A delay synchronized with the rising edge of the signal is given to synchronize with the brightness information encoder. 72115 and 7211
Reference numeral 6 denotes a 4-input 1-output selector which outputs the A input value as the Y output when the s input (2 bits) value is "0" and outputs the B input when the s input value is "1". Output. When the value of s input is "2", the value of C input is output to the Y output terminal, and when the value of s input is "3", the value of D input is output from the Y output terminal.

Here, the upper 2 bits of the LMX signal are input to the s input of the selector 72115, and the selector 7
The upper 2 bits of the LMN signal are input to the s input of 2116.

Further, 72117 to 72128 are flip-flops, which give a delay synchronized with the rising edge of the CLK signal. 72129 and 72130 are 72
It is a 4-input / 1-output selector similar to 115 and 72116. The lower 2 bits of the synchronized LMX signal are input to the s input of the selector 72129.
The lower 2 bits of the synchronized LMN signal are input to the s input of 30.

As a result, L ^* within a 4 × 4 pixel block
Signal a ^* value at the position (coordinates) taking the maximum value (b ^* b ^* values in the case of a quantizer 7208) is output as the MX,
A ^* value (b ^{* in} the case of the b ^* quantizer 7208) at the position (coordinates) where the L ^* signal takes the minimum value in the 4 × 4 pixel block.
Value) is output as MN.

On the other hand, 72131 is an average value calculator,
Average of 4 inputs of A, B, C, D (A + B + C + D) /
4 is output. Reference numerals 72132 to 72135 denote flip-flops, which give a delay synchronized with the rising edge of the CLK signal. 72136 is an average value calculator similar to 72131, and outputs the average value (A + B + C + D) / 4 of four inputs of A, B, C, and D.

As a result, a within a 4 × 4 pixel block
^* Average of the values (b ^* b ^* values in the case of a quantizer 7208) is outputted as the ME.

Further, 72137 to 72140 are flip-flops, which give a delay synchronized with the rising edge of the CLK signal, and apply the LGAIN signal to MX, MN, and M.
It is output as an LG signal in synchronization with each signal of E.

Further, turning to FIG. 25, the signals of MX, MN, ME and LG obtained by the above circuit configuration are synchronized by the rising edge of the CLK signal in the flip-flops 72141 to 72144. The subtractor 72145 calculates M from the value of MX.
By reducing the value of N, within a 4 × 4 pixel block, L
^* Signal to calculate a difference value between a ^* signal at the position where the position and L ^* signal takes the maximum value is a minimum value (b ^* b ^* signal when the quantizer 7208). Furthermore, 72146, 7215
Reference numerals 0 and 72151 are flip-flops, and the subtractor 72
The difference value calculated in 145 is the flip-flop 721.
46 of lookup table ROM 72417 A
Input to addresses 15 to A8. The LG signal is
It is inputted to the addresses A7 to A0 of the look-up table ROM 72417 via the flip-flops 72144 and 72151, and the look-up table ROM 7214 is inputted.
The LFLG signal is input to the address A16 of 7.

This look-up table ROM 7214
The 7, the AC component of a ^* signal at 4 × 4 pixel block (b ^* b ^* signal when the quantizer 7208) of the amplitude,
L ^* Ratio of AC component amplitude to signal (MX-N) / L
The value of G is quantized into 4 bits when the LFLG signal is "1", and the value is quantized into 2 bits when it is "0" is written in advance and output as data.

Similarly, the lookup table ROM 72
The 158, the quantization value of the mean value ME of the a ^* signal 4 × 4 pixel block (b ^* b ^* signal when the quantizer 7208), the 6 bits when the LFLG signal is "1" If it is "0", the 8-bit data is written in advance and is output as data.

Look-up table ROM 72147,
The data of 72158 follows the frequency distribution of the image data obtained empirically. For example, when the LFLG signal is "1", the amplitude ratio data of the look-up table ROM 72158 is written as non-linear data having the characteristics shown in FIG.

Reference numerals 72148 and 72152 are 2-input and 1-output selectors, and 72149 and 72153 to 72157 are flip-flops. As a result, the gain signal and the mean signal are output at the timings shown in FIG.

[Description of Timing Chart of Device Operation]
FIG. 31 shows a device timing chart in this embodiment. The START signal is a signal indicating the start of the document reading operation in this embodiment. The WPE signal is a section in which the image scanner reads a document and performs coding processing and memory writing. The ITOP signal is a signal indicating the start of printing operation. The MPE signal is a section signal for driving the magenta semiconductor laser 216 in FIG. Similarly, the CPE signal is a cyan semiconductor laser 215.
, A YPE signal is a section signal for driving the yellow semiconductor laser 214, and a BPE signal is a section signal for driving the black semiconductor laser 213.

As shown in FIG. 31, the CPE signal, the YPE signal, and the BPE signal are t1 and t with respect to the MPE signal, respectively.
It is delayed by 2, t3, which is d1, d2 in FIG.
, D3, t1 = d1 / v, t2 = d2 / v, t3
= D3 / v, (v is the sheet feed speed).

The HSYNC signal is the main scanning synchronization signal, CLK
The signal is a pixel synchronization signal. The YPHS signal is the count value of the 2-bit sub-scanning counter, and the XPHS signal is the count value of the 2-bit main-scanning counter. As shown in FIG. 30, a circuit including an inverter 1001, 2-bit counters 1002 and 1003. Is generated in.

The BLK signal is a synchronizing signal in units of 4 × 4 pixel blocks, and is 4 × at the timing indicated by BDATA.
Processing is performed in units of 4 blocks.

[Explanation of Area Processing] FIG. 29 shows a block diagram of a 4 × 4 area processing circuit (reference numerals 115-11 and 115-21 in FIGS. 1 and 2). In the figure, CLK is a pixel synchronizing signal, and HSYNC is a main scanning synchronizing signal. 90
Reference numerals 1, 902 and 903 denote line memories that give a delay of 1 line, and signals X1, X2, and X3 are 1 line, 2 lines, and 1 line in the sub-scanning direction with respect to the input signal X, respectively.
A signal delayed by three lines is shown. An adder 904 counts the number of "1" s among X, X1, X2, and X3 corresponding to the four pixels of the binary signal X in the sub-scanning direction.

Further, 904 to 908 are flip-flops, and 909 is these flip-flops 904 to 9
Sum of signals latched by 08, ie 4 ×
The total number of "1" in the 4 blocks is calculated.

Reference numeral 910 denotes a 2-input / 1-output selector, and 911.
Is a NOR gate, 912 is a flip-flop, and X is
BLK generated by PHS (0) and XPHS (1)
The number of counted pixels C1 for which X = “1” is calculated in units of 4 × 4 blocks in synchronization with the signal, and the register 91
C1 is compared with the comparison value C2 preset to 3.
The output Y becomes "1" only when <C2, and otherwise becomes "0" and is output at the timing shown by BDATA in FIG.

Here, what is characteristic is that the image code L-code and ab-code signals obtained by the encoding and the characteristic signals K1 and K extracted by the characteristic extraction circuit.
2 corresponds one-to-one with the 4 × 4 block unit shown in FIG.

That is, the image code and the characteristic signal are extracted for each 4 × 4 pixel block unit, stored in the same address of the memory or at the address calculated from the same address, and read out correspondingly even in the case of reading. be able to.

That is, by storing the image information and the characteristic (attribute) information in association with each other at the same address of the memory or at an address calculated from the same address, for example, the writing / reading control circuit of the memory can be shared. The simplification is possible, and the editing processing such as scaling / rotation on the memory can be performed by a simple processing, and the system can be optimized.

FIG. 32 shows an example of specific area processing for character pixel detection. For example, with respect to the document shown in 1201, for the portion shown in 1201-1, K1 '= 1 in the pixel indicated by "○" as the determination result of whether each pixel is a character pixel or not, and other than that. It is assumed that K1 '= 0 is determined in the pixel.

In the area processing circuit 115-11, as shown in FIG.
By carrying out the processing shown in, for example, by setting C2 = 4, a block corresponding to 4 × 4 blocks can be obtained.
A signal K1 with reduced noise can be obtained as shown in FIG.

Similarly, the determination result K of the black pixel detection circuit
A similar circuit is also applied to 2 '(115-2 in FIGS. 1 and 2).
By processing in 1), the signal K2 corresponding to 4 × 4 blocks can be obtained.

[Explanation of Lightness Component Decoder 117] Next, the lightness component decoder 117 in the embodiment will be explained. However, other brightness component decoders 117 ′, 11
The same applies to 7 ″ and 117 ″ ′.

FIG. 36 shows a block diagram of the lightness component decoder 117.

For the decoding of the brightness information, the L-code read from the image memory 116 is subjected to inverse Hadamard transform of the decoded data to decode the L ^* signal. The inverse Hadamard transform is an inverse transform of the Hadamard transform shown by the equation (3), and is defined by the following equation (4).

[0122]

[Equation 4] On the other hand, the Hadamard transform and the inverse Hadamard transform are linear operations, and when the Hadamard transform or the inverse Hadamard transform of the matrix X is expressed as H (X), the following equation (5) generally holds.

[0123]

H (X ₁ + X ₂ + ... + X _n ) = H (X ₁ ) + H (X ₂ ) + ... + H (X _n ). ． ． (5) Utilizing this property, the inverse Hadamard transform is decomposed into each frequency band defined by the brightness information encoder and performed in parallel.

Here, the data matrix decoded by the L1 code is Y _L1 , the data matrix decoded by the L2 code is Y _L2 , and the data matrix decoded by the M code is Y _M , H. When the data matrix decoded by the code is Y _H , the following equation (6)
Is established.

[0125]

[Equation 6] H (Y _L1 + Y _L2 + Y _M + Y _H ) = H (Y _L1 ) + H (Y _L2 ) + H (Y _M ) + H (Y _H ). ． ． (6) In FIG. 36, reference numerals 1601 to 1604 are lookup table ROMs. Lookup table 16
The code of L1 is in the lower order of the address of 01, the code of L2 is in the lookup table 1602, the code of M is in 1603,
The code of H is input to 1604. Each look-up table holds in each ROM pre-calculated encoding processing and inverse Hadamard transform processing.

On the other hand, XPHS and Y are stored in the upper 4 bits of each address of each lookup table ROM.
Data is written in each ROM so that PHS is input and the value after the inverse Hadamard transform is output at the position (coordinate) in each 4 × 4 pixel block.

The adder 1605 is a part for performing addition corresponding to the above equation (6), and each frequency component (L1, L2,
M, H) is a part for adding the results of the inverse Hadamard transform. As a result of the addition, an AC component of the L ^* signal in the 4 × 4 pixel block is obtained, and is output as an L ^* AC component LAC via the flip-flop 1606.

If decoding is performed collectively without using this method, a look-up of a total of 36-bit address space (64 gigabytes) of 34-bit code and 4-bit coordinate position (XPHS, YPHS) is performed. Up-tables are required, which is unrealistic even if it can be realized logically. By using this method, several ROMs having an address space of at most 13 bits (8 kilobytes) may be prepared, and the configuration is simplified. Further, it is easy to deal with the case where the code length is changed.

Reference numeral 1607 denotes an adder, which is 4 × of the L ^* signal.
The L ^* signal after decoding is obtained by adding the average value AVE within four blocks, and is output in synchronization with the rising edge of the CLK signal by the flip-flop 1608.

[Explanation of Chromaticity Component Decoder 118] FIG.
A block diagram of the lightness component decoder 118 (see FIGS. 1 and 2) is shown in FIG. However, other brightness component decoders 11
The same applies to 8 ′, 118 ″, and 118 ′ ″.

First, the ab-code signal read out from the image memory 116 is transferred to C in the flip-flop 1701.
It is synchronized at the rising edge of the LK signal and is decomposed into a-code and b-code, as shown in FIG.
Furthermore, it is decomposed into again, amean, bgain, and bmean.
Reference numeral 1702 denotes a multiplier, which is a in the 4 × 4 pixel block.
^The again signal, which is the ratio of the L ^* signal amplitude to the ^* signal amplitude, is multiplied by the AC component of the lightness information L ^* . Adder 1704
In decoding the a ^* signal by adding the amean signal is a DC component of the output signal and a ^* signal from the multiplier 1702, the synchronization at the rising edge of the CLK signal in the flip-flop 1706 is taken to the output.

Similarly, in the multiplier 1703, 4 × 4
The bgain signal, which is the ratio of the amplitude of the L ^* signal to the amplitude of the b ^* signal in the pixel block, is multiplied by the AC component of the brightness information L ^* . Then, the result and bmea which is the DC component of the b ^* signal
The n signal is added by the adder 1705 to decode the b ^* signal. The decoded b ^* signal is flip-flop 1707
Is synchronized with the rising edge of the CLK signal and output.

[Color Space Converter 119 (119 ', 11
9 ″, 119 ″ ′)] FIG. 11 shows a block configuration of the color space converter 119. However, other color space converters 11
The same applies to 9 ′, 119 ″, and 119 ′ ″.

Reference numeral 501 designates L ^* , a ^* , b ^* signals as R, G, B signals.
It is a means for converting into a signal, and is converted by the following equation.

[0135]

[Equation 7] However,

[Equation 8]

[Equation 9] [Α _ij '] (i, j = 1,2,3) is [α _ij ] (i, j =
Inverse [βij '] (i of 1,2,3), j = 1,2,3) is, (2) [β _ij] in the formula (i, j =
Inverse matrices 502, 503, and 504 of 1,2,3) are brightness / density converters, respectively, and are converted by the following equation (10).

[0136]

[Equation 10] M ₁ = −log ₁₀ G C ₁ = −log ₁₀ R Y ₁ = −log ₁₀ B (10) 503 is a black extraction circuit,

[Equation 11] Bk ₁ = min (M ₁ , C ₁ , Y ₁ ) ... The black signal Bk ₁ is generated as in (11). Reference numerals 504 to 507 denote multipliers, which multiply the signals of C1, M1, Y1, and Bk1 by predetermined coefficients a1, a2, a3, and a4, and then add them in an adder 508 to obtain the following expression (12). The sum product operation shown is performed.

[0137]

(Output C, M, Y, or Bk) = a ₁ M ₁ + a ₂ C ₁ + a ₃ Y ₁ + a ₄ Bk ₄ (12) 509 to 513 are registers, and the coefficient a ₁₁ , _{a 21, a 31, a 41} , 0 is set. However,
These respective coefficients are the color space converters 119 ′, 11 for the respective color components.
It differs for every 9 "and 119"'. Specifically, it is as shown in FIG. 12, and its coefficient in the color space converter 119 'is a1.
2, a22, a32, in A42,0, 'and that of a13, a23, a33, a43,0, color space transformer 119' color space converter 119 'and that of''a14, a24, a34, a44, a 14 'Is set.

Reference numerals 531 to 533 are gate circuits, and 530 is 2
The input / output selector circuit 520 is a NAND gate circuit, and as a result, the logical product of the black pixel determination signal K1 and the character area determination signal K2 is used to determine whether or not the pixel is in the black character area. As shown in 12, a1, a
The values of 2, a3, and a4 are selected, and if it is not a black character area, the processing of the following equation (13) is performed, and if it is a black character area, the processing of equation (14) is performed.

[0139]

[Equation 13]

[Equation 14] That is, in the black character area, black (B
k) By outputting in a single color, it is possible to obtain an output without color shift. On the other hand, in areas other than the black character area, four colors of M, C, Y, and Bk are output as shown in the equation (13), but R and G read by the CCD sensor by the calculation of the equation (13). , M1, C1, Y1, Bk1 based on the B signal
The signals are M, C, Y based on the spectral distribution characteristics of the toner,
The Bk signal is corrected and output.

[Explanation of Spatial Filter] FIG. 27 shows a block configuration of the spatial filter 121. However, the same applies to the other spatial filters 121 ′, 121 ″, 121 ′ ″.

In the figure, reference numerals 801 and 802 denote line memories for giving a delay of one line, and reference numerals 803 to 809 denote flip-flops giving a delay of one pixel. 810,81
1 is an adder, and 812, 813 and 814 are multipliers, respectively, which are multiplied by coefficients b1, b0 and b2, and adder 81
The sum product operation is performed by 5.

On the other hand, 816 to 821 are registers, respectively, and these are b11, b12, b01, b02, b2 in advance.
The selectors 822 and 8 hold the values 1 and b22.
23 and 824 select one of the two input to themselves according to the character determination signal K2 and output it as b1, b0 and b2.

In FIG. 28, the character determination signals K2 and b0, b1,
The relationship with the value of b2 is shown.

For example, b01, = 4/8, b11 = 1/8,
b21 = 1/8, b02 = 12/8, b12 = -1 / 8, b22
= -1 / 8, the registers 816, 817, 8
When set to 18, 819, 820, 821, as shown in FIG. 28, a smoothing filter can be formed in K2 = 0, that is, in a non-character portion, and noise of high frequency components in the image can be removed. On the other hand, in the case of K2 = 1, that is, in the character portion, edge emphasis can be formed to correct the sharpness of the character portion.

[Pixel Correction Means] FIGS. 5 and 6 are block diagrams of the pixel correction means. In the figure, CLK is a pixel synchronizing signal, and HSYNC is a horizontal synchronizing signal. In the figure, 401 and 402 are line memories that give a delay of one line, and 403 to 411 are flip-flops.
Each gives a delay of one pixel. As a result, as shown in FIG. 10, peripheral pixels X11, X12, X13, X21, X23, X31, X32, and X in eight neighborhoods centering on the target pixel X22.
Outputs 33.

Reference numerals 411 to 414 denote pixel edge detection circuits, which output a value of | A-2B + C | / 2 for three inputs A, B and C, as shown in FIG. All of the target pixel X22 are input to the B inputs of the four pixel edge detection circuits.
Has been entered.

X12 and X32 are input to the A and C inputs of the edge detection circuit 411, respectively, and the result is | X
12-2X22 + X32 | / 2 is output, which is shown in FIG.
It becomes the absolute value of the secondary differential amount in the sub-scanning direction shown in 0,
The edge strength in the sub-scanning direction shown in FIG. 10 is output.

X11 and X33 are input to the A input and C input of the edge detection circuit 412, respectively, and the result is | X
11-2X22 + X33 | / 2 is output, which is shown in FIG.
It becomes the absolute value of the second derivative amount in the diagonally downward right direction indicated by 0, and the strength of the edge in the diagonally downward right direction shown in FIG. 10 is output.

X21 and X23 are input to the A and C inputs of the edge detection circuit 413, respectively, and the result is | X
21-2X22 + X23 | / 2 is output, which is shown in FIG.
It becomes the absolute value of the secondary differential amount in the main scanning direction shown in 0,
The strength of the edge in the main scanning direction shown in is output.

X31 and X23 are input to the A and C inputs of the edge detection circuit 414, respectively, and the result is | X
31-2X22 + X13 | / 2 is output, which is shown in FIG.
It becomes the absolute value of the second derivative amount in the diagonally downward right direction indicated by 0, and the strength of the edge in the diagonally downward right direction shown in FIG. 10 is output.

Reference numeral 415 in FIGS. 5 and 6 denotes a maximum value detection circuit, which determines which input signal has the maximum value among the four input signals a, b, c and d, and outputs 2 bits. The determination result y of is output.

FIG. 7 shows details of the maximum value detection circuit 415. In the figure, 421 is a comparator, which outputs "1" only when a> b as the comparison result of a and b. Four
Reference numeral 22 denotes a 2-input 1-output selector, which is a 2-input signal A,
By inputting a and b to B and inputting the comparison result of the comparator 421 to the select signal S, as a result, the maximum value m of a and b is input.
Output ax (a, b).

Similarly, a comparator 423 and a selector 424
From, the comparison result of c and d and the maximum value max of c and d
(C, d) is output.

Further, the maximum value max (a, b) of a and b and the maximum value max (c, d) of c and d are respectively calculated by the comparator 4
25, and outputs the y ₁ signal. As a result, the y ₁ signal has the maximum value max (a, b, c, d)
It becomes "1" when the value of b, c, d) is a or b.
In other words, the maximum value max (a, b, c of a, b, c, d
It becomes "0" when the value of c, d) is c or d.

Reference numeral 428 denotes inverters 426, 427, 42.
Reference numeral 9 denotes a 2-input NAND gate, and as a result, the y ₀ signal has a maximum value max (a, b, c) of a, b, c, d.
When the value of c, d) is a or c, it becomes "1" (a,
When the maximum value ma (a, b, c, d) of b, c, d is b or d, it becomes "0". ) That is, a, b, c, d
Depending on the value of the maximum value max (a, b, c, d) of, the 2-bit outputs y ₀ and y ₁ of the maximum value detection circuit are as follows.

When max (a, b, c, d) = a y ₀ = 1 y ₁ = 1 max (a, b, c, d) = b y ₀ = 0 y ₁ = 1 max (a , B, c, d) = c y ₀ = 1 y ₁ = 0 max (a, b, c, d) = d y ₀ = 0 y ₁ = 0 Returning to FIGS. 5 and 6, Reference numerals 416 to 419 denote smoothing circuits, which output a value of (A + 2B + C) / 4 for three inputs A, B, and C, as shown in FIG.
The B pixel of each of the four smoothing circuits is connected to the target pixel X22.
Has been entered.

X12 and X32 are input to the A and C inputs of the smoothing circuit 416, respectively, and the result is (X12 +
2X22 + X32) / 4 is output. This means the smoothing process in the sub-scanning direction shown in FIG.

X11 and X33 are input to the A and C inputs of the smoothing circuit 417, respectively, and the result is (X11 +
2X22 + X33) / 4 is output. This means the smoothing processing in the diagonally lower right direction shown in FIG.

X21 and X23 are input to the A and C inputs of the smoothing circuit 418, respectively, and the result is (X21 +
2X22 + X24) / 4 is output. This means smoothing processing in the main scanning direction shown in FIG.

X31 and X13 are input to the A and C inputs of the smoothing circuit 419, respectively, and the result is (X31 +
2X22 + X13) / 4 is output. This means the smoothing processing in the diagonally upper right direction shown in FIG.

Reference numeral 420 denotes a 4-input / 1-output selector, which operates with the following logic with respect to 4-input signals A, B, C, D and 2-bit select signal S (output signal from selector 415). .

When S = 00, B input is output (Y ← B) When S = 01, A input is output (Y ← A) When S = 10, D input is output (Y ← D) S = When the value is 11, the C input is output (Y ← C). Therefore, the final output of the pixel correction circuit is as follows: In FIG. 10, when the edge amount in the direction is the maximum, the direction is smoothed. .

When the edge amount in the direction is the maximum, the direction is smoothed.

When the edge amount in the direction is maximum, the direction is smoothed.

When the edge amount in the direction is maximum, the direction is smoothed.

That is, the smoothing direction is perpendicular to the edge direction (direction in which the density change is large).

[Result of Pixel Correction] The result of image correction will be described with reference to FIG. When an image having a density pattern as shown in FIG. 33 (a) is encoded / decoded by block encoding, FIG. 33 (b).
As shown in (4), there is a case in which ruggedness appears in units of 4 × 4 due to the coding error. Therefore, by performing the above-mentioned smoothing process on the same figure (b), the roughness is reduced as shown in the same figure (c).

For example, the pixel shown in A of FIG.
Compared to the A-equivalent pixel shown in FIG. 10A, the pixel is decoded to have a higher density, which causes the image to be rough.
In the pixel A in FIG. 10B, the amount of edge (density gradient) in the direction shown in FIG. 10 is larger than the amount of edge in the other direction, so the pixel is smoothed in the direction orthogonal to, and the density is corrected to be low. To be done. Similar corrections are made for the other pixels as well, and as shown in FIG. 7C, the overall shading is reduced. Further, since the smoothing process is performed in the direction orthogonal to the density gradient, the sharpness of the character portion is not impaired.

<Description of Second Embodiment> The present invention is not limited to the first embodiment described above. The second embodiment will be described with reference to FIG.

As shown in FIG. 40, as the determination signal for separating the image area, the difference between the L ^* maximum value and the minimum value of the 4 × 4 pixel block is used in the first embodiment. The distance between the maximum value and the minimum value of the chromaticity information on the color space is used.

1901, for the input a ^* signal
The line memories 1902 and 1903 delay by one line each (1908, 1909, 191 for b ^* signals).
0), aGAIN calculator 1904, bGAIN calculator 1
Input to the A to D inputs of 911. The obtained aGAIN signal and bGAIN signal are respectively multiplied by multipliers 1905, 1
The signal is squared from 912, further added by the adder 1906, and output as the rGAIN signal.

Then, the rGAIN signal is compared with the comparator 19
The threshold value sent from the CPU (not shown) is input to the B input of 07 to the A input of the comparator 1907.

Here, if A <B, the output L> FLG of the comparator 1907 becomes "1", and otherwise "0".
Is output.

<Explanation of Third Embodiment> The present invention is not limited to the actual sister example described above. Third using FIG.
An example will be described.

FIG. 40 shows an example of a full-color image encoder. A full-color image signal color-separated into red (R), green (G) and blue (B) is expressed by the following equation (15) in 2001. Are converted into Y, U and V signals.

[0176]

## EQU15 ## Y = c ₁ R + c ₂ G + c ₃ BU U = c ₄ (RY) V = c ₅ (BY) (15) where c ₁ , c ₂ , c ₃ , c ₄ , c ₅ is a constant, where Y is a signal representing lightness information, similar to L ^* ,
U and V are signals that represent chromaticity like a ^* and b ^* . Reference numeral 2002 denotes a circuit that performs discrete cosine transform, and n × n (n is a power of 2; n = 4, 8, 16, 32)
...) A circuit for performing discrete cosine transform of pixels. The Y signal is expanded into each spatial frequency component by the discrete cosine transform, and is encoded by the encoder 2006 by, for example, the Huffman code. Furthermore, as with 715, Y
The amplitude detector 2003 calculates the amplitude Y-GAIN of the Y signal in the n × n pixels.

On the other hand, reference numeral 2004 denotes a circuit similar to 7204, which outputs the amplitude ratio Ugain of the U signal to the amplitude of the Y signal and the DC component Umean of the U signal, and also outputs U−.
code. Similarly, 2005 is a circuit similar to 7204, and the amplitude ratio Vga of the V signal to the amplitude of the Y signal is Vga.
It is output as the DC component Vmean of the in and V signals, and is collectively referred to as V-code.

Furthermore, Y-code, U-code, V
The combination of -code is used as the code of the image data.

<Fourth Embodiment> In the first to third embodiments described above, as the information to be stored in the memory 116, the encoded L-code, ab-code, and the characteristic signals K ₁ and K ₂ are used. However, in addition to this, a signal indicating whether or not it is at an edge may be included. This example will be described as a fourth embodiment.

The construction of the entire apparatus in the fourth embodiment is shown in FIGS. 41 and 42. The difference from the first to third embodiments is that the encoder 113 encodes the encoded edge signal E.
A point to output the −code signal and a point to output the E-code signal to each of the decoders 117 and 118 when decoding. The overall configuration of the fourth embodiment is almost the same as that of the first to third embodiments, and only different points will be described for simplification of description.

In the fourth embodiment, the encoded L
When storing the -code data in the memory 116, the state shown by reference numeral 71108 'in FIG. 43 is basically set. Then, when the target block is at the edge portion, the amount of information is increased as compared with the case where it is not. That is, in the edge portion, since the information of the AC component is important, a large code length is assigned to the AC components L ₁ , L ₂ , M, and H. As a result, the number of bits assigned to the L-code data in the edge portion is as shown by reference numeral 71109 in FIG.

FIG. 44 shows the configuration of the lightness information decoder 113 'in the fourth embodiment.

The basic idea is that L _FLG in FIG.
Is to be used as a signal indicating whether an edge is present or not. That is, as shown in the figure, the LGAIN calculator 715 (see FIGS.
LGAIN obtained in (8) indicates the difference between the maximum brightness and the minimum brightness in a 4 × 4 block. The fact that it is at the edge of the image also means that the brightness change is large, so this brightness change amount is a predetermined value (fixed register 717
Comparing with the threshold value Th) held in the comparator 716, a signal ED signal indicating whether the edge is present or not is output. When the logic level of the ED signal is "1",
The 4 × 4 block of interest is at the edge of the image, and when it is “0”, it is at the non-edge.

Further, this ED signal is sent to the grouping circuit 7
09, the three flip-flops 718 to 720 delay three blocks as shown in FIG.
It is provided to the upper addresses of 0 to 713. L1, L2 output from the grouping circuit 709 are assigned to the lower addresses.
M and H are supplied.

As a result, when the block of interest is at the edge part, signals of 9, 9, 9, 8, and 8 bits are output as L1, L2, M, H, and AVE, and a total of 43 bits are output.
Quantized into bits. Further, when the target block is in the non-edge portion, signals of 8, 8, 8, 7, and 8 bits are output as L1, L2, M, H, and AVE, so that quantization is performed to 39 bits in total. become.

In order to synchronize with the output of the generated L-code signal, the obtained ED signal is delayed by one block by the flip-flop 721 and output as E-code.

Next, the chromaticity signal encoder (reference numeral 114 'in FIG. 41) in the fourth embodiment will be described.

A block diagram of the chromaticity signal encoder 114 'is shown in FIG. The internal structure of a ^* quantization 7204 'and 7208' in this encoder 114 'will be described. However, these quantizing circuits have been described with reference to FIGS. 23, 24 and 25 in the first embodiment, but FIGS. 23 and 24 are adopted as they are in the fourth embodiment as well, and different configurations are used here. Only this will be described with reference to FIG. This FIG. 46 is the same as FIG. 25 in the first embodiment.
The portion corresponding to is shown.

What is different in the drawing is that a selector 72158 having two inputs and one output is newly provided. The selector 72158 operates using the ED-code signal described above as a switching signal, and selects an 8-bit signal when the target block is at the edge of the image, and a 6-bit signal when it is at the non-edge. Select and output the signal.

With this configuration, the quantizing circuit 7204 or 7208 in FIG. 45 can output 6 bits when the target block is at the image edge and 8 bits when the target block is at the non-edge. become.

Here, the code length of the 4 × 4 pixel block in the coding system of the fourth embodiment will be described below with reference to FIG.

Reference numeral 1101 denotes a format of coded data when the target block is located at the image edge portion.
Reference numeral 2 shows the format of the encoded data in the non-edge portion.

The E-code indicating whether the target block is at the edge or at the non-edge is assigned to the leading bit. In addition, AV which is the DC component of the brightness information
8 bits are allocated to E. Further, as described above, since the AC component of the brightness information is more important in the edge portion than in the non-edge portion, the number of bits to be assigned to the AC components L1, L2, M, and H is set to the non-edge portion. , 9, 9, 8 bits more than that in (8, 8, 8, 7 bits respectively in the non-edge part).

On the other hand, the a _mean signal and the b _mean signal, which are the DC components of the chromaticity component, are assigned 6 bits in the edge portion and 8 bits in the non-edge portion, respectively. This is because the information on the DC component in the non-edge portion is more important than that in the edge portion. Also, the DC component _gain of the chromaticity information
4 bits are assigned to each of the edge portion and the non-edge portion for the signal and the b _gain signal.

As a result, when the target block is at the edge portion, 43 bits are assigned to the lightness information and 20 bits are assigned to the chromaticity information, and 39 bits are assigned to each of the non-edge portions.
Twenty-four bits will be allocated. Then, 1 bit indicating whether or not it is an edge portion is allocated to each, and each is composed of 64 bits. That is, the encoded data is encoded into a fixed length of 64 bits regardless of the edge / non-edge.

This means that when reading data from the memory 116 ', it is sufficient to read 64 bits regardless of whether the data is at the edge / non-edge.

As described above, the encoded data is stored in the memory 116 '. Next, the decoding process in the fourth embodiment will be described.

The block configuration of the lightness component decoder 117 according to the fourth embodiment is shown in FIG. The difference from FIG. 36 is that an E-code signal is added as an address of each lookup table ROM 1601-1604 (supplied to the most significant address bit). This means
This is because the meaning of each bit differs depending on whether the encoded data of the lightness component read from the memory 116 'is at an edge or not. This also applies to the chromaticity decoder.

As described above, according to the fourth embodiment, the brightness information and the chromaticity information have a variable length, but the encoded data of one block has a fixed length regardless of the edge / non-edge. You can Therefore, the circuit configuration can be further simplified, and since the encoding is performed according to the state in which each block is placed, the reproduced image can be made more precise.

<Explanation of Fifth Embodiment> The present invention is not limited to the above-described fourth embodiment. The fifth embodiment will be described with reference to FIG.

FIG. 49 shows an example of a full-color image encoder. The full-color image signal color-separated into red (R), green (G) and blue (B) has been described in 1801 (14). It is converted into Y, U and V signals according to the formula.

Reference numeral 1802 is a circuit for performing a discrete cosine transform, and n × n (n is a power of 2; n = 4, 8, 16,
32 ...) is a circuit for performing discrete cosine transform of pixels.
The Y signal is expanded into each spatial frequency component by the discrete cosine transform, and is encoded by the encoder 1805 by, for example, the Huffman code. Further, the amplitude detector 1803 for Y detects the amplitude Y− of the Y signal in the n × n pixels.
GAIN is calculated.

Further, as in the fourth embodiment, Y-GAI
Depending on the size of N, it is determined whether the n × n pixel block is an edge portion or a flat portion, and the determination result (E−
The code length assigned to each code is appropriately variable depending on the level of the code signal.

On the other hand, 1084 is a circuit similar to 7204, which outputs as the amplitude ratio Ugain of the U signal with respect to the amplitude of the Y signal and the DC component Umean of the U signal, and also outputs U−.
code. Similarly, 2005 is a circuit similar to 7204, and the amplitude ratio Vga of the V signal to the amplitude of the Y signal is Vga.
It is output as the DC component Vmean of the in and V signals, and is collectively referred to as V-code.

Furthermore, Y-code, U-code, V
The combination of -code is used as the code of the image data.

FIG. 50 shows an example of the code length in the fifth embodiment. n × n pixel blocks (n = n in the above embodiment)
When it is determined that the image in 4) is an edge portion, E-
The code is "1", and the bit array is as shown by reference numeral 18101.

When the n × n pixel block is in the non-edge portion (flat portion), the E-code is "0", and the bit arrangement is as shown by reference numeral 18102. That is, in the edge portion, a large code length of lightness information is secured and the code length of chromaticity information is reduced. In the flat part, on the contrary, the code length of the lightness information is reduced and the code length of the chromaticity information is increased. As a result, appropriate encoding can be performed without missing important information.

<Description of Sixth Embodiment> Next, a sixth embodiment will be described.

In the sixth embodiment, the lightness component L ^* and the chromaticity components a ^* and b ^* are coded in the same manner as in the above embodiment. Further, in the fourth embodiment, each code length is controlled by the strength of the edge component of the lightness information, but in the sixth embodiment, each code length is controlled by the strength of the edge component of the chromaticity information.

FIG. 51 shows a chromaticity component encoding circuit corresponding to that of FIG. 45 in the fourth embodiment, and the same reference numerals are given to the portions which perform the same processing.

In the figure, 1901 and 1902 are
Encoders for a ^* and b ^* , respectively, mean and g
The output of ain has the same configuration as 7204 and 7208. Further, from the max output of 1901, the maximum data a _max of a ^* in the 4 × 4 block is obtained, and from min, it is 4
The minimum value a _min of a ^* in the × 4 block is output. Similarly, the max output of 1902 outputs the maximum data b _max of b ^* in the 4 × 4 pixel block, and the min outputs the minimum value data b _min of b ^* .

Reference numerals 1903 and 1904 denote subtractors, respectively, which outputs Δa, which is a value obtained by subtracting a _min from a _max, from 1903, and Δb, which is obtained by subtracting b _min from b _max, from 1904. To be done. 1905 is an adder,
The sum of a and Δb, Δa + Δb, is output.

This Δa + Δb indicates the degree of tint change in the 4 × 4 pixel block, and if this value is large, it can be determined that there is a tint edge. That is, this Δa + Δb is compared with the threshold Th, and the result is E-c.
Output as ode. The details of the circuit are omitted, but the fourth
The code lengths of the lightness component and the chromaticity component can be controlled as in the above embodiment.

<Explanation of Seventh Embodiment> A seventh embodiment will be described with reference to FIG. In the seventh embodiment, the lightness component L ^* and the chromaticity component a ^* are the same as in the above-described fourth embodiment ^.
And b ^* are encoded. In the fourth embodiment, each code length is controlled depending on the strength of the edge positive bnn of the lightness information. However, in the seventh embodiment, each code length is controlled depending on whether each pixel block is chromatic or achromatic. Control the length.

FIG. 52 shows a color component encoding circuit corresponding to FIG. 45 in the fourth embodiment. The same components as those in the fourth embodiment are designated by the same reference numerals. Reference numerals 1901 and 1902 denote a ^* and b ^* encoders, respectively. m
The outputs of ean and gain have the same configuration as 7204 and 7208. Furthermore, from the max output of 1901, 4
The maximum data a _max of a ^* in a × 4 pixel block is set to min
Outputs the minimum data a _min of a ^* . Similarly, 19
From the max output of 02, b ^* in the 4 × 4 pixel block
The maximum data b _max of b ^{* and} the minimum data a ^* of b ^* from min
Output _min .

Reference numerals 2001 to 2004 are comparators, and 2005 is a 4-input AND gate. Comparator 2
001 to 2004 are threshold values T set in advance.
Compare with _{h1 to} T _h4 .

As a result, the output C of the AND gate 2005
OL is T _h2 <a _min and a _max <T _h1 and T _h4
Only becomes 1 when <b _min and b _max <T _h3 ,
In other cases, it becomes "0".

In other words, by setting the values of T _{h1 to} T _h4 to appropriate values, the COL signal is "1" when the 4 × 4 block contains a chromatic color, and is only an achromatic color. If there is, it can be controlled so as to be "0".

FIG. 53 shows an example of the code length in the seventh embodiment. 2011 is COL = 1, that is, 4 × 4
The bit allocation when a chromatic color is included in a pixel block is shown. Moreover, 2012 has shown the case only for achromatic color. If the pixels in the 4 × 4 pixel block have only achromatic colors, the code length required for the code ab-code of the chromaticity information is reduced, and L is used to improve the reproducibility of black thin lines and the like.
It indicates that the code length required for -code can be increased.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

Furthermore, in the embodiment, the copying machine is described as an example, but the present invention is not limited to this. That is, the present invention aims at how to efficiently store a color image while keeping it in high quality when inputting and storing the color image. Therefore, for example, as the storage medium, the description has been made on the assumption that the memory 116 is an IC memory chip in the embodiment, but it is needless to say that the storage medium may be a magnetic storage medium such as a hard disk, a magneto-optical disk, or a magnetic tape.

[0222]

As described above, according to the present invention, it is possible to efficiently encode a color image while maintaining high quality.

Further, according to another invention, it is possible to generate code data corresponding to the state of each minute area and to make the code data have a single length.

[0224]

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a copying machine according to an embodiment.

FIG. 2 is an overall configuration diagram of a copying machine according to an embodiment.

FIG. 3 is a cross-sectional view of the copying machine of the embodiment.

FIG. 4 is a diagram illustrating scaling (enlargement / reduction) of an image.

FIG. 5 is a block configuration diagram of a pixel correction unit in the embodiment.

FIG. 6 is a block configuration diagram of a pixel correction unit in the embodiment.

FIG. 7 is a block configuration diagram of a maximum value detection circuit in the example.

FIG. 8 is a block configuration diagram of a smoothing circuit in the example.

FIG. 9 is a block configuration diagram of a pixel edge detection circuit in the example.

FIG. 10 is a diagram showing a correction direction of a pixel correction unit in the embodiment.

FIG. 11 is a block configuration diagram of a color space converter in the embodiment.

FIG. 12 is a diagram showing coefficients used in the color space converter in the embodiment.

FIG. 13 is a block configuration diagram of a brightness information encoder in the embodiment.

FIG. 14 is a diagram for explaining the outline of the lightness information code in the embodiment.

FIG. 15 is a block configuration diagram of a grouping circuit for vector quantization in the example.

FIG. 16 is a block configuration diagram of a grouping circuit for vector quantization in the example.

FIG. 17 is a block diagram of an LGAIN calculator in the embodiment.

FIG. 18 is a block configuration diagram of an LGAIN calculator in the embodiment.

FIG. 19 is a block configuration diagram of a search circuit for a maximum value and a minimum value in the sub-scanning direction of a pixel block in the example.

FIG. 20 is a block configuration diagram of a main-scanning-direction maximum value search circuit in the embodiment.

FIG. 21 is a block configuration diagram of a main-scanning-direction minimum value search circuit in the embodiment.

FIG. 22 is a block diagram of a chromaticity information encoding circuit in the example.

FIG. 23 is a block configuration diagram of a quantization circuit in the example.

FIG. 24 is a block configuration diagram of a quantization circuit in the example.

FIG. 25 is a block configuration diagram of a quantization circuit in the example.

FIG. 26 is a diagram illustrating encoding (compression) of image data in the embodiment.
It is a figure which shows the target block.

FIG. 27 is a block configuration diagram of a spatial filter according to an example.

FIG. 28 is a diagram illustrating a relationship between a character determination signal and each coefficient of filter processing based on the signal according to the embodiment.

FIG. 29 is a block configuration diagram of an area processing circuit in the example.

FIG. 30 is an explanatory diagram of a generation circuit of XPHS and YPHS signals in the example.

FIG. 31 is a timing chart showing an operation process of the copying machine of the embodiment.

FIG. 32 is a diagram illustrating an outline of area processing according to the embodiment.

FIG. 33 is a diagram for explaining pixel correction in the example.

FIG. 34 is a timing chart of the brightness information encoding circuit in the example.

FIG. 35 is a timing chart of the chromaticity information encoding circuit in the example.

FIG. 36 is a block diagram of a lightness component decoder in the embodiment.

FIG. 37 is a block diagram of a chromaticity information decoder in the embodiment.

FIG. 38 is a look-up table ROM in the embodiment.
It is a figure which shows an example of the quantization characteristic of.

FIG. 39 is a block diagram of image separation signal generation according to the second embodiment.

FIG. 40 is a block configuration diagram of a full-color image encoder in the third embodiment.

FIG. 41 is an overall configuration diagram of a copying machine according to a fourth embodiment.

FIG. 42 is an overall configuration diagram of a copying machine according to the fourth embodiment.

FIG. 43 is a diagram for explaining the outline of the lightness information code according to the fourth embodiment.

FIG. 44 is a diagram for explaining the outline of the lightness information code according to the fourth embodiment.

FIG. 45 is a block configuration diagram of a chromaticity component encoding circuit in the fourth embodiment.

FIG. 46 is a block configuration diagram of a quantization circuit according to a fourth embodiment.

[Fig. 47] Fig. 47 is a diagram illustrating a code length in an encoding method according to the fourth embodiment.

FIG. 48 is a lightness component decoder 11 according to the fourth embodiment.
7 is a block configuration diagram of No. 7.

[Fig. 49] Fig. 49 is a block configuration diagram of a full-color image encoder in a fifth example.

[Fig. 50] Fig. 50 is a diagram illustrating the code length in the encoding system according to the fifth embodiment.

FIG. 51 is a block diagram of a chromaticity component encoding circuit according to a sixth embodiment.

FIG. 52 is a block configuration diagram of a chromaticity component encoding circuit according to a seventh embodiment.

[Fig. 53] Fig. 53 is a diagram illustrating the code length in the encoding system according to the seventh embodiment.

[Explanation of symbols]

112 Color Space Converter 113 Lightness Information Encoder, 114 Chromaticity Information Encoder 116 Memory 117, 117 ′, 117 ″, 117 ″ ′ Lightness Information Decoder 118, 118 ′, 118 ″, 118 ′ '' Chromaticity information decoder 119, 119 ', 119'',119''' Color space converter 157-160 Magnification circuit 141-144 Decoder 151-156 Tristate gate 202 Read original 212 Image processing circuit Department

Claims (22)

[Claims] 1. A division process for dividing color image data into m × n (m and n are natural numbers) image blocks, and a color space conversion process for converting input color image data into lightness data and chromaticity data. A quantization step of separating the brightness data in the image block into a DC component and an AC component and quantizing the brightness data; and a first calculation step of calculating the amplitude of the AC component of the brightness data in the pixel block. A second calculation step of calculating the amplitude of the AC component of the chromaticity data in the pixel block, and the ratio of the amplitude of the AC component of the lightness data to the amplitude of the AC component of the chromaticity data. An image characterized by comprising: a first encoding step for encoding; and a second encoding step for nonlinearly encoding the amplitude ratio of the AC component of the chromaticity data and the AC component of the brightness data. Processing method. 2. The encoding of the amplitude ratio is a non-linear encoding in which a large number of code codes are assigned to a small amplitude ratio and a portion having a large amplitude ratio is put together with a small number of codes. The image processing method according to item 1. 3. The pixel block according to claim 1, wherein the pixel block is an n × n (n is a power of 2) pixel block, and a process for performing an orthogonal transformation is provided for each pixel block. Image processing method. 4. The image processing method according to claim 3, wherein the orthogonal transformation is Hadamard transformation. 5. The image processing method according to claim 3, wherein the orthogonal transform is a discrete Fourier transform or a discrete cosine transform. 6. The image processing method according to claim 1, wherein the encoded code length is a fixed length code. 7. A dividing means for dividing the color image data into m × n (m and n are natural numbers) image blocks, and a color space converting means for converting the input color image data into lightness data and chromaticity data. A quantizing unit that separates and quantizes the brightness data in the image block into a DC component and an AC component; and a first calculating unit that calculates the amplitude of the AC component of the brightness data in the pixel block. Second calculation means for calculating the amplitude of the AC component of the chromaticity data in the pixel block, and the ratio of the amplitude of the AC component of the brightness data to the amplitude of the AC component of the chromaticity data An image characterized by comprising: first encoding means for encoding; and second encoding means for nonlinearly encoding the amplitude ratio of the AC component of the chromaticity data and the AC component of the brightness data. Processing equipment. 8. The encoding of the amplitude ratio is a non-linear encoding in which a large number of code codes are assigned to a small amplitude ratio and a portion having a large amplitude ratio is combined with a small number of codes. The image processing device according to item 7. 9. The pixel block is an n × n (n is a power of 2) pixel block, and means for orthogonally transforming lightness data is provided for each pixel block. The image processing device according to item. 10. The image processing apparatus according to claim 9, wherein the orthogonal transformation is Hadamard transformation. 11. The image processing apparatus according to claim 9, wherein the orthogonal transform is a discrete Fourier transform or a discrete cosine transform. 12. The image processing method according to claim 7, wherein the encoded code length is a fixed length code. 13. A division step of dividing color image data into m × n (m and n are natural numbers) image blocks, a determination step of determining image attributes of the image blocks, and input color image data as brightness data. And a color space conversion step of converting into chromaticity data, a first encoding step of encoding lightness data corresponding to the divided image block, and a chromaticity data corresponding to the divided image block A second encoding process, and a data length for controlling the data length of each encoded data encoded in the first encoding process and the second encoding process based on the determination result of the determination process. An image processing method comprising: a control step. 14. The data length control step, wherein a combined data length of code data for a target image block obtained in the first encoding step and the second encoding step is made constant. The image processing method according to item 13. 15. The image processing method according to claim 13, wherein in the determination step, it is determined whether or not the image block of interest is at an image edge portion. 16. The image processing method according to claim 13, wherein in the determination step, it is determined whether or not the image block of interest is in a chromaticity edge portion. 17. The image processing method according to claim 13, wherein in the determination step, it is determined whether the image block of interest is a chromatic color or an achromatic color. 18. A dividing unit that divides color image data into m × n (m and n are natural numbers) image blocks, a determining unit that determines an image attribute of an image block, and input color image data as brightness data. And color space conversion means for converting into chromaticity data, first encoding means for encoding lightness data corresponding to the divided image blocks, and chromaticity data corresponding to the divided image blocks Second encoding means, and a data length for controlling the data length of each encoded data encoded by the first encoding means and the second encoding means based on the determination result of the determination means. An image processing apparatus comprising: a control unit. 19. The data length control means sets a combined data length of code data for the target image block obtained by the first coding means and the second coding means to be constant. The image processing apparatus according to item 18. 20. The image processing apparatus according to claim 18, wherein the determining means determines whether or not the image block of interest is located in an image edge portion. 21. The image processing apparatus according to claim 18, wherein the determining means determines whether or not the image block of interest is in a chromaticity edge portion. 22. The image processing apparatus according to claim 18, wherein the determination means determines whether the image block of interest is a chromatic color or an achromatic color.