JPH06124593A - Static ram - Google Patents

Abstract

PURPOSE:To secure the stable operation of a sense amplifier and to reduce power consumption even when dispersion in present on a sense amplifier by amplifying the difference of a current to be detected by the sense amplifier. CONSTITUTION:When a nMOS transistor 22 is made in an ON state, nMOS transistor 23 is made in an OFF state, a node 40 is made to a L level, and a node 41 is a high level in a memory cell 12, a current flows from a bit line BL side to the memory cell 12 when this cell 12 is selected at the time of reading out. A current flowing in pMOS transistors 28 and 29 is assumed Ia, a current flowing in the cell 12 is assumed as Ic, currents flowing in a resistor 54 are Ia-Ic, and a current flowing in a resistor 55 is Ia. Since the resistance values of the resistors 54 and 55 are assumed the same value, a current flows in a transistor 56 out of nMOS transistors 56 and 57. In this case, when a current flowing in the transistor 56 is assumed as Id, the difference of a current DELTAI to be detected by a sense amplifier 15 is amplified as shown in equation Ia+Ib-(Ia-Ic-Id)=2Id+Ic.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static RAM (static r) having a flip-flop as a storage element.
andom access memory. In the following, it will be referred to as SRAM), and an SRAM configured to include a current detection type sense amplifier.

[0002]

2. Description of the Related Art Conventionally, an SRAM having a block diagram shown in FIG. 7 is known. In the figure, 1 is SRA
M body (chip _{body), 2 0, 2 1 ···} 2 n row address signal input terminal to which a row address signal A _0, A ₁ ··· A _n are _{input, 2 n + 1, 2 n} + 2 ... 2 _m are column address signal input terminals to which the column address signals A _{n + 1} , A _{n + 2,} ... _Am are input.

Reference numeral 3 designates the waveforms of the row address signals A ₀ , A ₁ ... A _n input via the row address signal input terminals 2 ₀ , 2 ₁ ... 2 _n to form complementary signals. Is a row address buffer that outputs an internal row address signal.

Reference numeral 4 is a row decoder for decoding an internal row address signal output from the row address buffer 3 to select a word line. Reference numeral 5 is a memory cell array portion in which memory cells are arranged.

6 is a column address signal input terminal 2
_{n + 1, 2 n + 2} ··· 2 column address signal A _{n + 1} is input through the _{m, A n + 2 ··· A} m formed by complementary signaling to waveform shaping the internal column address signal Is a column address buffer that outputs

Further, 7 is a column decoder for decoding the internal column address signal output from the column address buffer 6 and outputting a column selection signal, and 8 is a column selection based on the column selection signal output from the column decoder 7. It is a column switch that does.

Further, 9 is a sense amplifier for sensing the data stored in the selected memory cell at the time of reading, 10 is an output buffer for outputting the data sensed by the sense amplifier 9 to the outside, 11 Is a data output terminal to which data is output.

Further, FIG. 8 shows a basic circuit of an example of a conventional SRAM having a current detection type sense amplifier,
In the figure, WL is a word line, BL, / BL is a bit line, 12
Is a memory cell, 13 is a current supply circuit (load circuit), 14
Is a column switch, 15 is a current detection type sense amplifier composed of a differential amplifier, and 16 is an output buffer.

In the memory cell 12, 17 is a high resistance load type flip-flop, 18 and 19 are VCC power supply lines for supplying a power supply voltage VCC, 20 and 21 are high resistances as loads, and 22 and 23 are driving. NMOS transistors, which are transistors for memory cells, and 24 and 25 are nMOS transistors, which are transistors for selecting memory cells.

In the current supply circuit 13, 26,
Reference numeral 27 is a VCC power supply line, and 28 and 29 are pMOS transistors of the same size which are transistors for supplying current. These pMOS transistors 28 and 29 have their gates grounded and are turned on during operation.

Further, in the column switch 14, 3
0 and 31 are pMOS transistors, 32 and 33 are nMO
At the time of selection, an L-level is applied to the gates of the pMOS transistors 30 and 31 and an H-level is applied to the gates of the nMOS transistors 32 and 33, and the pMOS transistors 30 and 31 and the nMOS transistors 32 and 33 are turned on. To be done.

In the sense amplifier 15, 34,
Reference numeral 35 is a VCC power supply line, 36 and 37 are pMOS transistors which are load transistors, and 38 and 39 are nMOS transistors which are drive transistors.

Here, in the memory cell 12, nMO
S transistor 22 = ON, nMOS transistor 23
= OFF, node 40 = L level, node 41 = H level, when this memory cell 12 is selected during reading, a current flows from the bit line BL side to the memory cell 12.

Here, pMOS transistors 28 and 29 are provided.
The current flowing through the I _a, the memory cell from the bit line BL 12
When the current flowing into the column switch 14 is I _C , the current flowing through the column switch 14 is I _a −I _{c on} the side of the pMOS transistor 30 and the nMOS transistor 32, and
1, the nMOS transistor 33 side becomes I _a , and the current difference ΔI to be detected by the sense amplifier 15 is I _a − (I _a −I
_c ) = I _c .

Here, for example, I _a = 2 mA and I _c = 0.
If it is 5 mA, pMOS transistor 30 and nMOS
Current flowing through the transistor 32 side is I _a -I _c = 2-0.
5 = 1.5 mA, pMOS transistor 31, nMOS
The current flowing through the transistor 33 side is I _a = 2 mA, and the current difference ΔI to be detected by the sense amplifier 15 is 2-
It becomes 1.5 = 0.5 mA.

[0016]

As described above, the conventional S
In the RAM, the current difference to be detected by the sense amplifier 15 is determined by the current flowing into the memory cell 12. For this reason, there is a problem that the stable operation of the sense amplifier 15 cannot be secured if the current difference to be detected by the sense amplifier 15 is small and the characteristics of the sense amplifier 15 vary in the process.

In view of the above point, the present invention can ensure a stable operation of the sense amplifier even when the current detection type sense amplifier for detecting the data stored in the memory cell has variations. SRAM capable of reducing power consumption
The purpose is to provide.

[0018]

FIG. 1 is a diagram for explaining the principle of the present invention, in which 42 is a memory cell, 43 and 44 are input / output terminals of the memory cell 42, and 45 and 46 are currents supplied from upstream end portions. Current paths, 47 and 48 are resistance elements having the same or substantially the same resistance value, 49 and 50 are unidirectional elements, and 51 is a current detection type sense amplifier. The current paths 45 and 46 are
In the figure, the upper side is upstream and the lower side is downstream.

That is, in the SRAM according to the present invention, the input / output terminals 43 and 44 of the memory cell 42 are connected to each other, and the input / output terminal 43 of the memory cell 42 of the current paths 45 and 46 to which the current is supplied from the upstream side ends. , 44 are connected in series downstream of the connection point to which the resistance elements 44, 44 are connected, respectively, and the current path 45 downstream of the resistance element 47 and the resistance path downstream of the resistance element 48 are connected. Current path 46
Between the unidirectional elements 49 and 50 in the forward and reverse directions, and the current paths 45 and 4 downstream of the connection points 52 and 53 to which the unidirectional elements 49 and 50 are connected.
The difference between the currents flowing in 6 is detected by the current detection type sense amplifier 51, and the data stored in the memory cell 42 is read out.

[0020]

At the time of reading, if the current I _x is supplied to the current paths 45 and 46 from the upstream side and the current I _y flows into the memory cell 42 from the current path 45 side through the input / output terminal 43, current flowing through the resistor element 47 is I _X -I _y, and the current flowing through the resistor element 48 becomes I _x.

Here, the resistance values of the resistance elements 47 and 48 are
Since they are the same or substantially the same, the voltage of the node 52>
The voltage is applied to the node 53, and a current flows through the unidirectional element 49 of the unidirectional elements 49 and 50.

In this case, assuming that the current flowing through the unidirectional element 49 is I _z , the current flowing through the current path 45 on the downstream side of the node 52 becomes I _x −I _y −I _z , which is the current on the downstream side of the node 53. The current flowing through the current path 46 is I _x + I _z .

Therefore, the current difference ΔI to be detected by the sense amplifier 51 is I _x + I _z − (I _x −I _y −I _z ) = 2I _z
It becomes + I _y . When the resistance elements 47, 48 and the unidirectional elements 49, 50 are not provided, that is, in the conventional case, the current difference ΔI to be detected by the sense amplifier 51 is I _x − (I _x
−I _y ) = I _y .

As described above, according to the present invention, since the current difference to be detected by the sense amplifier 51 can be amplified, the sense amplifier 51 can be stabilized even when the sense amplifier 51 has variations in characteristics. The operation can be secured.

Further, according to the present invention, the sense amplifier 51
Can amplify the current difference to be detected, the stable operation of the sense amplifier 51 can be ensured even if the current _IX flowing from the upstream side to the current paths 45 and 46 is somewhat reduced, and the current consumption is reduced. It is possible to reduce power consumption.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first embodiment of the present invention will be described below with reference to FIGS.
The conventional SRA shown in FIG. 8 for the examples to the fourth example
The case of improving M will be described as an example. Therefore, in FIGS. 2 to 4 and 6, the portions corresponding to those in FIG. 8 are designated by the same reference numerals, and the duplicate description thereof will be omitted.

First Embodiment FIG. 2 FIG. 2 is a circuit diagram showing an essential part of the first embodiment of the present invention.
In the first embodiment, the pMOS transistor 3
0, the data bus DB connected to the bit line BL via the nMOS transistor 32 and the pMOS transistor 3
1, bit line / BL via nMOS transistor 33
Resistors 54 and 55 having the same resistance value are respectively connected in series to a data bus / DB connected to.

Further, on the downstream side of the resistors 54 and 55, that is, on the current output side of the resistors 54 and 55, diode-connected nMOS transistors 56 and 57 are respectively connected in the forward direction and the reverse direction, and nodes 58 and 59 are provided. The sense amplifier 15 is adapted to detect the difference in the current flowing on the downstream side. Otherwise, the configuration is similar to that of the conventional SRAM shown in FIG.

Here, in the memory cell 12, nMO
S transistor 22 = ON, nMOS transistor 23
= OFF, node 40 = L level, node 41 = H level, when this memory cell 12 is selected during reading, a current flows from the bit line BL side to the memory cell 12.

Here, pMOS transistors 28 and 29 are provided.
_Let I _a be the current flowing into the memory cell 12 and I _C be the current flowing into the memory cell 12 via the bit line BL, the current flowing through the resistor 54 is I _a −I _c , and the current flowing through the resistor 55 is I _a .

Here, since the resistance values of the resistors 54 and 55 are the same, the voltage of the node 58> the voltage of the node 59, and the nM of the nMOS transistors 56 and 57 is nM.
A current flows through the OS transistor 56.

In this case, assuming that the current flowing through the nMOS transistor 56 is I _d , the current flowing downstream of the node 58 becomes I _a −I _c −I _d , and the current flowing downstream of the node 59 is I _a + I _d .

[0033] Thus, the current difference ΔI sense amplifier 15 is to be _{detected, I a + I d - (} I a -I c -I d) = 2I d
+ I _c . Incidentally, in the conventional SRAM shown in FIG.
The current difference ΔI to be detected by the sense amplifier 15 is I _a −
(I _a −I _c ) = I _c .

Here, for example, I _a = 2 mA and I _c = 0.
Assuming 5 mA and I _d = 0.25 mA, the current flowing through the resistor 54 becomes I _a −I _c = 2-0.5 = 1.5 mA, and the current flowing through the resistor 55 becomes I _a = 2 mA, which is downstream of the node 58. Current flowing to the side is 1.5-0.25 = 1.25mA, node 5
The current flowing to the downstream side of 9 is 2 + 0.25 = 2.25 mA
Becomes

Therefore, the current difference ΔI to be detected by the sense amplifier 15 is 2.25-1.25 = 1 mA. In the conventional SRAM shown in FIG. 8, the sense amplifier 15
The current difference ΔI to be detected by is 0.5 mA.

As described above, according to the first embodiment, the current difference to be detected by the sense amplifier 15 can be amplified. Therefore, even if the sense amplifier 15 has a characteristic variation, the sense amplifier 15 can be used. The stable operation of the sense amplifier 15 can be ensured and the stable operation of the sense amplifier 15 can be ensured even if the current I _a to be flown from the upstream side to the bit lines BL and / BL is slightly reduced. It is possible to reduce power consumption.

Second Embodiment FIG. 3 FIG. 3 is a circuit diagram showing an essential part of the second embodiment of the present invention.
In the second embodiment, the size of pM shown in FIG. 2 is used as a current supply transistor on the upstream side of the bit line BL.
The pMOS transistors 60 and 61, which are half of the OS transistors 28 and 29, are connected.

Further, the pMOS transistors 62 and 6 having the same size as the pMOS transistors 60 and 61 as transistors for supplying current on the upstream side of the bit line / BL.
3 is connected.

Here, pMOS transistors 60 and 62
Has its gate grounded and is turned on during operation. The gates of the pMOS transistors 61 and 63 are connected to the nodes 58 and 59, respectively. Others are the same as those of the first embodiment shown in FIG.

Thereafter, as in the conventional example and the first example, in the memory cell 12, the nMOS transistor 22 = O.
N, nMOS transistor 23 = OFF, node 40
= L level and node 41 = H level will be described.

In the second embodiment, the size of the pMOS transistors 60 and 61 is half that of the pMOS transistors 28 and 29 shown in FIG. 2, so that the current flowing through these pMOS transistors 60 and 61 is I
It becomes _a / 2.

Assuming that the current flowing through the pMOS transistor 62 is I _f1 and the current flowing through the pMOS transistor 63 is I _f2 , the current flowing through the resistor 54 is I _a / 2 +.
I _f1 −I _c , and the current flowing through the resistor 55 is I _a / 2 +
It becomes I _f2 .

In this case, the voltage of node 58> node 59
Therefore, I _f1 <I _f2 . Here, for example, I _f1 = 0.5 mA and I _f2 = 0.66 mA, and the current flowing through the resistor 54 is I _a / 2 + I _f1 −I _c = 1 + 0.5.
−0.5 = 1 mA, the current flowing through the resistor 55 is I _a / 2 +
I _f2 = 1 + 0.66 = 1.66 mA.

As a result, the current flowing to the downstream side of the node 58 is 1-0.25 = 0.75 mA, and the current flowing to the downstream side of the node 59 is 1.66 + 0.25 = 1.91 mA, and the sense amplifier 15 The current difference ΔI to be detected by is 1.
91-0.75 = 1.16 mA. In the case of the first embodiment shown in FIG. 2, the current difference ΔI to be detected by the sense amplifier 15 is 1 mA.

As described above, according to the second embodiment, the current difference to be detected by the sense amplifier 15 can be amplified more than in the case of the first embodiment, so that the sense amplifier 15 has variations in characteristics. In some cases, more stable operation of the sense amplifier 15 can be ensured than in the case of the first embodiment, and even if the current to be flown from the upstream side to the bit lines BL and / BL is slightly reduced, the sense operation is performed. Amplifier 1
The stable operation of No. 5 can be secured, and the power consumption can be reduced.

Third Embodiment ... FIG. 4 and FIG. 5 FIG. 4 is a circuit diagram showing a main part of a third embodiment of the present invention.
In the third embodiment, NAND circuits 64 and 65 and an inverter 66 are added.

Here, in the NAND circuit 64, the voltage of the node 67 is input to one input terminal, the clock pulse CP shown in FIG. 5D is input to the other input terminal, and its output is applied to the gate of the pMOS transistor 61. Is connected to.

In the NAND circuit 65, the voltage of the node 67 is input to one input terminal via the inverter 66, and the clock pulse CP shown in FIG. 5D is input to the other input terminal.
Is input and the output is connected to the gate of the pMOS transistor 63.

Therefore, the gate of the pMOS transistor 61 is not connected to the node 58, and
The gate of the transistor 63 is not connected to the node 59. Others are the same as those in the second embodiment.

Thereafter, in the memory cell 12, the nMOS transistor 22 = ON and the nMOS transistor 23 = O as in the case of the conventional example, the first embodiment and the second embodiment.
The case where the node 40 is at the L level and the node 41 is at the H level in the FF will be described.

FIG. 5 is a waveform diagram showing the operation of the third embodiment. FIG. 5A is an externally supplied system clock, FIG. 5B is an address signal transition, and FIG. 5C is a word line W.
L level, FIG. 5D shows the clock pulse CP supplied to the NOR circuits 64 and 65, FIG. 5E shows the output of the sense amplifier 15, and FIG. 5F shows the output of the output buffer 16. In FIG. 5C, the broken line shows the case of so-called pulse control.

Also in the third embodiment, the voltage of the node 58> the voltage of the node 59, so that the sense amplifier 15
Node 67 = L level, node 68 = H level, output of NOR circuit 64 = H level, NOR circuit 65
Output = L level.

As a result, the pMOS transistor 61 is cut off, the pMOS transistor 63 is completely turned on, and the current flowing through the pMOS transistor 61 is 0.
The current flowing through the mA and pMOS transistor 63 is I _f2
= 1 mA.

Therefore, the current flowing through the resistor 54 is I
_{a / 2-I c = 1-0.5} = 0.5mA, the current flowing through the resistor _{55, I a / 2 + I f2} = 1 + 1 = 2mA, node 58
The current flowing to the downstream side is 0.5-0.25 = 0.25m
A, the current flowing on the downstream side of the node 59 is 2 + 0.25.
= 2.25 mA.

Therefore, the current difference ΔI to be detected by the sense amplifier 15 is 2.25−0.25 = 2 mA. In the case of the second embodiment shown in FIG. 3, the sense amplifier 1
The current difference ΔI to be detected by 5 is 1.16 mA.

As described above, according to the third embodiment, the current difference to be detected by the sense amplifier 15 can be amplified more than in the case of the second embodiment, so that the sense amplifier 15 has variations in characteristics. In this case, more stable operation of the sense amplifier 15 can be ensured than in the second embodiment, and even if the current to be flown from the upstream side to the bit lines BL and / BL is reduced to some extent, Stable operation can be ensured and power consumption can be reduced.

Fourth Embodiment FIG. 6 FIG. 6 is a circuit diagram showing an essential part of a fourth embodiment of the present invention.
In the fourth embodiment, pMOS transistors 60 and 62
Has the same size as the nMOS transistors 22 and 23 which are transistors for driving the memory cell 12.

That is, the pMOS transistors 60 and 62
Is _Ia / 4 = 0.5 m with respect to the bit lines BL and / BL.
It is configured to supply A. Others are the same as those of the third embodiment shown in FIG.

Hereinafter, in the memory cell 12, the nMOS transistor 22 = ON and the nMOS transistor 23 = OF, as in the conventional example and the first to third examples.
In F, the case where the node 40 = L level and the node 41 = H level will be described.

Also in the fourth embodiment, since the voltage of the node 58> the voltage of the node 59, the sense amplifier 15
Node 67 = L level, node 68 = H level, output of NOR circuit 64 = H level, NOR circuit 65
Output = L level.

As a result, the pMOS transistor 61 is cut off, and the current flowing through the pMOS transistor 61 becomes 0 mA. On the other hand, the pMOS transistor 63 is turned on, and the current flowing through the pMOS transistor 63 becomes I _f2 = 1 mA.

Therefore, the current flowing through the resistor 54 is I
_{a / 4-I c = 0.5-0.5} = 0mA, the current flowing through the resistor _{55, I a / 4 + I f2} = 0.5 + 1 = 1.5mA , and this case, the current flowing to the downstream side of the node 58 Is 0m
A, the current flowing on the downstream side of the node 59 is 1.5 mA.

Therefore, the current difference ΔI to be detected by the sense amplifier 15 is 1.75-0.25 = 1.5 mA. In the case of the second embodiment shown in FIG. 3, the current difference ΔI to be detected by the sense amplifier 15 is 1.16 m.
It is A.

As described above, according to the fourth embodiment, the current difference to be detected by the sense amplifier 15 can be amplified more than in the case of the second embodiment, so that the sense amplifier 15 has variations in characteristics. In this case, more stable operation of the sense amplifier 15 can be ensured than in the second embodiment, and even if the current to be flown from the upstream side to the bit lines BL and / BL is reduced to some extent, Stable operation can be ensured and power consumption can be reduced.

In the first to fourth embodiments,
A resistor 54 connected in series to the data buses DB, / DB,
55 can be configured by using not only pure resistance but also ON resistance of a pMOS transistor.

In the first to fourth embodiments, the diode-connected nMOS transistors 56 and 57 are connected as unidirectional elements between the nodes 58 and 59, but instead of this, Diode connected p
You may make it connect a MOS transistor.

[0067]

According to the present invention, since the current difference to be detected by the sense amplifier can be amplified, stable operation of the sense amplifier can be ensured even when the characteristics of the sense amplifier vary. In addition, the stable operation of the sense amplifier can be ensured and the power consumption can be reduced even if the current to be flown from the upstream side to the current path for reading the data of the memory cell is slightly reduced. You can

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a main part of the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a main part of a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a main part of a third embodiment of the present invention.

FIG. 5 is a waveform chart showing the operation of the third embodiment of the present invention.

FIG. 6 is a circuit diagram showing a main part of a fourth embodiment of the present invention.

FIG. 7 is a block diagram showing a main part of an SRAM.

FIG. 8 is a circuit diagram showing a basic circuit of a conventional SRAM.

[Explanation of symbols]

 42 memory cell 43, 44 input / output terminal of memory cell 45, 46 current path 47, 48 resistance element 49, 50 unidirectional element 51 current detection type sense amplifier

Claims (6)

[Claims] 1. A first and a second current path (45) to which currents are supplied from an upstream side end to which first and second input / output terminals (43, 44) of a memory cell (42) are connected, respectively. Four
6) First and second resistors having the same or substantially the same resistance value downstream of the connection point to which the first and second input / output terminals (43, 44) of the memory cell (42) are connected. The elements (47, 48) are connected in series and the first
The first current path (45) downstream of the resistive element (47) of
And a second current path (46) downstream of the second resistive element (48) with first and second unidirectional elements (49, 50) in forward and reverse directions, respectively. Connect to
The difference between the currents flowing in the first and second current paths (45, 46) downstream of the connection point (52, 53) to which the first and second unidirectional elements (49, 50) are connected. Is detected by a current detection type sense amplifier (51), and the data stored in the memory cell (42) is read out. 2. A first pMOS having a source connected to a power supply line on the high potential side, a drain connected to an upstream end of the first current path (45), and a low potential voltage applied to the gate.
A second pMOS transistor having a transistor and a source connected to the power supply line on the high potential side, a drain connected to an upstream end of the second current path (46), and a low potential voltage applied to the gate. Is provided to supply a current to the first current path (45) via the first pMOS transistor and a current to the second current path (46) via the second pMOS transistor. The static RAM of claim 1 configured to supply. 3. A first pMOS having a source connected to a power supply line on a high potential side, a drain connected to an upstream end of the first current path (45), and a low potential voltage applied to a gate.
A second pMOS transistor having a transistor and a source connected to the power supply line on the high potential side, a drain connected to an upstream end of the second current path (46), and a low potential voltage applied to the gate. And a source connected to the power supply line on the high potential side, a drain connected to an upstream end of the first current path (45), and a gate connected to the downstream of the first resistance element (47). A third pMOS transistor connected to the first current path (45), a source connected to the high-potential-side power supply line, and a drain connected to the upstream end of the second current path (46). And a fourth pMOS transistor whose gate is connected to the second current path (46) downstream of the second resistance element (48), and through the first and third pMOS transistors. The first
Current path (45) and current is supplied to the second current path (46) via the second and fourth pMOS transistors. The static RAM according to claim 1. 4. A first pMOS having a source connected to a power supply line on the high potential side, a drain connected to an upstream end of the first current path (45), and a low potential voltage applied to the gate.
A second pMOS transistor having a transistor and a source connected to the power supply line on the high potential side, a drain connected to an upstream end of the second current path (46), and a low potential voltage applied to the gate. And a source connected to the power supply line on the high potential side, a drain connected to an upstream end of the first current path (45), and the memory cell (42) connected from the first current path (45). ), A high potential voltage is applied to the gate, and the second current path (4
A third pMOS in which a low potential voltage is applied to the gate when a current flows from 6) to the memory cell (42).
A transistor and a source are connected to the high-potential-side power supply line, a drain is connected to an upstream end of the second current path (46), and the first current path (45) to the memory cell ( When a current flows into 42), a low potential voltage is applied to the gate, and when a current flows from the second current path (46) into the memory cell (42), a high potential voltage is applied to the gate. And a fourth pMOS transistor that is provided.
The described static RAM. 5. A read voltage is applied to one of the input terminals by applying a drain voltage of a first nMOS transistor which forms a driving transistor of the sense amplifier (51) whose gate is connected to the first current path (45). At this time, for driving the first NOR circuit in which a low potential voltage is applied to the other input terminal and the sense amplifier (51) whose gate is connected to the second current path (46) at one input terminal. A second NOR circuit to which a drain voltage of a second nMOS transistor forming a transistor is applied and a low potential voltage is applied to the other input terminal at the time of reading, and a source is connected to a power source line on the high potential side and a drain is connected. Is connected to the upstream end of the first current path (45) and a low potential voltage is applied to the gate.
PMOS transistor and source connected to the high-potential-side power supply line, and drain connected to the second current path (46)
Of the first current path (45), a second pMOS transistor connected to the upstream end of the gate of the first pMOS transistor to which a low potential voltage is applied to the gate, a source connected to the high potential side power supply line, and a drain connected to the first current path A third pMOS transistor connected to the upstream end and having a gate connected to the output terminal of the first NOR circuit, a source connected to the high-potential-side power supply line, and a drain connected to the second current. 4. A fourth pMOS transistor connected to the upstream end of the path (46) and having a gate connected to the output terminal of the second NOR circuit. Static RAM. 6. The first and second pMOS transistors have the same current drivability as an nMOS transistor forming a driving transistor of a flip-flop forming the memory cell (42). The static RAM according to claim 4 or 5.