JPH06124549A - Reproducied data detection system - Google Patents

Abstract

PURPOSE:To improve a bit error rate to random errors by dinarizing reproduced signals at a reproduction side employing a code correlation, estimating a most likely state transition and deciding a trellis diagram. CONSTITUTION:Let S0 to S5 be six reproduction states. When -1 is inputted at S0, it transits to S0, make output data 0 and when 1 is inputted, it transits to S1 and the output data are made to 0. When 1 is inputted at S2, it transits to S3 and the output data are made to 0. When -1 is inputted at S3, it transits to S4 and the output data are made to 1. When 1 is inputted, it transits to S3 and the output data are made to 0. When -1 is inputted at S4, it transits to S5 and the output data are made to 0. When -1 is inputted at S5, it transits to S0 and the output data are made to 0. And a most likely state transition is estimated in accordance with the state transition rule, a trellis diagram is decided and bit error recorrections of a reproduction signal detection are performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproduction data detection method, and more particularly to a bit error correction method utilizing a state transition in the reproduction data detection method used in a digital VTR, an optical disk device or the like.

[0002]

2. Description of the Related Art Generally, in a reproduction data detecting method for a digital VTR, a digital optical disk recording apparatus, etc., when a discrimination of reproduced digital data is made, a threshold voltage is determined for each bit and the reproduction voltage level is set to that threshold voltage. “High” if the threshold voltage is exceeded,
When the reproduction voltage level does not exceed the threshold voltage, it is judged as "low".

Also, in some of the digital optical disk devices, a reproduction data detection method based on the partial reply pan (1,1) + Viterbi decoding method is used.

FIG. 5 shows a partial response (PR).
FIG. 6 is a block diagram showing an example of a conventional reproduction data detection method based on the (1,1) + Viterbi decoding method, and FIG. 6 is a timing chart of the conventional reproduction data detection method shown in FIG.

In FIGS. 5 and 6, the signal is NRZ / NRZI converted on the recording side by the precoater 11, and the partial response (P) is set by the PR (1,1) equalizer 13 on the reproducing side.
R) (1,1) detection is performed. The partial response (1,1) detection is a method of detecting data by utilizing the correlation between reproduced codes, and sets the reproduction equalization output signal to "..001100 .." for the recording signal "1", As a result, it is a method of detecting a level with three values. Viterbi decoding is performed after the partial response (1, 1) is detected.

FIG. 7 is a state transition diagram of the reproduction data detecting method shown in FIG. 5, and FIG. 8 is a trellis diagram thereof.

In FIGS. 7 and 8, the Viterbi decoding method sets the reproduction state to two states, S0 and S1, changes to S0 when 0 is input in S0, sets output data to 0, and inputs 1 in S0. When transitioning to S1, the output data is set to 1, and when 0 is input at S1, transition is made to S1 and the output data is set to 0, and -1 is set at S1.
, The output data is set to 1, and when there is an input that violates this state transition rule, the state of the violation is detected and the original state is judged to correct the bit error. This is a method for improving the error rate against random dam errors.

FIG. 9 is a diagram showing the probability of reproducing data in the state transition shown in FIG.

From FIG. 9,

[0010]

Here, the length of the metric can be represented by the negative logarithm of the probability. Therefore, the product of probabilities can be represented by the sum of the negative logarithms of the probabilities, that is, the sum of the metric lengths.

[0012]

Since the metric will discuss the relative value of the length instead of the absolute value in the future, a constant value is added to the sum of the logarithmic values and further multiplied by a constant value before comparison.

[0014]

[0015] The above 1 _00, 1 _10, 1 _11, to define the normalized metrics, and _{1 11 = 1 01 = 0 1} 10 = -y k +0.5 1 00 = y k +0.5.

Here, at time n, the sampled values are y _n ,
The standardized metrics of state S1 and state S0 are m
_{If n} (S1) and m _n (S0), then m _n (S1) = min [m _n-1 (S1) +1 ₁₀ , m _n-1 (S0) +1 ₀₁ ] = min [m _n-1 (S1 _{) -y n + 0.5, m n} -1 (S0)] m n (S0) = min [m n-1 (S1) +1 11, m n-1 (S0) +1 00] = min [m n- ₁ (S1), m _n-1 (S0) + y _n +0.5], and the above equation can be expanded as follows.

[0017]

[0018]

[0019]

[0020] The reproduced data and y _n, when a _{-1 ≦ y n ≦ 1, y} n + 0.5 from the input data, -y _n +0.5
Is calculated, and the metric m _n-1 (S1) is set as the merge 0.
When -m _n-1 (S0) is larger than y _n +0.5, the metric m _n (S1) is the metric m _n-1 (S0), and the metric m _n (S0) is the metric m _n-1 (S0) + y _n. +
0.5, and merge 1 as metric m _n-1 (S
1) -m _n-1 (S0) is between y _n +0.5 and y _n -0.5, the metric m _n (S1) is converted to the metric m _n-1.
(S0), metric m _n (S0) is converted to metric m _n-1
(S1) and merge 2 as metric m _n-1 (S
1) -m _n-1 (S0) is smaller than y _n -0.5, the metric m _n (S1) is converted to the metric m _n-1 (S1) -y _n.
+0.5, metric m _n (S0) is metric m _n-1
(S1).

Then, the paths are merged, and the most probable path is determined in the past from the point where the paths are merged. At high communication costs, such a path determination method is called the Viterbi decoding method. Here, since the merge is not performed at the immediately preceding time, even if the path shape at the time n is obtained,
At that point in time, no merge is done and no output value is obtained. However, due to the occurrence of merge 0 or merge 2,
The paths are merged and the corresponding output sequence is obtained.

FIG. 10 is a diagram showing an example of the pass purge.

In FIG. 10, when the paths are merged, the output is set to 0 for the states S0 → S0 and S1 → S1, and the state S0 is set.
Output data can be obtained by setting output 1 for S1, S1 and S0.

[0024]

The bit-by-bit judgment in the reproduction data detection method which has been generally used in the related art utilizes the characteristics of digital storage, and has a simple logic and a simple circuit. It has the advantage of being. However, if an error occurs in the reproduction voltage that slightly exceeds the threshold, all of them directly lead to a bit error. Further, there is a drawback in that the error once generated is corrected by the error correction circuit block, but cannot be corrected by the identification reproduction circuit block.

Further, the partial response (PR) (1,1) detection + two-state Viterbi decoding method using the inter-code correlation of the reproduced signal performs bit error correction by using the correlation due to the reproduced signal being ternary. However, in the code conversion method in which continuous non-sign inversion bits on the recording side are suppressed to within the range of at least 3 and converted into channel bits, and recorded, the continuous non-sign inversion bits on the recording side have a range of at least 3 It does not use the correlation that it is suppressed within, and the error rate is improved by bit error correction compared to the judgment for each bit, but it can not be said that the original capacity of the stored code is fully used. There are drawbacks.

[0026]

According to the reproduction data detecting method of the present invention, a code for recording a data bit by converting the data bit into a channel bit with the number of consecutive non-code inversion bits on the storage side kept to a minimum of 3 is recorded. In contrast to the conversion method, the reproduction signal is converted into a binary value by the partial response (1) to (1,1) detection using the inter-code correlation on the reproduction side, and after the level is determined, the reproduction state is S0, S1, S2. S3, S
4, when S-1 is input, transition to S0 and output data is 0, and when S0 is 1, transition to S1 is performed and output data is 1.
When 1 is input to 1 the output data changes to S2 and 0, when 1 is input to S2 the output data changes to S3 and 0 when the input data is 1 and when -1 is input to S3 the output data changes to S4. Then, the output data is set to 1, and when 1 is input in S3, the process proceeds to S3 and the output data is set to 0, and -1 is input in S4.
When inputting, the output data is 0 and the output data is 0. When inputting -1 in S5, the output data is 0 and the output data is 0. The most probable state transition is estimated according to the rule of the state transition, Performing re-bit error correction for reproduction signal detection by determining the trellis diagram, or
When the input data is y _n and −1 ≦ y _n ≦ 1, the reproduction state is set to the 6 states S0, S1, S2, S3, S4 and S5, and one of these states is taken as the reciprocal of the probability. Is called a metric, and the merge is 0, and the metric m
_{When n-1} (S3) is smaller than metric m _n-1 (S2) and metric m _n-1 (S0) is smaller than metric m _n-1 (S5), metric m _n (S5) is metric m _n-1.
(S4) + y _n , metric m _n (S4) is melolic m _n-1 (S3) + y _n , metric m _n (S3) is metric m _n-1 (S3) -y _n , metric m _n (S2)
Metric m _n-1 (S1) -y _n , metric m _n
(S1) is a metric m _n-1 (S0) -y _n , metric m _n (S0) is a metric m _n-1 (S0) + y _n, and the metric m _n-1 (S3) is a metric m as merge 1. smaller than _n-1 (S2), metric m _n-1 (S
0) is larger than the metric m _n-1 (S5), the metric m _n (S5) is the metric m _n-1 (S4) + y _n , and the metric m _n (S4) is the metric m _n-1 (S3) + y.
_n , metric m _n-1 (S3) is converted to metric m _n-1 (S
3) -y _n , metric m _n (S2) as metric m
_n-1 (S1) -y and _n, the metric m _n a (S1) metric _{m n-1 (S0) -y} n, the metric m _n a (S0) and the metric _{m n-1 (S5) +} y n, merge 2 , The metric m _n-1 (S3) is the metric m _n-1 (S
2) When the metric m _n-1 (S0) is larger than the metric m _n-1 (S5) and the metric m _n (S5) is the metric m _n-1 (S4) + y _n , the metric m _n (S5)
4) is a metric m _n-1 (S3) + y _n , a metric m
_n (S3) is a metric m _n-1 (S2) -y _n , metric m _n (S2) is a metric m _n-1 (S1) -y _n ,
The metric m _n (S1) is converted to the metric m _n-1 (S0)-
y _n and metric m _n (S0) are converted to metric m _n-1 (S
0) + y _n , merge 3 and metric m _n-1
When (S3) is larger than metric m _n-1 (S2) and metric m _n-1 (S0) is larger than metric m _n-1 (S5), metric (S5) is set to metric m _n-1 (S4).
+ Y _n , metric m _n (S4) to metric m _n-1
(S3) + y _n, the metric m _n (S3) the metric _{m n-1 (S2) -y} n, the metric m _n a (S2) metric _{m n-1 (S1) -y} n, the metric m _n (S1)
Metric m _n-1 (S0) -y _n , metric m _n
Let (S0) be the metric m _n-1 (S5) + y _n, and these transition patterns of the playback state are (the merge 0 to the merge 1) → (the merge 0 to the merge 1) → (the merge 0 Through merge 1) → (merge 0 through merge 1), the playback state S3 changes to (merge 0 through merge 2) → (merge 0 through merge 2) → merge 2 → ( When the transition is made from the merge 0 to the merge 2) → (the merge 0 to the merge 2), Perth merges into the playback state S0, the playback state up to that point is determined, and then the playback states S0, S1, Output data is calculated by setting output "0" for S2, S3, S5 and output "1" for the reproduction states S1, S2.

[0027]

According to the reproduction data detecting method of the present invention, the data bit is converted into the channel bit while the continuous non-code inversion bit on the recording side is suppressed within the range of 3 at minimum, and the reproduction is performed in comparison with the code conversion method of recording. The reproduced signal is converted into a binary signal by utilizing the correlation between the codes that the continuous non-sign inversion bit is 3 on the side, and after the level is judged, the reproduced state is changed to S.
There are 6 states of 0, S1, S2, S3, S4, S5, the input level in each state is limited to a certain range, and when there is an input that violates the rule of this state transition, the state of the violation is detected, Bit error correction can be performed by determining the original state, and the error rate for random errors can be improved. Also, S3 and S2, S0 and S5
It is possible to realize a circuit that determines merge depending on the magnitude of the value, determines pass merge of S3 to S0, and obtains output data depending on the state after that. By doing so, bit error correction is performed, and the bit error rate for random errors is increased. It has the effect that it can be improved.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a state transition diagram of an embodiment of the present invention, and FIG. 2 is a trellis diagram in the state transition shown in FIG.

In FIG. 1 and FIG. 2, in the present embodiment, the reproduction states are S0, S1, S2, S3, S4, and S5, and when -1 is input at S0, the process proceeds to S0 and the output data 0 Then, when 1 is input at S0, it shifts to S1 and the output data is 1. When 1 is input at S1, it shifts to S2 and the output data is 0. When 1 is input at S2, it shifts to S3 and the output data is 0, when -1 is input in S3, it goes to S4 and output data is 1, when 1 is input in S3, it goes to S3 and output data is 0, and when -1 is input in S4, it goes to S5 When output data is 0 and -1 is input in S5, S0
When there is an input that violates this state transition rule and changes the output data to 0, the state of the violation is detected and the bit error correction is performed by judging the original state. Improve the rate.

A normalized metric is obtained by using the method of deriving the equations described in FIGS. 5 to 10.

Normalized metrics 1 ₀₀ , 1 ₀₁ , 1 ₁₂ ,
1 ₂₃ , 1 ₃₃ , 1 ₃₄ , 1 ₄₅ , and 1 ₅₀ are: 1 ₀₀ = y _n 1 ₀₁ = y _n 1 ₁₂ = -y _n 1 ₂₃ =
-Y _n 1 ₃₃ = -y _n 1 ₃₄ = y _n 1 ₄₅ = y _n 1 ₅₀ =
y _n .

Here, at time n, the sampled value is yn,
The standardized metric for the states S3, S2, S1, S0 is m
_{If n} (S5) to (S0), then m _n (S5) = m _n-1 (S4) +1 ₄₅ = m _n-1 (S4) + y _n m _n (S4) = m _n-1 (S3) +1 ₃₄ = m _n-1 (S3) + y _n m _n (S3) = min [m _n-1 (S3) +1 ₃₃ , m _n-1 (S2) +1 ₂₃ ] min [m _n-1 (S3) -y _{n, m n-1 (S2} ) -y n] m n (S2) = m n-1 (S1) +1 12 = m n-1 (S1) -y n m n (S1) = m n-1 ( S0) +1 ₀₁ = m _n-1 (S0) -y _n m _n (S0) = min [m _n-1 (S0) +1 ₀₀ , m _n-1 (S5) +1 ₅₀ ] = min [m _n-1 (S0) + y _n , m _n-1 (S5) + y _n ], and the above equation can be expanded as follows.

[0034]

[0035]

[0036]

[0037]

When the reproduction data is y and -1≤y≤1, merging is determined from the input data.

As a merge 0, the metric m _n-1 (S
When 3) is smaller than metric m _n-1 (S2) and metric m _n-1 (S0) is smaller than metric m _n-1 (S5), metric m _n (S5) is metric m _n-1 (S4).
+ Y _n , metric m _n-1 (S4) is converted to metric m _n-1
(S3) + y _n, the metric m _n (S3) the metric _{m n-1 (S3) -y} n, the metric m _n a (S2) metric _{m n-1 (S1) -y} n, the metric m _n (S1)
Metric m _n-1 (S0) -y _n , metric m _n
(S0) is set as metric m _n-1 (S0) + y _n, and merge 1 is set as metric m _n-1 (S3).
_{When the} metric m _n-1 (S0) smaller than _n-1 (S2) is larger than the metric m _n-1 (S5), the metric m _n
(S5) is a metric m _n-1 (S4) + y _n , and metric m _n-1 (S4) is a metric m _n-1 (S3) + y _n ,
The metric m _n (S3) is converted to the metric m _n-1 (S3)-
y _n , metric m _n (S2) is converted to metric m _n-1 (S
1) -y _n , metric m _n (S1) to metric m
_{Let n-1} (S0) -y _n and metric m _n (S0) be metric m _n-1 (S0) + y _n, and as merging 2, metric m _n-1 (S3) is metric m _n-1 (S2). The larger metric m _n-1 (S0) is the metric m _n-1
When smaller than (S5), metric m _n (S5) is metric m _n-1 (S4) + y _n , metric m _n (S4) is metric m _n-1 (S3) + y _n , metric m _n (S
3) is a metric m _n-1 (S2) -y _n , a metric m
_n (S2) is the metric m _n-1 (S1) -y _n , metric m _n (S1) is the metric m _n-1 (S0) -y _n ,
The metric m _n (S0) is converted to the metric m _n-1 (S0) +
y _n, and merging 3, metric m _n-1 (S3)
Is larger than the metric m _n-1 (S2), the metric m _n-
When 1 (S0) is larger than metric m _n-1 (S5), metric m _n (S5) is metric m _n-1 (S4) + y
_n , metric m _n (S4) is converted to metric m _n-1 (S
3) + y _n , metric m _n (S3) is converted to metric m
_{n-1 (S2) -y n} , the metric m _n a (S2) metric _{m n-1 (S1) -y} n, the metric m _n a (S1) metric _{m n-1 (S0) -y} n, the metric m _n (S
0) as a metric m _n-1 (S0) + y _n, and then
When either of the following occurs, the paths are merged and the corresponding output sequence is obtained.

FIG. 3 is a diagram showing an example of path merging in this embodiment.

In FIG. 3, three consecutive states are (merge 0 to merge 1) → (merge 0 to merge 1)
→ merge 1 → (merge 0 or merge 1) → (merge 0
Or merge 1), the path is merged into S3.

Three consecutive states are (merge 0 or merge 2) → (merge 0 or merge 2) → merge 2 →
When (merge 0 or merge 2) → (merge 0 or merge 2), the path is merged with S0.

The states are obtained by merging the paths, and the output data is obtained. That is, the states S0, S2, S
By setting the output 0 to 3 and S5 and setting the output 1 to states S1 and S4, output data can be obtained and bit error correction for a random error can be performed.

FIG. 4 is a block diagram showing a reproduction data detecting circuit to which an embodiment of the present invention is applied.

The reproduced data detection circuit of the present application will enter the y _n, y _n, condition calculating circuit 1 calculates the -y _n and y _n,
-Y _n is input, m _n (S1) to m _n (S5) are calculated, and m _n-1 (S1) and m _n-1 (S2), 0 and m _n-1 (S
5), the normalization metric operation circuit / merge determination circuit 2 that determines the merger 0 to merge 3 and merge 0, 2 → 0, 2 → 2 → 0, 2 → 0, 2 or merge 0,
The path merge determination circuit 3 that detects a sequence of 1 → 0, 1 → 1 → 0, 1 → 0, 1 and determines S3 merge from S0 merge and the backward trace data from S0 merge and S3 merge are determined. The path memory circuit 4 of FIG.

Next, the operation of the reproduction data detection circuit of this application example will be described.

The input signal y _n is input to the conditional operation circuit 1. Here, y _n is 4-bit A / D converted, and y _n , −
Calculate y _n .

Next, it is input to the normalized metric operation circuit 2. Here, merge 0 of the previous sample from y _n , -y _n ,
According to the results of merge 1, merge 2, and merge 3, m _n (S
1) to _mn (S3) are calculated.

Further, it is input to the merge determination circuit 2. Here, m _n-1 (S3) and m _n-1 (S2), m _n-1 (S0) and m _n-1 (S5) are judged to be larger or smaller, and m _n-1 (S3) <m _{n- 1} (S2) and m _n-1 (S0)
<M _n-1 (S5) and merge 0, m _n-1 (S3) <m _n-1 (S2) and m _n-1 (S0)
When ≧ m _n-1 (S5) and merge 1, _mn-1 (S3) ≧ m _n-1 (S2) and m _n-1 (S0)
<M _n-1 (S5) and merge 2; m _n-1 (S3) ≧ m _n-1 (S2) and m _n-1 (S0)
When ≧ m _n−1 (S5), the merge 3 is determined. here,
Since the relative value of m _n is important, m _n (S0) = 0
And m _n (S1) to mn (S3) are respectively m _n
The relative value with (S0) is calculated.

Then, it is input to the path merge determination circuit 3. This is: (Merge 0, 1) → (Merge 0, 1) → Merge 1 →
When (merge 0, 1) → (merge 0, 1) appears,
S3 merge, and (merge 0, 2) → (merge 0, 2) → merge 2 →
When (merge 0, 2) → (merge 0, 2) appears,
S0 merge.

Finally, the merge information and the path merge information are input to the bus memory circuit 4. Here, the paths are arranged in order, a bus merge is detected, and the paths are traced back to the past.
The maximum likelihood path is searched to detect how the states S0 to S5 transit, and output data "1", S0,
Output data “0” is set for S2, S3, and S5.

As an example, merging 1 → 2 → 0 → 2 → 3 → 1 → 0 → 1 → 1 → 0 in order from time 1 in FIG. 3, and merge 1 → 0 → from time 6 to time 10.
Since 1 → 1 → 0, it is merged into S3 at time 6, and the output data becomes “0”. When the path is traced back from here, at time 5, merge S2, output data “0”,
Merge S1 and output data “1” at time 4, merge S0 and output data “0” at time 3, merge S at time 2
0, output data “0”, merge S5 at time 1, output data “0”.

[0053]

As described above, according to the present invention, the data bit has at least 3 consecutive non-sign inversion bits on the recording side.
In contrast to the code conversion method of converting to channel bits while suppressing the value within the range of, and reproducing, the reproduced signal is converted into a binary signal by utilizing the correlation between the codes that the number of consecutive non-code inversion bits on the reproducing side is 3 at minimum. After converting and judging the level, the playback state is set to 6 states of S0, S1, S2, S3, S4, S5, the input data in each state is limited to a certain range, and the input that violates the rule of this state transition is input. In this case, there is an effect that the bit error correction is performed by detecting the state of the violation and determining the original state, and the error rate for the random error can be improved. Also S3
And the value of S2, S0 and S5 determines the merge,
It is possible to realize a circuit that determines the path merge of S3 to S0 and obtains the output data, thereby performing the bit error correction and improving the error rate with respect to the random error.

[Brief description of drawings]

FIG. 1 is a state transition diagram of an embodiment of the present invention.

FIG. 2 is a trellis diagram in the state transition shown in FIG.

FIG. 3 is a diagram showing an example of path merging according to the present embodiment.

FIG. 4 is a block diagram showing a reproduction data detection circuit to which an embodiment of the present invention is applied.

FIG. 5 is a block diagram showing an example of a conventional reproduction data detection method based on a partial response (PR) (1,1) + Viterbi decoding method.

6 is a diagram showing the timing of the conventional reproduction data detection method shown in FIG.

7 is a state transition diagram of the conventional reproduction data detection method shown in FIG.

FIG. 8 is a trellis diagram in the state transition shown in FIG.

9 is a diagram showing a probability of reproducing data in the state transition shown in FIG.

10 is a diagram showing an example of a path merge after the state transition shown in FIG.

[Explanation of symbols]

1 Conditional Calculation Circuit 2 Normalized Metric Calculation Circuit / Merge Judgment Circuit 3 Path Merge Judgment Circuit 4 Path Memory Circuit 11 Precoder 12 Recording / Playback Section 13 Partial Response (PR) (1, 1) Equalizer 14 High Frequency Filter ( HPF) 15 Viterbi decoder

Claims (2)

[Claims] 1. A code conversion method in which data bits are converted into channel bits while suppressing consecutive non-sign inversion bits on the storage side within a range of at least 3 and recorded, and inter-code correlation is used on the reproduction side for a code conversion method. The reproduced signal is converted into a binary value by detecting the partial response (1) to (1,1) and the level is determined, and then the reproduced state is changed to S0, S1, S2, S3, S.
4, when S-1 is input, transition to S0 and output data is 0, and when S0 is 1, transition to S1 is performed and output data is 1.
When 1 is input to 1 the output data changes to S2 and 0, when 1 is input to S2 the output data changes to S3 and 0 when the input data is 1 and when -1 is input to S3 the output data changes to S4. Then, the output data is set to 1, and when 1 is input in S3, the process proceeds to S3 and the output data is set to 0, and -1 is input in S4.
When inputting, the output data is 0 and the output data is 0. When inputting -1 in S5, the output data is 0 and the output data is 0. The most probable state transition is estimated according to the rule of the state transition, A reproduction data detection method characterized by performing re-bit error correction for reproduction signal detection by determining a trellis diagram. 2. The input data is y _n, and −1 ≦ y _n ≦ 1.
And the reproduction state is S0, S1, S2, S
There are 6 states of S3, S4 and S5, and the reciprocal of the probability that takes one of these states is called a metric, and the metric m _n-1 (S3) is the metric m _n-1 (S
2) When the metric m _n-1 (S0) is smaller than the metric m _n-1 (S5) and the metric m _n (S5) is the metric m _n-1 (S4) + y _n , the metric m _n (S5)
4) is melonic m _n-1 (S3) + y _n , metric m
_n (S3) is a metric m _n-1 (S3) -y _n , metric m _n (S2) is a metric m _n-1 (S1) -y _n ,
The metric m _n (S1) is converted to the metric m _n-1 (S0)-
y _n and metric m _n (S0) are converted to metric m _n-1 (S
0) + y _n, and as merge 1, the metric m _n-1 (S3) is smaller than the metric m _n-1 (S2) and the metric m _n-1 (S0).
Is larger than metric m _n-1 (S5), metric m
_n (S5) is the metric m _n-1 (S4) + y _n , metric m _n (S4) is the metric m _n-1 (S3) + y _n ,
The metric m _n-1 (S3) is converted to the metric m _n-1 (S3)
-Y _n , metric m _n (S2) is metric m _n-1
(S1) -y and _n, the metric m _n a (S1) metric _{m n-1 (S0) -y} n, the metric m _n a (S0) and the metric _{m n-1 (S5) +} y n, as the merge 2, metric m _n-1 (S3) is larger than metric m _n-1 (S2), and metric m _n-1 (S0)
Is smaller than metric m _n-1 (S5), metric m
_n (S5) is the metric m _n-1 (S4) + y _n , metric m _n (S4) is the metric m _n-1 (S3) + y _n ,
The metric m _n (S3) is converted to the metric m _n-1 (S2)-
y _n , metric m _n (S2) is converted to metric m _n-1 (S
1) -y _n , metric m _n (S1) to metric m
_n-1 (S0) -y _n , metric m _n (S0) are set as metric m _n-1 (S0) + y _n, and as merge 3, metric m _n-1 (S3) is set as metric m _n-1 (S2). Greater metric m _n-1 (S0)
Is larger than metric m _n-1 (S5), metric (S5) is metric m _n-1 (S4) + y _n , metric m _n (S4) is metric m _n-1 (S3) + y _n , metric m _n ( S3) is a metric m _n-1 (S2) -y _n
, Metric m _n (S2) to metric m _n-1 (S
1) -y _n , metric m _n (S1) to metric m
_{Let n−1} (S0) −y _n and metric m _n (S0) be metrics m _n−1 (S5) + y _n, and these transition patterns of the reproduction state are (merging 0 to merging 1) → ( When the transition is made from the merge 0 to the merge 1) → (the merge 0 to the merge 1) → (the merge 0 to the merge 1), the playback state S3 becomes (the merge 0 to the merge 2) →
(Merge 0 to Merge 2) → Merge 2 →
(Merge 0 to Merge 2) → (Merge 0
Through the merge 2), Perth merges with the playback state S0, and the playback state up to that point is determined,
Thereafter, the output data is calculated by setting the output "0" for the reproduction states S0, S1, S2, S3, S5 and the output "1" for the reproduction states S1, S2. The reproduction data detection method according to claim 1.