JPH06121236A - Defect correction device for ccd camera - Google Patents

Abstract

PURPOSE:To surely correct a defect picture element and proximity defect picture elements close to the defect picture element with a simple circuit configuration by reading various data other than the proximity defect picture elements from a ROM and reading various data for proximity defect picture elements from a RAM and correcting all defect picture elements with both the data. CONSTITUTION:This device is provided with a ROM 15 storing various data, for defect picture element correction, a RAM 16 storing various data for proximity defect picture element correction, address counters 34, 35 applying address data to the ROM, RAM, a mode select circuit 19 controlling the selection of various data other than proximity defect picture elements from the ROM 16 or various data for proximity defect picture elements from the RAM 16, strobe circuits 17, 18, switches 20, 21, 22, a latch circuit 23 obtaining a correction signal based on selected various data, a D/A converter 24, a decoder 25, flip-flop circuits 26, 27, 28 and a switch 29.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to, for example, a CCD device.
The present invention relates to a defect correction device for a CCD camera, which is suitable for application to a single-chip type video camera using three sheets and a multiple-plate type video camera using three CCD elements.

[0002]

2. Description of the Related Art For example, in a video camera using a CCD element, it is obtained by picking up an image by a so-called defective pixel which outputs a signal of a specific level in a state where no light is incident on each pixel of the CCD element There was a problem that the image quality deteriorates.

Therefore, conventionally, a defect correction device for correcting an output signal of a defective pixel is mounted on a video camera, and before the video camera is shipped to a user, which pixel is defective in the CCD element of the video camera. If the pixel is inspected, the correction data corresponding to the defective pixel obtained as a result of the inspection is stored in the storage area of the defect correction device of the video camera, and when used, the output by the defective pixel is corrected by the correction data. By doing so, after the signal actually reaches the user's hand, the signal output by the defective pixel is corrected by the correction device by the defect correction device, and it is possible to obtain image data of good image quality. ing.

As a defect correction device for such a CCD camera, for example, one shown in FIG. 6 has been proposed.

A conventional defect correcting device for a CCD camera will be described below with reference to FIG.

In FIG. 6, reference numeral 1 is a ROM.
As shown in FIG. 1, the storage area 1a stores output timing data, the storage area 1b stores color code data 1b, and the storage area 1c stores correction data. These data are manually or automatically obtained by inspection in advance and stored.

The output timing data of the storage area 1a of the ROM 1 is read by supplying read address data from the address counter 3. The output timing data output from the ROM 1 by reading is supplied to the strobe generating circuit 2, and the strobe signal for determining the correction timing from the strobe generating circuit 2 is supplied to the decoder.

On the other hand, a color code (data indicating which of R, G and B pixels) is read from the storage area 1b and supplied to the decoder 4. The decoder 4 responds to the gate pulse for turning on or off the analog switch 10 described later on R, G, B based on the strobe signal from the strobe generating circuit 2 and the color code data read from the storage area 1b of the ROM 1. This gate pulse is supplied to the analog switch 10 via flip-flop circuits 5, 6 and 7 for absorbing a delay amount for correction on the main line (not shown).

In parallel with this, the storage area 1c of the ROM 1
Correction data is read out, and the gain control circuit 8 reads D
-A converter 9 is supplied. The correction data supplied to the DA converter 9 is converted into an analog signal here and then supplied to the analog switch 10.

The analog switch 10 corrects the analog CCD correction signal from the DA converter 9 based on the gate pulse supplied from the decoder 4 through the flip-flop circuits 5, 6 and 7. To the output terminal 11 for correcting the G CCD element or the output terminal 13 for correcting the B CCD element.

From this analog switch 10 to the output terminal 1
The correction signal output from 1, 12, or 13 is used, for example, in a video camera main body circuit (not shown) to correct the captured video signal.

As described above, conventionally, the correction data is previously stored in the ROM 1 in advance, and when the video camera is used, the correction data stored in the ROM 1 causes A so-called defective pixel which outputs a signal of a peculiar level is corrected to obtain a good image.

[0013]

By the way, in the above description, since the correction data for correcting the defective pixel is sequentially read from the ROM and used, the correction speed depends on the access speed of the ROM.

Therefore, when a defective pixel exists in the vicinity of an arbitrary defective pixel, that is, when a plurality of defective pixels exist in close proximity, the output data from one defective pixel cannot be corrected and the image pickup is performed. There is an inconvenience that the image quality of the obtained image deteriorates.

The present invention has been made in view of the above point, and even if a plurality of defective pixels are present close to each other with a simple circuit configuration, the defective pixels can be surely corrected, and an image is obtained by this. An object of the present invention is to propose a defect correction device for a CCD camera that can prevent deterioration of image quality and obtain a good image.

[0016]

According to the present invention, among pixels of a CCD element, first correction data corresponding to a defective pixel, second correction data corresponding to a defective pixel adjacent to the defective pixel,
Also, a first storage means 15 for storing control data corresponding to the first and second correction data, and a second storage means 16 for storing the second correction data.
Address generating means 33, 34, 35, 36 for supplying read or write address data to the first and second storage means 15, 16 and the first storage means 1.
5, the first correction data and control data read from
And the first correction data read from the first storage means 15 based on the second correction data read from the second storage means 16, or the first correction data read from the second storage means 16. Selection control means 17 for selecting the correction data of 2;
18, 19, 20, 21, 22 and selection control means 17,
First selected by 18, 19, 20, 21, 22
Alternatively, correction means 23, 24, 25, 26, 27, 2 for obtaining a signal for correcting the CCD element based on the second correction data.
8 and 29.

Further, in the present invention described above, the second storage means 16 is faster than the access speed of the first storage means 15.

Further, in the above-mentioned invention, the first storage means 15 is a ROM and the second storage means 16 is a RAM.

Further, according to the present invention, in the above description, the address generating means 33, 34, 35 and 36 are provided for the first counter 34 for generating the read and write address data corresponding to the defective pixel and the defective pixel adjacent to the defective pixel. A second counter 35 for generating corresponding read and write address data, and a timing generating means 33 for supplying a timing signal to the first and second counters 34, 35,
Selection means 3 for selecting address data from the first and second counters 34, 35 and supplying it to the first storage means 15.
6 and 6.

Further, according to the present invention, in the above description, the first correction data stored in the first storage means 15 is composed of at least correction data, relative address data and color code data, and is stored in the second storage means 16. The second correction data is composed of at least correction data, relative address data, and color code data.

Further, according to the present invention, in the above description, the selection control means 17, 18, 19, 20, 21, 22 corrects the defective pixel based on the first correction data read from the first storage means 15. And a first control means 17 for generating a control signal for advancing the read or write address data generated by the address generation means 33, 34, 35, 36, and a second memory. The second gate pulse for correcting the defective pixel based on the second correction data read from the means 16 and the read or write address data generated by the address generating means 33, 34, 35, 36 are stepped. Second control means 18 for generating a control signal for controlling the relative address data and control in the first correction data read from the first storage means 15. Data, and second storage means 16
Selection of the first or second gate pulse output by the first and second control means 17 and 18 based on the relative address data in the second correction data read from the first correction means and the first storage means. The color code data in the first correction data from 15 or the color code in the second correction data from the second storage means 16 is selected, and the steps in the address generating means 33, 34, 35, 36 are performed. And a third control means 19 for controlling the.

Further, the present invention is based on the above, and the correction means
3, 24, 25, 26, 27, 28, 29 are correction data in the first correction data from the first storage means 15 or correction data in the second correction data from the second storage means 16. To conversion signals for correcting defective pixels of the CCD element, and selection control means 17, 18, 1
A control signal generating means 25 for generating a control signal for selecting a CCD element based on the first or second gate pulse and color code data from 9, 20, 21, 22 and the control signal generating means 25. It comprises switch means 26, 27, 28, 29 for allocating the correction signals from the converting means 23, 24 to the corresponding CCD elements based on the control signals.

[0023]

According to the structure of the present invention, the first correction data corresponding to the defective pixel among the pixels of the CCD element, the second correction data corresponding to the defective pixel adjacent to the defective pixel, and the first and the second correction data. The control data corresponding to the second correction data are stored in the first storage unit 15, the second correction data is stored in the second storage unit 16, and the first and second storage units 15 and 16 are stored. On the other hand, read or write address data is supplied to the address generating means 33, 34, 35, 36.
The first correction data and the control data supplied from the first storage means 15 and the second storage means 16
Selection control of the first correction data read from the first storage means 15 or the second correction data read from the second storage means 16 based on the second correction data read from Selection by means 17, 18, 19, 20, 21, 22 and selection control means 17, 18, 19, 20, 21, 2
Based on the first or second correction data selected by 2, the correction signals of the CCD element are corrected by the correction means 23, 24,
Get at 25, 26, 27, 28, 29.

Further in the above, according to the configuration of the present invention,
Of the pixels of the CCD element, the first correction data corresponding to the defective pixel, the second correction data corresponding to the defective pixel adjacent to the defective pixel, and the control data corresponding to these first and second correction data are provided. Each is stored in the first storage means 15, and the second correction data is stored in the second storage means 16 having an access speed faster than that of the first storage means 15.

Further in the above, according to the configuration of the present invention,
Of the pixels of the CCD element, the first correction data corresponding to the defective pixel, the second correction data corresponding to the defective pixel adjacent to the defective pixel, and the control data corresponding to the first and second correction data are provided. Each of them is stored in the ROM as the first storage means 15, and the second correction data is stored in the second storage means 1.
6 is stored in the RAM.

Further in the above, according to the configuration of the present invention,
The first counter 34 constituting the address generation means 33, 34, 35, 36 generates read and write address data corresponding to the defective pixel, and the second counter 35.
To generate read and write address data corresponding to the defective pixel adjacent to the defective pixel, supply the address data to the first and second counters 34 and 35 by the timing generation means 33, and select the first and first address data by the selection means 36. The address data from the second counters 34 and 35 is selected, and the selected address data is supplied to the first storage means 15.

Further in the above, according to the configuration of the present invention,
The first storage means 15 stores at least the correction data as the first correction data, the relative address data and the color code data, and the second storage means 16 stores at least the second correction data.
The correction data as the correction data, the relative address data, and the color code data are stored.

Further in the above, according to the configuration of the present invention,
For correcting defective pixels on the basis of the first correction data read from the first storage unit 15 by the first control unit 17 constituting the selection control units 17, 18, 19, 20, 21, and 22. A control signal for advancing the first gate pulse and the read or write address data generated by the address generation means 33, 34, 35, 36 is generated, and the second control means 18 generates the second storage means 16. A second gate pulse for correcting a defective pixel based on the second correction data read from the address correction means 3
First correction data read out from the first storage means 15 by the third control means 19 by generating a control signal for advancing the read or write address data generated by 3, 34, 35, 36. Based on the relative address data and control data therein and the relative address data in the second correction data read from the second storage means 16, the first and second control means 17 and 18 respectively output the The selection of the first or second gate pulse and the selection of the color code data in the first correction data from the first storage means 15 or the color code in the second correction data from the second storage means 16. Address generating means 3
Control the steps at 3, 34, 35, 36.

Further, according to the structure of the present invention described above,
In the conversion means 23, 24 constituting the correction means 23, 24, 25, 26, 27, 28, 29, the correction data in the first correction data from the first storage means 15 or from the second storage means 16 is obtained. CCD correction data in the second correction data
The signal is converted into a signal for correcting the defective pixel of the device, and the control signal generation means 25 selects the selection control means 17, 18, 19, 20, 2.
A control signal for selecting a CCD element is generated on the basis of the first or second gate pulse from 1 or 22 and the color code data. Based on the control signal from the control signal generation means 25 by the switch means 28 or 29. Conversion means 23, 2
The correction signal from 4 is assigned to the corresponding CCD element.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the defect correcting device for a CCD camera of the present invention will be described in detail below with reference to FIG.

In FIG. 1, 15 is a ROM (PRO
M, EEPROM, one-time ROM, etc.)
In the storage area of M15, various correction data obtained by mounting on a video camera (not shown) or by manual or automatic inspection by a separate inspection device are stored in advance.

FIG. 2 shows the various correction data.
2 will be described with reference to FIG.
The storage area 15 stores various data corresponding to the defective pixel and the adjacent defective pixel adjacent to the defective pixel.

That is, as shown in FIG. 2, the correction data corresponding to each adjacent defective pixel is stored in the storage area a1 of the area 15a of the adjacent defective pixel adjacent to the defective pixel, and the storage area a2 of this area 15a is stored. The relative address data corresponding to each proximity defective pixel is stored in
The correction data corresponding to each proximity defective pixel is stored in the storage area a3 of the area 15a.

Then, the correction data corresponding to each defective pixel is stored in the storage area b1 of the defective pixel area 15b, and the relative address data corresponding to each defective pixel is stored in the storage area b2 of this area 15b. Then, the color code corresponding to each defective pixel is stored in the storage area b3 of the defective pixel area 15b, and the mode select data corresponding to each defective pixel is stored in the storage area b4 of this area 15b. Although illustration of the gain control data for performing the gain control of the correction data and the gain control circuit for performing the gain control by this data is omitted, in the case where the gain control circuit is included, the gain control data D
-It will be arranged in front of the A converter 24.

For example, as shown in FIG. 4, the color code data is set to "0" when only the pixel of the channel R (channel of the CCD for red) is a defective pixel, and the channel G
If only the pixel of (green CCD channel) is a defective pixel, it is set to "1", and if the pixel of channel B (blue CCD channel) is only a defective pixel, it is set to "2". Is a defective pixel, "3", the pixels of channels R and B are "4", the pixels of channels G and B are "5", and the channels of channels R, G and When all the B pixels are defective pixels, "6" is set so that the decoder 25, which will be described later, can select a channel to be corrected by this color code data.

The defective pixel and the adjacent defective pixel adjacent to the defective pixel in this example will be described below.

That is, for example, as shown in FIG. 3, a defective pixel within 13 clocks from an arbitrary defective pixel f1 is set as a proximity defective pixel. Of course, the standard of 13 clocks or less is determined by the access time of the RAM 16 described later.

When the defective pixel within 13 clocks is set as the adjacent defective pixel, in FIG.
The defective pixel at the position after 2 to 5 clocks is the adjacent point n
The defective pixel at 1 or the adjacent defective pixel and located 11 clocks after the defective pixel f3 is set as the adjacent point n2, that is, the adjacent defective pixel.

The above-mentioned relative address data is
The number of clocks from a defective pixel serving as a reference to the next defective pixel, and in this example, 5 and 11 are relative address data.

Referring again to FIG. 1, reference numeral 33 is a timing generating circuit, which is based on a reference horizontal synchronizing signal and a reference vertical synchronizing signal supplied from, for example, a main circuit of a video camera (not shown) via input terminals 33h and 33v. And generates a clock pulse for counting. This clock pulse is an address counter 3 corresponding to a defective pixel serving as a reference
4 and the address counter 35 corresponding to the proximity defective pixel.

The address data output from the address counters 34 and 35 is supplied to the selector 36. The selector 36 selects the address data from the address counter 35 when the reference vertical synchronizing signal from the input terminal 33v is low level "0", and selects the address data from the address counter 34 when the reference vertical synchronizing signal is high level "1".
Select address data from.

That is, when the reference vertical synchronizing signal is at the low level "0" (vertical blanking period), the address data corresponding to the adjacent defective pixel is R via the selector 36.
It is supplied to the OM15, whereby the above-mentioned correction data corresponding to the proximity defective pixel is read from the ROM15,
It is supplied to the RAM 16 and stored in the RAM 16.

On the other hand, when the reference vertical synchronizing signal is at the high level "1", the address data corresponding to the reference defective pixel is supplied to the ROM 15 via the selector 36, whereby the reference defect stored in the ROM 15 is stored. The correction data corresponding to the pixel, the relative address data, the color code, and the mode select data are read.

The correction data read from the ROM 15 is supplied to the fixed contact 20b of the switch 20, and the ROM 15
Relative address data read from is supplied to the strobe generation circuit 17 and the mode selection circuit 17, respectively.
The color code data read from the ROM 15 is supplied to the fixed contact 22b of the switch 22, and the mode select data read from the ROM 15 is supplied to the mode select circuit 19, respectively.

When the reference vertical synchronizing signal is at the high level "1", the address data from the address counter 35 is supplied to the RAM 16, which causes RA.
The correction data, relative address data, and color code data corresponding to the proximity defective pixel written when the reference vertical synchronizing signal is at the low level "0" are read from M16.

The correction data corresponding to the proximity defective pixel read from the RAM 16 is the fixed contact 20a of the switch 20.
Is supplied to the strobe generating circuit 1 and the relative address data corresponding to the proximity defective pixel read from the RAM 16 is supplied to the strobe generating circuit 1.
8 and the mode selection circuit 19 respectively, and the RAM
The color code data corresponding to the proximity defective pixels read from 16 are supplied to the fixed contacts 22a of the switch 22, respectively.

The strobe generating circuit 17 obtains a gate pulse for a point for correcting a defective pixel serving as a reference other than the adjacent defective pixel on the basis of the relative address data supplied from the ROM 15, and the gate pulse is switched by the switch 21.
Is supplied to the fixed contact 21b, and a control signal for incrementing the address counter 34 is obtained, and the control signal is supplied to the address counter 34.

Similarly, the strobe generating circuit 18 is
Based on the relative address data supplied from M16, a gate pulse for the point at which the proximity defective pixel is corrected is obtained, and this gate pulse is supplied to the fixed contact 21 of the switch 21.
At the same time, the control signal for incrementing the address counter 35 is obtained and the control signal is supplied to the address counter 35.

The mode select circuit 19 obtains a switching pulse for switching the switches 20, 21 and 22 based on the mode select data and the relative address data from the ROM 15 and the relative address data corresponding to the proximity defective pixel from the RAM 16. , This switching pulse is supplied to the switches 20, 21 and 22, respectively.

Therefore, by the switching pulse, the movable contacts 20c, 21c of the switches 20, 21 and 22 are moved.
And 22c are respectively connected to the fixed contacts 20b, 21b and 22b, the ROM 1 is connected via the switch 20.
5 is supplied to the latch circuit 23, the gate pulse from the strobe generating circuit 17 is supplied to the decoder 25 via the switch 21, and the color code data from the ROM 15 is supplied to the decoder 25 via the switch 22.
Are supplied to each.

On the other hand, when the movable contacts 20c, 21c and 22c of the switches 20, 21 and 22 are respectively connected to the fixed contacts 20a, 21a and 22a by the switching pulse, the RAM 16 is connected via the switch 20.
The correction data corresponding to the proximity defective pixel from is supplied to the latch circuit 23, the gate pulse from the strobe generating circuit 18 is supplied to the decoder 25 via the switch 21, and the proximity defective pixel from the RAM 16 is supplied to the decoder 25 via the switch 22. Corresponding color code data is supplied to the decoder 25, respectively.

The decoder 25 outputs R, G and B signals based on the gate pulse supplied from the strobe generating circuit 17 or 18 via the switch 21 and the color code data supplied from the ROM 15 or RAM 16 via the switch 22. The corresponding three control data are obtained, and these three control data are respectively fed to the flip-flop circuit 2
Supply to switch 29 via 6, 27 and 28.

On the other hand, the latch circuit 23 supplies the correction data corresponding to the reference defective pixel or the correction data corresponding to the adjacent defective pixel supplied from the ROM 15 or the RAM 16 via the switch 20 to the DA converter 24.

The DA converter 24 converts the correction data corresponding to the defective pixel serving as the reference or the correction data corresponding to the adjacent defective pixel supplied from the latch circuit 23 into an analog signal, and then supplies the analog signal to the switch 29.

Therefore, in the switch 29, the correction data from the D / A converter 24 is supplied to the R, G and B based on the control data supplied from the decoder 25 via the flip-flop circuits 26, 27 and 28. Output terminal 3
Supply to 0, 31 and 32.

A defective pixel serving as a reference among the image signals output from the video camera by the correction signal is supplied as a correction signal to the main circuit of the video camera (not shown) through these output terminals 30, 31 and 32. Further, when the signal portion corresponding to the adjacent defective pixel close to the defective pixel is corrected and is output as a good image signal by this and displayed on a monitor television or the like, an extremely good image can be obtained.

The above processing will be described below with reference to the timing chart of FIG. That is, as shown in FIG. 5A, among the pulses indicated by the high level “1”, the left pulse is the correction data corresponding to the reference defective pixel, and the right pulse is the proximity defective pixel close to the reference defective pixel. Assuming the correction data, as shown in FIG. 5B, the ROM
Since the correction data corresponding to the defective pixel serving as the reference is output from 15 and the correction data corresponding to the adjacent defective pixel adjacent to the defective pixel serving as the reference is output from the RAM 16 as shown in FIG. 5A, As a result, even if defective pixels are present close to each other, since the access speed of the RAM 16 is high, the correction can be performed reliably and accurately.

Thus, in this example, the ROM 15
The correction data corresponding to the defective pixel, the relative address data, the color code data, and the mode select data are stored in the RAM 16 having a high access speed during the period when the reference vertical synchronizing signal is at the low level “0”.
Of the various correction data corresponding to the 15 defective pixels, the correction data corresponding to the proximity defective pixel, the relative address data and the color code data are written, and the proximity defective pixel is read from the ROM 15 while the reference vertical synchronization signal is at the high level “1”. The correction data, relative address data, and color code data corresponding to defective pixels other than the above are read, and in parallel with this, the correction data, relative address data, and color code data corresponding to the proximity defective pixel are read from the RAM 16. Therefore, it is possible to surely correct the defective pixel and the adjacent defective pixel adjacent to the defective pixel. As a result, for example, two R pixels for the defective pixel and for the adjacent defective pixel are provided.
It is possible to obtain an image that has been subjected to favorable defective pixel correction processing with a simple circuit configuration without making the circuit configuration complicated and large in scale such as by providing an OM.

In the above example, a three-plate type video camera has been described as an example, but the same effect can be obtained when applied to a single-plate type or two-plate type video camera, for example.

The above-described embodiment is an example of the present invention, and it goes without saying that various other configurations can be adopted without departing from the scope of the present invention.

[0061]

According to the present invention described above, the first correction data corresponding to the defective pixel among the pixels of the CCD element, the second correction data corresponding to the defective pixel adjacent to the defective pixel,
Further, control data corresponding to these first and second correction data are stored in the first storage means, respectively, and the second correction data are stored in the second storage means, and in the first and second storage means. On the other hand, read or write address data is supplied by the address generation means, and the first correction data and control data read from the first storage means and the second correction data read from the second storage means. First based on the data
The first correction data read from the storage means or the second correction data read from the second storage means is selected by the selection control means, and the first or second selection data is selected by the selection control means. Since the correcting means obtains the signal for correcting the CCD element based on the correction data of 1., it is possible to correct the defective pixel and the defective pixel close to the defective pixel, thereby obtaining an extremely good image. You can

Further in the above, according to the invention, a CCD
Among the pixels of the element, the first correction data corresponding to the defective pixel, the second correction data corresponding to the defective pixel adjacent to the defective pixel, and the control data corresponding to the first and second correction data are respectively provided. Since the second correction data is stored in the first storage means and the second correction data is stored in the second storage means having an access speed faster than that of the first storage means, in addition to the above-mentioned effect, the defective pixel and its proximity It is possible to surely correct the defective pixel, which results in good image quality,
A good image can be obtained.

Further in the above, according to the invention, a CCD
Among the pixels of the element, the first correction data corresponding to the defective pixel, the second correction data corresponding to the defective pixel adjacent to the defective pixel, and the control data corresponding to the first and second correction data are respectively provided. The second correction data is stored in the ROM as the first storage means, and the second correction data is stored in the R as the second storage means.
Since the data is stored in the AM, in addition to the above-described effect, the defective pixel and the defective pixel adjacent thereto can be surely corrected with a simple circuit configuration, thereby obtaining an image with good image quality. be able to.

Further, according to the present invention described above, read and write address data corresponding to the defective pixel is generated by the first counter constituting the address generating means,
The second counter generates read and write address data corresponding to the defective pixel adjacent to the defective pixel, the timing generating means supplies the address data to the first and second counters, and the selecting means performs the first and second. Since the address data from the counter is selected and the selected address data is supplied to the first storage means, in addition to the above effect, the defective pixel stored in the first storage means and the proximity of the defective pixel Various correction data corresponding to the defective pixel
Data can be output separately in two systems, which makes it possible to implement preprocessing for correcting defective pixels and defective pixels adjacent thereto with a simple circuit configuration.

Further, according to the present invention described above, at least the correction data as the first correction data, the relative address data and the color code data are stored in the first storage means, and at least the second storage means is stored in the second storage means. Since the correction data as the correction data, the relative address data, and the color code data are stored, the correction of the defective pixel and the defective pixel adjacent thereto can be surely performed in addition to the above-described effect.

Further, according to the present invention described above, the first control means constituting the selection control means corrects the defective pixel based on the first correction data read from the first storage means. The second correction data read out from the second storage means by the second control means for generating a control signal for advancing the gate pulse of 1 and the read or write address data generated by the address generation means. A second gate pulse for correcting the defective pixel and a control signal for advancing the read or write address data generated by the address generating means, and the third control means for storing the first memory. Relative address data and control data in the first correction data read from the means, and relative add in the second correction data read from the second storage means. Selection of the first or second gate pulse output by the first and second control means based on the color data, and the color code data or the second storage in the first correction data from the first storage means. While selecting the color code in the second correction data from the means,
Since the step in the address generating means is controlled, in addition to the above-mentioned effects, in addition to the above-mentioned effects, for example, even in a video camera using a plurality of CCD elements, correction of defective pixels and defective pixels adjacent thereto Can be done well.

Further in the above, according to the present invention, in the conversion means constituting the correction means, in the correction data in the first correction data from the first storage means or in the second correction data from the second storage means. Control data is converted into a signal for correcting a defective pixel of the CCD element, and the control signal generation means controls the CCD element selection based on the first or second gate pulse and the color code data from the selection control means. Since a signal is generated and the switch means allocates the correction signal from the conversion means to the corresponding CCD element based on the control signal from the control signal generation means, in addition to the above-mentioned effect, a simple circuit is provided. With the configuration, it is possible to correct a defective pixel of a video camera using a plurality of CCD elements and a defective pixel adjacent thereto.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a defect correction device for a CCD camera of the present invention.

FIG. 2 is a data configuration diagram showing storage data of a ROM used for explaining one embodiment.

FIG. 3 is an explanatory diagram for describing a defective pixel adjacent to a defective pixel used in the description of one embodiment.

FIG. 4 is an explanatory diagram showing an example of a color code used for describing one embodiment.

FIG. 5 is a timing chart used for explaining one embodiment.

FIG. 6 is a configuration diagram showing an example of a conventional defect correction device for a CCD camera.

[Explanation of symbols]

 15 ROM 16 RAM 17, 18 Strobe generating circuit 19 Mode select circuit 20, 21, 22 Switch 23 Latch circuit 24 A-D converter 25 Decoder 26, 27, 28 Flip-flop circuit 29 Switch 33 Timing generating circuit 34, 35 Address counter 36 Selector

Claims (7)

[Claims] 1. A first correction data corresponding to a defective pixel among pixels of a CCD element, a second correction data corresponding to a defective pixel adjacent to the defective pixel, and the first and second correction data. Corresponding to the first storage means for storing the respective control data, the second storage means for storing the second correction data, and read to the first and second storage means, Alternatively, address generation means for supplying write address data, the first correction data and the control data read from the first storage means, and the second correction data read from the second storage means. The first based on the correction data
Selection control means for selecting the first correction data read from the storage means or the second correction data read from the second storage means; and the selection control means selected by the selection control means. A defect correction device for a CCD camera, comprising: a correction unit that obtains a signal for correcting the CCD element based on the first or second correction data. 2. The defect correction device for a CCD camera according to claim 1, wherein the second storage means is faster than the access speed of the first storage means. 3. The defect correction device for a CCD camera according to claim 1, wherein the first storage means is a ROM and the second storage means is a RAM. 4. The address generating means generates a read / write address data corresponding to the defective pixel, and a read / write address data corresponding to a defective pixel adjacent to the defective pixel. A second counter, timing generating means for supplying a timing signal to the first and second counters, and address data from the first and second counters are selected and supplied to the first storage means. 2. The defect correction device for a CCD camera according to claim 1, further comprising a selection unit. 5. The second correction data stored in the first storage means is composed of at least correction data, relative address data and color code data, and is stored in the second storage means. 2. The CC according to claim 1, wherein the correction data of at least comprises correction data, relative address data and color code data.
Defect correction device for D camera. 6. The selection control means includes a first gate pulse for correcting the defective pixel based on the first correction data read from the first storage means, and the address generating means. Of the defective pixel based on the second correction data read from the second storage means, and first control means for generating a control signal for advancing the read or write address data Second gate pulse for correction, second control means for generating a control signal for advancing the read or write address data generated by the address generation means, and read from the first storage means The relative address data and the control data in the first corrected data, and the relative in the second corrected data read from the second storage means. Selection of the first or second gate pulse output by the first and second control means, respectively, based on address data, and the first storage means from the first storage means.
Third control means for selecting the color code data in the correction data or the color code in the second correction data from the second storage means and controlling the step in the address generating means. 6. The defect correction device for a CCD camera according to claim 5, further comprising: 7. The correction means includes the correction data in the first correction data from the first storage means or the second correction data from the second storage means.
Based on the first or second gate pulse and the color code data from the selection control means, the conversion means for converting the correction data in the correction data into the signal for correcting the defective pixel of the CCD element, Control signal generating means for generating a control signal for selecting a CCD element, and switch means for allocating a correction signal from the converting means to a corresponding CCD element based on the control signal from the control signal generating means. 7. The defect correction device for a CCD camera according to claim 6, wherein.