JPH06120836A - Multibit sigmadelta a/d converter - Google Patents

Abstract

PURPOSE:To provide a higher order multibit SIGMADELTA A/D converter which has the high accuracy and a wide band and can reduce the influence of the nonlinear error of a multibit A/D converter. CONSTITUTION:A multibit SIGMADELTA A/D converter consists of the primary SIGMADELTA A/D converters 50a and 50b which are cascaded together and a digital circuit 5a which calculates the digital output signals based on the outputs of both vonverters 50a and 50b. Then (N-1) pieces of primary SIGMADELTA A/D converters which are cascaded to (N-1) pieces of stages with an analog input signal inputted to the first stage are added together with a primary multibit SIGMADELTA A/D converter which is cascaded to the (N-1)-th stage. Then the circuit 5a calculates the digital output signals based on the outputs of the primary SIGMADELTA A/D converter and (N-1) pieces of primary SIGMADELTA A/D converters.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a .SIGMA..DELTA.A / D converter, and more particularly to a high precision, wide band multi-bit .SIGMA..DELTA.A / D converter.

[0002]

2. Description of the Related Art Due to the recent development of VLSI technology, ΣΔ
A / D conversion based on the method is drawing attention. First-order ΣΔA /
In the D converter, every time the OSR (Over Sampling Ratio) is doubled, the accuracy of the primary ΣΔA / D converter is improved by 1.5 bits. Also, a second-order ΣΔA / D converter and a third-order ΣΔA / D
In the converter, the accuracy increases by 2.5 bits and 3.5 bits each time the OSR is doubled. That is, in general, Nth-order ΣΔA /
In the D converter, the accuracy is (N + 0.
5) Bits will be improved.

Since increasing the OSR corresponds to narrowing the band, it is possible to obtain a wide band and high accuracy without increasing the OSR by using a high-order ΣΔ A / D converter.

However, in the third-order or higher ΣΔ A / D converter, it is 3
The stability of the next loop becomes poor and it is difficult to realize.
Therefore, a method of equivalently realizing a third-order ΣΔA / D converter by connecting a first-order ΣΔA / D converter in a three-stage cascade is "Y. Matsuya, et.al:A 16-bit Oversampling A-to. -D Co
nversion Technology Using Triple-Integration Noise
Shaping, IEEE JOUNAL OF SOLID-STATE CIRCUIT, Vol.2
2, No. 6 Dec. 1987 ”.

FIG. 5 is a block diagram showing an example of a third-order ΣΔ A / D converter in which such a first-order ΣΔ A / D converter is connected in a three-stage cascade. In FIG. 5, 1a,
1b and 1c are subtractors, 2a, 2b and 2c are integrators, 3a, 3b and 3c are 1-bit A / D converters, 4
a, 4b, and 4c are 1-bit D / A converters, 5 is a digital circuit that performs digital operation based on the outputs of the 1-bit A / D converters 3a to 3c, 100 is an analog input signal, and 101 is a digital output signal. is there.

The analog input signal 100 is input to one input of the subtractor 1a, and the output of the subtractor 1a is connected to one input of the 1-bit A / D converter 3a and the subtractor 1b via the integrator 2a. It The output of the 1-bit A / D converter 3a is connected to the 1-bit D / A converter 4a and the digital circuit 5, and the output of the 1-bit D / A converter 4a is the subtractor 1a.
Connected to the other input of.

The output of the subtractor 1b is 1 through the integrator 2b.
It is connected to one input of the bit A / D converter 3b and the subtractor 1c. The output of the 1-bit A / D converter 3b is connected to the 1-bit D / A converter 4b and the digital circuit 5,
The output of the 1-bit D / A converter 4b is connected to the other input of the subtractor 1b.

The output of the subtractor 1c is 1 through the integrator 2c.
It is connected to the bit A / D converter 3c. 1-bit A / D
The output of the converter 3c is connected to the 1-bit D / A converter 4c and the digital circuit 5, and the output of the 1-bit D / A converter 4c is connected to the other input of the subtractor 1c. The output of the digital circuit 5 is output as the digital output signal 101.

As can be seen from FIG. 5, in the ΣΔ A / D converter of FIG. 5, since each loop is first-order, stability can always be ensured.

On the other hand, the primary multi-bit ΣΔA /
Since the D converter can obtain high accuracy with a small OSR as compared with the first-order 1-bit ΣΔA / D converter, by using the high-order ΣΔA / D converter shown in FIG. High accuracy can be obtained with a small OSR.

[0011]

However, in the first-order multi-bit ΣΔ A / D converter, the multi-bit D / A converter is used as the D / A converter, and the 1-bit D / A converter is used.
The non-linearity error of a converter is zero, whereas the non-linearity error of a multi-bit D / A converter is generally difficult to zero. As a result, the primary multi-bit ΣΔA
The accuracy of the multi-bit ΣΔA / D converter deteriorates due to the non-linearity error of the multi-bit D / A converter used in the / D converter.

Further, even when the high-order ΣΔ A / D converter shown in FIG. 5 is multi-bit, it is a multi-bit D / A.
The accuracy of the multi-bit ΣΔ A / D converter deteriorates due to the non-linearity error of the converter. Therefore, the object of the present invention is to
It is to realize a high-precision, wide-band, high-order multi-bit ΣΔ A / D converter in which the influence of the non-linearity error of the multi-bit D / A converter is reduced.

[0013]

In order to achieve such an object, according to the present invention, a plurality of first-order ΣΔA / D converters are connected in cascade, and each of the plurality of first-order ΣΔA / D converters is connected. In a ΣΔ A / D converter composed of a digital circuit that calculates a digital output signal based on the output,
An analog input signal is input to the first stage, and (N-1) first-order ΣΔA / D converters cascade-connected to the (N-1) th stage and (N- 1) A first-order multi-bit ΣΔ A / D converter cascade-connected to the stage, an output of the first-order multi-bit ΣΔ A / D converter, and outputs of the (N-1) first-order ΣΔ A / D converters. And a digital circuit that calculates a digital output signal based on

[0014]

The first-order ΣΔ A / D converters are cascade-connected in a plurality of stages, and the final multi-stage ΣΔA is further provided in the final stage.
By connecting the / D converters in cascade, the effects of non-linearity errors in the multi-bit D / A converter are reduced.

[0015]

The present invention will be described in detail below with reference to the drawings.
FIG. 1 is a block diagram showing a third-order N-bit ΣΔ A / D converter which is a first embodiment of a multi-bit ΣΔ A / D converter according to the present invention. Here, 1a, 1b, 1c,
Reference numerals 2a, 2b, 2c, 3a, 3b, 4a and 4b are the same as those in FIG. In FIG. 1, 5a is a digital circuit, 6 is an N-bit A / D converter, and 7 is an N-bit D / A.
A converter, 100a is an analog input signal, and 101a is a digital output signal.

Further, 1a, 2a, 3a, 4a and 1b,
2b, 3b and 4b are primary ΣΔ A / D converters 50a and 50b, and 1c, 2c, 6 and 7 are primary N-bit ΣΔ.
Each of the A / D converters 51 is configured.

The analog input signal 100a is input to one input of the subtractor 1a, and the output of the subtractor 1a is an integrator 2a.
Is connected to one input of the 1-bit A / D converter 3a and the subtractor 1b. The output of the 1-bit A / D converter 3a is the 1-bit D / A converter 4a and the digital circuit 5a.
The output of the 1-bit D / A converter 4a is connected to the other input of the subtractor 1a.

The output of the subtractor 1b is 1 via the integrator 2b.
It is connected to one input of the bit A / D converter 3b and the subtractor 1c. The output of the 1-bit A / D converter 3b is connected to the 1-bit D / A converter 4b and the digital circuit 5a, and the output of the 1-bit D / A converter 4b is connected to the other input of the subtractor 1b.

The output of the subtractor 1c is passed through the integrator 2c to N
It is connected to the bit A / D converter 6. The output of the N-bit A / D converter 6 is the digital circuit 5a and the N-bit D / A.
It is connected to the converter 7 and the output of the N-bit D / A converter 7 is connected to the other input of the subtractor 1c. The output of the digital circuit 5a is output as the digital output signal 101a.

The components of the first embodiment shown in FIG. 1 are, for example, 1-bit A / D converters 3a and 3
b is a comparator or the like, 1-bit D / A converters 4a and 4b are multiplexers or the like, and the subtractors 1a to 1c and the integrator 2a.
2c can be respectively realized by a switched capacitor circuit or the like, while a normal flash type A / D converter or the like is used for the N-bit A / D converter 6 and a normal flash-type A / D converter 7 or the like. An R-2R ladder type D / A converter or the like can be used.

The operation of the embodiment shown in FIG. 1 will be described with reference to FIG. Here, FIG. 2 is a block diagram showing an equivalent circuit of the first embodiment shown in FIG. In FIG. 2, 1a, 1
b, 1c, 2a, 2b, 2c, 100a, 101a are the same as those in FIG. 1, and 8a, 8b, 8c, 8d, 13a
And 13b are adders, 9, 10, 11 and 12 are delay elements, 102, 103, 104 and 105 are output signals, 1
Reference numerals 06, 107 and 108 denote the respective quantization noise signals of the 1-bit A / D converters 3a and 3b and the N-bit A / D converter 6 shown in FIG. 1, and 109 denotes the N-bit D / A converter 7.
Is a non-linearity error signal of. However, the non-linearity error signal of the 1-bit D / A converters 4a and 4b shown in FIG. 1 is "0".
I am trying. In addition, the integrators 2a to 2c are "Z- ¹ / (1-
Z ^-1 ) "and 9 to 13b are the digital circuits 5
a is configured.

The analog input signal 100a is "X", the digital output signal 101a is "Y", and the output signals 102 to 1
05 is "Y1", "Y2", "Y3", and "Y", respectively.
4 ", the quantization noise signals 106 to 108 are" E1 ","
E2 ”and“ E3 ”, the non-linearity error signal 109 is set to“ δ
When set to 3 ", outputs" Y1 "to" Y "of each primary loop
3 ″ is represented by the following formula: Y1 = Z ⁻¹ · X + (1-Z ⁻¹ ) · E1 (1) Y2 = Z ⁻¹ · (Y2-E1) + (1-Z ⁻¹ ) · E2 (2) Y3 = Z ^-1 · (Y2-E2) + (1-Z ^-1 ) · E3-Z ^-1 · δ3 (3)

The output of the adder 13b is "Y4".
Is the addition result of the outputs of the delay elements 10 and 11, and therefore, using equations (2) and (3), Y4 = Z ⁻² · Y2 + (1−Z ⁻¹ ) · Y3 = Z ⁻¹ · Y2-Z ^-1 * (1-Z- ¹ ) * E2 + (1-Z- ¹ ) ² * E3-Z- ¹ * (1-Z- ¹ ) * δ3 = Z- ² * (Y1-E1) + (1- Z ⁻¹ ) ² · E3 −Z ⁻¹ · (1-Z ⁻¹ ) · δ3 (4).

Furthermore, since a is "Y" is the digital output signal 101a is a sum of the output of the delay element 9 and 12 using equation (1) and ^{(4), Y = Z -3} · Y1 + (1- ^{Z -1) · Y4 = (Z} -3 + Z -2 -Z -3) · Y1-Z -2 · (1-Z -1) · E1 + (1-Z -1) 3 · E3-Z -1 ^{· (1-Z -1) 2} · δ3 = Z -3 · X + Z -2 · (1-Z -1) · E1-Z -2 · (1-Z -1) · E1 + (1-Z -1 ^{) 3 · E3-Z -1 ·} (1-Z -1) 2 · δ3 = Z -3 · X + (1-Z -1) 3 · E3-Z -1 · (1-Z -1) 2 · δ3 (5)

As a result, as can be seen from the equation (5), the term "(1-Z ^-1 ) ² " is applied to the term of the nonlinearity error signal "δ3" of the N-bit D / A converter, That is, the non-linearity error signal “δ3” is subjected to second-order noise shaping, and the influence of the non-linearity error signal “δ3” is reduced.

FIG. 3 shows a multi-bit Σ according to the present invention.
A third embodiment of the ΔA / D converter, which is a third-order N-bit Σ
FIG. 3 is a configuration block diagram showing a ΔA / D converter. here,
1a, 1b, 1c, 2a, 2b, 2c, 3a, 3b, 4
Reference numerals a, 4b, 6, 7, 50a, 50b and 51 are the same as those in FIG. In FIG. 1, 5b is a digital circuit, 100b is an analog input signal, and 101b is a digital output signal.

The analog input signal 100b is input to one input of the subtractor 1a, and the output of the subtractor 1a is the integrator 2a.
Is connected to the 1-bit A / D converter 3a via. The output of the 1-bit A / D converter 3a is one input of the subtractor 1b, the 1-bit D / A converter 4a and the digital circuit 5b.
The output of the 1-bit D / A converter 4a is connected to the other input of the subtractor 1a.

The output of the subtractor 1b is 1 via the integrator 2b.
It is connected to the bit A / D converter 3b. 1-bit A / D
The output of the converter 3b is connected to one input of the subtractor 1c, the 1-bit D / A converter 4b and the digital circuit 5b,
The output of the 1-bit D / A converter 4b is connected to the other input of the subtractor 1b.

The output of the subtractor 1c is passed through the integrator 2c to N
It is connected to the bit A / D converter 6. The output of the N-bit A / D converter 6 is the digital circuit 5b and the N-bit D / A.
It is connected to the converter 7 and the output of the N-bit D / A converter 7 is connected to the other input of the subtractor 1c. The output of the digital circuit 5b is output as a digital output signal 101b.

The operation of the embodiment shown in FIG. 3 will be described with reference to FIG. Here, FIG. 4 is a block diagram showing an equivalent circuit of the second embodiment shown in FIG. In FIG. 4, 1a to 1
c, 2a to 2c, 100b and 101b have the same reference numerals as those in FIG. 3, and 8a to 8d, 11, 12, 106 to 109 have the same reference numerals as those in FIG. Also, 14 and 15 are delay elements,
16a and 16b are subtractors, and 102a, 103a, 10
4a and 105a are output signals. However, the non-linearity error signals of the 1-bit D / A converters 4a and 4b shown in FIG. 3 are "0". Further, 11 to 15 form the digital circuit 5b.

The analog input signal 100b is "x", the digital output signal 101b is "y '", and the output signal 102a.
To 105a are "y1", "y2", "y3" and "y4", respectively, and the quantization noise signals 106 to 108 are "E".
1 ”,“ E2 ”and“ E3 ”, the non-linearity error signal 109
Is “δ3”, the output of each primary loop is “y1”
~ "Y3" is represented by the following formula. y1 = Z ⁻¹ · x + (1-Z ⁻¹ ) · E1 (6) y2 = Z ⁻¹ · E1 + (1-Z ⁻¹ ) · E2 (7) y3 = Z ⁻¹ · E2 + (1-Z ^{− 1} ) ・ E3-Z ^-1・ δ3 (8)

The output of the subtractor 16b is "y4".
Is the result of subtracting the output of the delay element 11 from the output of the delay element 15, and therefore using equations (7) and (8), y4 = Z ⁻¹ · y2- (1-Z ⁻¹ ) · y3 = Z ^-1・ E1 + Z ^-1・ (1-Z ^-1 ) ・ E2-Z ^-1・ (1-Z ^-1 ) ・ E2-(1-Z ^-1 ) ²・ E3 + Z ^-1・ (1-Z ^{-1 ) · δ3 = Z -1 · E1-} (1-Z -1) 2 · E3 + Z -1 · (1-Z -1) · δ3 become (9).

Further, since the digital output signal 101b, "y", is the result of subtracting the output of the delay element 12 from the output of the delay element 14, y = Z ^-2 using the equations (6) and (9). * Y1 + (1-Z- ¹ ) * y4 = Z- ³ * x + Z- ² * (1-Z- ¹ ) * E1-Z- ² * (1-Z- ¹ ) * E1 + (1-Z- ^{1) ) 3 · E3-Z -1 ·} (1-Z -1) 2 · δ3 = Z -3 · X + (1-Z -1) 3 · E3-Z -1 · (1-Z -1) 2 · δ3 (10)

As a result, the equation (10) becomes the same as the equation (5), and similarly the non-linearity error signal "δ3" is subject to the second-order noise shaping, and the influence of the non-linearity error signal "δ3". Is less.

That is, the two first-order ΣΔ A / D converters 50
a and 50b are connected to each other in a cascade, and further the primary N-bit ΣΔA / D converter 51 is connected to the cascade so that the N-bit D / A used in the primary N-bit ΣΔA / D converter 51. It is possible to reduce the influence of the non-linearity error of the converter 7.

Further, the first-order ΣΔ A / D converter is not limited to two, but it is possible to connect a plurality of them in cascade.

[0037]

As is apparent from the above description, the present invention has the following effects. First-order ΣΔA / D
By connecting the converters in multiple stages in cascade and further connecting the first-order multi-bit ΣΔ A / D converter in the final stage, the effect of the non-linearity error of the multi-bit D / A converter is reduced. A high-order multi-bit ΣΔ A / D converter with high accuracy and wide band can be realized.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing a third-order N-bit ΣΔA / D converter that is a first embodiment of a multi-bit ΣΔA / D converter according to the present invention.

FIG. 2 is a block diagram showing an equivalent circuit of the first embodiment shown in FIG.

FIG. 3 is a configuration block diagram showing a third-order N-bit ΣΔA / D converter that is a second embodiment of a multi-bit ΣΔA / D converter according to the present invention.

FIG. 4 is a block diagram showing an equivalent circuit of the second embodiment shown in FIG.

FIG. 5 is a configuration block diagram showing an example of a third-order ΣΔA / D converter in which conventional first-order ΣΔA / D converters are connected in a three-stage cascade.

[Explanation of symbols]

1a, 1b, 1c, 16a, 16b Subtractor 2a, 2b, 2c Integrator 3a, 3b, 3c 1-bit A / D converter 4a, 4b, 4c 1-bit D / A converter 5, 5a, 5b Digital circuit 6 N-bit A / D converter 7 N-bit D / A converter 8a, 8b, 8c, 8d, 13a, 13b Adder 9, 10, 11, 12, 12, 14, 15 Delay 50a, 50b First-order ΣΔ A / D conversion Unit 51 Primary N-bit ΣΔ A / D converter 100, 100a, 100b Analog input signal 101, 101a, 101b Digital output signal 102, 102a, 103, 103a, 104, 104
a, 105, 105a Output signal 106, 107, 108 Quantization noise signal 109 Non-linearity error signal

Claims (1)

[Claims] 1. A ΣΔA / comprising a plurality of first-order ΣΔ A / D converters connected in cascade, and a digital circuit for calculating a digital output signal based on each output of the plurality of first-order ΣΔA / D converters. In the D converter, an analog input signal is input to the first stage, and (N-1) first-order ΣΔA / D converters are cascade-connected to the (N-1) th stage, and the first-order ΣΔA / D conversion is performed. Multi-bit ΣΔ A / D converter cascade-connected to the (N-1) th stage of the converter, the output of the first multi-bit ΣΔ A / D converter and the (N-1) first-order ΣΔA / D converters. An Nth-order multi-bit ΣΔ A / D converter, comprising: a digital circuit that calculates a digital output signal based on the output of the D converter.