JPH06120782A - Signal processing circuit - Google Patents

Abstract

PURPOSE:To reduce the power consumption without reducing the processing speed of the whole of a signal processing circuit by making the amplitude of a clock shorter than a normal gate signal amplitude in the signal processing circuit like a half latch circuit. CONSTITUTION:pMOS transistors TR and nMOS TRs constituting clocked inverters 2-1 and 2-2 are driven by a pair of clock driving circuits 4 independent of each other to which a supply voltage VDD and a ground voltage GND are supplied respectively, and an input signal IN is latched in an inverter 3 forming the half latch circuit and is outputted. The amplitude of the clock due to the circuit 4 is made shorter than the amplitude of the normal gate signal, and for example, the driving power is reduced to 1/4 when the amplitude of the clock is 1/2 of the normal gate signal amplitude; and thus, the power consumption is reduced without reducing the signal processing speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing circuit capable of reducing power consumption without lowering the operating speed of the circuit, and more particularly to a CMOS semiconductor integrated circuit.

[0002]

2. Description of the Related Art Conventionally, in a digital signal processing circuit which operates at high speed, a method of improving the throughput of processing by a pipeline structure has been used. In the pipeline structure, a logic circuit and an arithmetic circuit are divided into appropriate steps, and a latch circuit is provided at each step. For example, in a circuit that calculates the partial product of a certain value,
When the circuit for directly carrying the carry is connected, the partial product is calculated and the carry digit is calculated at a certain clock period. However, by inserting a register between these two circuits and dividing it into two steps, the next partial product operation is performed in parallel with the calculation of the digit of the previous carry in the pipeline processing. Therefore, the throughput of the process is improved. In addition, processing through
The put is determined by the delay time from the latch to the next latch. In that case, even in the pipeline, the processing time becomes slower as the number of logic gates connected in series during one step increases, so that the number of gates per stage is reduced as much as possible. To do. In the above example, the arithmetic circuit for the partial product uses as few gates as possible, and also has as few gates as possible in the carry circuit.
To use. Therefore, as the number of steps to be divided is increased and the number of stages of the logic gate from the latch to the latch of the next stage is reduced, the throughput of processing is improved. The technology relating to CMOS devices as digital signal processing circuits is described, for example, in "Trends in Latest CMOS Devices", July 1979, Electronic Science, April 24, 1979, published by Kobo, pp.13-67. There is.

[0003]

As described above, in order to improve the throughput of processing, the number of steps is increased and the number of logic gates from the latch to the next latch is reduced. However, it is necessary to provide more latch circuits. However, when the number of pipeline stages is increased, the power consumption of each latch circuit increases, and there is a problem that the power consumption increases more than the increase in the circuit scale. As an effective method of reducing power consumption, there is a method of lowering the power supply voltage. However, this method slows down the operation speed of the logic gate and lowers the speed performance of the circuit. By the way, an analysis of power consumption reveals that the latch circuit is directly driven by a clock, and therefore its power consumption is considerably higher than that of other ordinary logic gates. Since the normal logic gate state inversion handles a signal synchronized with the clock, even if it is assumed that the signal is inverted every clock cycle, it is only half the frequency of the clock. In general,
In the case of the normal logic gate state inversion, the frequency of ¼ of the clock is often set as the worst value. Therefore, a transistor driven directly by a clock (a half-latch circuit in which data is held at the rising or falling of the clock) is
It consumes four times as much power as a transistor forming a normal logic gate. Generally, in the case of a half-latch circuit composed of 10 transistors, the number of transistors serving as a clock load is 4 (see FIG. 1). If the power consumption of a transistor forming a normal gate is 1, the power consumed by a normal gate formed of 10 transistors is 10, and a half gate formed of 10 transistors is used. The power in the case of a latch circuit is 4
X4 + 6 = 22. Therefore, the power consumed by the latch circuit is more than twice that of the normal gate. For example, in a digital filter using a three-stage pipeline configuration, the power consumption of a normal arithmetic circuit is 60% of the total.
%, And the consumption by the latch is 40%. As described above, 16/22 of the power consumption by the latch circuit is consumed because it is directly driven by the clock. Therefore, about 30% of the whole is consumed by the circuit directly driven by the clock. An object of the present invention is to provide a signal processing circuit that solves such a conventional problem and can reduce power consumption without substantially reducing the processing speed of the entire circuit.

[0004]

In order to achieve the above object, a signal processing circuit of the present invention comprises: (a) a signal processing circuit composed of a CMOS semiconductor integrated circuit, which supplies a clock to a p-channel MOS transistor. 1 clock drive circuit and a second clock drive circuit for supplying a clock to an n-channel MOS transistor, and the amplitudes of the clock signals of the first and second clock drive circuits are compared with those of the normal logic gate. The feature is that it is smaller. (B) The first and second clock drive circuits are composed of inverters that are connected to each other at the midpoint of the power supply voltage level and the ground voltage level, and charge is distributed between the load capacitors of the clock drive circuits. It also features charging and discharging. Further, (c) the first and second clock drive circuits have the power supply voltage VDD and the ground voltage GND, P
Set the threshold voltage of the MOS and NMOS transistors to V
thp, Vthn, and the voltage applied to the PMOS and NMOS transistors is Vmp (> 0) and Vmn (> 0), the clock drive circuit for driving the PMOS transistor has a signal swinging between VDD-Vthp-Vmp and VDD. The clock drive circuit for driving the NMOS transistor and driving the NMOS transistor is also characterized in that it outputs a signal swinging between Vthn + Vmn and GND.

[0005]

In the present invention, the clock amplitude is normally
Signal amplitude of the latch circuit to reduce power consumption of the latch circuit. Specifically, a low-amplitude clock drive circuit that independently drives PMOS and NMOS transistors among the transistors driven by the clock of the latch circuit is provided. By the way, when the amplitude of the clock is swung by the full swing of 0 to the power supply voltage, a voltage corresponding to the swing is required. On the other hand, as is clear from the relationship of P = (1/2) CV ² , if the amplitude is halved, the power can be reduced to ¼. Further, as is clear from the equation of the time constant of T = CR, the resistance R becomes large by decreasing the amplitude, so that the time constant becomes large and the operation speed becomes slow. Therefore,
Although the delay of the latch circuit itself increases, since the delay of the latch circuit itself occupies a small amount of the entire delay time, the delay as a whole is not so large. As a result, the processing speed of the entire digital signal processing circuit is hardly reduced,
Power consumption can be reduced.

[0006]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a configuration diagram of a signal processing circuit showing an embodiment of the present invention. In FIG. 1, a harf composed of clocked inverters 2-1 and 2-2 and an inverter 3.
A latch circuit is shown. The clocked inverters 2-1 and 2-2 which are directly driven by the clock are each composed of four PMOS and NMOS transistors, a total of eight transistors.
Two PMOSs and NMOSs forming the inverter 3
It is a transistor. Here, the clocked inverter
The clock signal from the clock drive circuit 4 is input to the gate control terminals of the computers 2-1 and 2-2. That is, the clock signal φp is the PMOS of the clocked inverter 2-1.
The clock signal / φp is supplied to the gate of the transistor, and the clock signal φn is clocked to the gate of the PMOS transistor of the next clocked inverter 2-2.
-1 to the gate of the NMOS transistor, the clock signal / φn is the NMOS of the next clocked inverter 2-2.
It is applied to the gates of the transistors. Although only the half-latch circuit composed of two clocked inverters and one inverter is described in this embodiment, the clocks of other flip-flop circuits etc. are inputted. The same applies to all circuits.

FIG. 2 is a waveform diagram of a clock input to the half latch circuit of FIG. In FIG. 1, the power supply voltage is VDD, the ground point is GND, and the threshold voltages of the PMOS and NMOS transistors are Vthp, Vthn, and PMO, respectively.
The voltages applied to the S and NMOS transistors are Vmp and Vmn, respectively, and Vmp> 0 and Vmn> 0.
As shown in FIG. 2, the clock driving circuit 4 for driving the PMOS transistors is provided with VDD-Vthp-Vmp and VD.
A signal swinging between D is output. Further, the clock drive circuit 4 for driving the NMOS transistor is Vthn + V
It outputs a signal that swings between mn and GND. In order to further simplify the clock drive circuit 4, the clock drive circuit 4 that drives the PMOS transistor is a circuit that outputs a signal swinging between VDD / 2 and VDD, and the clock drive circuit 4 that drives the NMOS transistor is VDD /
It is a circuit that outputs a signal swinging between 2 and GND.

FIG. 3 is a block diagram showing an embodiment of the clock drive circuit in FIG. Each of the four clock driving circuits 4 is composed of an inverter 5 or 6 composed of a PMOS and an NMOS transistor. In the inverters 5 and 6, the source of the NMOS transistor of the one inverter 5 and the source of the PMOS transistor of the other inverter 6 are connected to form a virtual midpoint 7, and the former inverter is used. The source of the PMOS transistor of the data 5 is VDD
In addition, the latter inverter 6 NMOS transistor source
The ground is connected to GND. The figure shows two circuits that generate a positive-phase clock and a negative-phase clock. By making the load capacitances Cp, Cn, / Cp, / Cn on the driven side equal (that is, Cp = Cn, / Cp =
/ Cn), the amount of charge and discharge is the upper inverter 5
Then, the lower inverter 6 becomes equal, and the potential at the virtual midpoint 7 is held at VDD / 2. As a result, the clock drive circuit 4 having a low amplitude can be realized without providing a new power supply terminal for the clock drive circuit 4.

As shown by arrows in FIG. 3, clock driving circuits 5 and 6 for supplying a clock signal to the clocked inverter 2-1 and a clock signal to the clocked inverter 2-2. With the clock driving circuits 5 and 6, the load capacitances Cp, Cn and / Cp, / Cn are charged and discharged to perform a catch ball.
That is, the arrows of the clock driving circuits 5 and 6 on the left side indicate charging and discharging, and the clock driving circuits 5 and 6 on the right side.
Arrows indicate discharging and charging. As described above, in the present invention, the data is applied with the full-amplitude voltage as usual, but the power consumption can be reduced by applying only the necessary small amplitude to the clock signal. For example, when the power supply voltage is 5 V, the clock signal voltage is 2.5
When it is set to V, the voltage becomes higher than the required minimum voltage, but for the sake of simplification of the circuit, a clock drive circuit as shown in FIG.
Provides a clock signal. In FIG. 3, the clock drive circuit 5 has an amplitude of 5V to 2.5V, and the clock drive circuit 6 has an amplitude of 0V.
A clock signal voltage is supplied with an amplitude of V to 2.5V. However, a smaller amplitude, for example 5V
It is also possible to supply a clock signal with an amplitude of 3V and 0V to 2V. Further, it is also possible to supply them by overlapping each other like the amplitude of 5V to 2V and the amplitude of 0V to 3V. In this case, it is necessary to insert a reference power source, a diode, etc. in the circuit of FIG. 3, which complicates the circuit.

FIG. 4 is a detailed diagram of the signal processing circuit in FIG. As shown in FIG. 4, the two clocked inverters 2-1 and 2-2 are connected in parallel to the clock drive circuit 4, and both outputs of the clocked inverters 2-1 and 2-2 constitute the inverter 3 of the final stage.
It is connected to the gates of the MOS and NMOS transistors. The signal input is applied to the gate of the signal input PMOS and the gate of the signal input NMOS transistor of the clocked inverter 2-1. Further, the clock signal φp is a switching PMOS of the clocked inverter 2-1.
The clock signal φn is applied to the gate of the transistor, and the clock signal φn is applied to the gate of the switching NMOS transistor. Further, the clock signal / φp is applied to the gate of the switching PMOS transistor of the clocked inverter 2-2, and the clock signal / φn is applied to the gate of the switching NMOS transistor. Also,
The feedback line of the output of the inverter 3 is connected to the signal input PMOS transistor of the clocked inverter 2-2 and the NMO.
It is connected to each gate of the S transistor. When the clock drive circuit of FIG. 3 is applied to the signal processing circuit of FIG. 4, the load capacitance Cp is mainly the gate-substrate capacitance of the switching PMOS transistor of the clocked inverter 2-1 and the load capacitance Cn. Is mainly for switching N
This is the gate-substrate capacitance of the MOS transistor. Similarly, the load capacitances / Cp and / Cn are the gate-substrate capacitances of the switching PMOS transistor and the switching NMOS transistor of the clocked inverter 2-2, respectively. In other words, the circuit of FIG.
To apply the clock drive circuit of these, these switching PMOS transistors, switching NMOS
It is necessary to make the gate-substrate capacitances of the transistors equal to each other.

FIG. 5 is an equivalent circuit diagram in FIG.
5 is an equivalent circuit showing the first half time phase of the clock waveform of FIG. 2, and is an equivalent circuit showing the second half time phase of the clock waveform of FIG. In the first half of the clock of FIG. 2, the low-level clock signal φp is switched to the switching PMOS transistor of the clocked inverter 2-1 and the high-level clock signal φn is switched to the clocked inverter 2-1. Since it is applied to the respective NMOS transistors, as shown in FIG. 5, the clocked inverter 2-
1 becomes the operating state. On the other hand, a high level clock signal /
φp is a low level clock signal / φ to the switching PMOS transistor of the clocked inverter 2-2
n is N for switching the clocked inverter 2-2
Since the voltage is applied to each MOS transistor, FIG.
The clocked inverter 2-2 is shut off as shown in FIG. Therefore, in the first half of the clock, the signal processing circuit becomes the equivalent circuit of FIG. 5, and the input signal is in the through state. Next, in the latter half of the clock, the high level clock signal φp is applied to the switching PMOS transistor of the clocked inverter 2-1 and the low level clock signal φn is applied to the switching NMOS transistor. , As shown in FIG.
The inverter 2-1 is cut off. On the other hand, the low-level clock signal / φp is applied to the switching PMOS transistor of the clocked inverter 2-2, and the high-level clock signal / φn is applied to the switching NMOS transistor. like,
The clocked inverter 2-2 becomes active. Therefore, in the latter half of the clock, the signal processing circuit becomes the equivalent circuit of FIG. 5, and the input signal immediately before changing from to cannot pass through the circuit, and is in the latch state.

In the present embodiment, the processing speed of the entire circuit is determined by the gate delay from the latch to the latch of the next stage, but this gate (2-1, 2-2, 3 in FIG. 4). Since the conventional power supply voltage is applied, the delay does not increase. That is, the delay of the latch circuit itself increases, but the delay amount of the latch circuit itself occupies the entire delay time, which is originally small. When the clock drive circuit of FIG. 3 is used, the power consumption of the circuit directly driven by the clock is 1/4 that of the conventional one. For example, in a digital filter using a three-stage pipeline configuration, the power consumption of the circuit directly driven by the clock, which occupies 30% of the total, is reduced to 1/4. (30-8 = 22).

[0013]

As described above, according to the present invention,
By providing a low-amplitude clock drive circuit that independently drives the PMOS and NMOS transistors among the transistors driven by the clock of the latch circuit, the processing speed of the entire signal processing circuit is not reduced and the consumption is reduced. It is possible to reduce the power.

[0014]

[Brief description of drawings]

FIG. 1 is a configuration diagram of a signal processing circuit showing an embodiment of the present invention.

2 is a waveform diagram of a clock signal supplied from the clock driving circuit of FIG.

FIG. 3 is a configuration diagram of a clock drive circuit in FIG.

FIG. 4 is a diagram showing a detailed configuration of the signal processing circuit of FIG.

5 is a diagram showing an equivalent circuit of the signal processing circuit in FIG.

[Explanation of symbols]

 2-1 and 2-2 Clocked inverter 3 Inverter constituting a half-latch circuit 4 Clock drive circuit 5, 6 Inverter constituting a clock drive circuit 7 Virtual midpoint of clock drive circuit INde -Data input terminal OUT Data output terminal VDD Power supply voltage GND Ground voltage Cp, Cn, / Cp, / Cn Load capacitance

Claims (3)

[Claims] 1. A signal processing circuit composed of a CMOS semiconductor integrated circuit, wherein a first clock driving circuit for supplying a clock to a p-channel MOS transistor and a second clock driving circuit for supplying a clock to an n-channel MOS transistor. And a signal processing circuit characterized in that the amplitudes of the clock signals of the first and second clock driving circuits are smaller than the signal amplitude of the normal logic gate. 2. The first and second clock drive circuits are composed of inverters connected to each other at a midpoint of a power supply voltage level and a ground voltage level, and are connected between load capacities of the respective clock drive circuits. The signal processing circuit according to claim 1, which charges and discharges electric charges. 3. The first and second clock drive circuits have a power supply voltage of VDD, a ground voltage of GND, a threshold voltage of PMOS and NMOS transistors of Vthp, and a threshold voltage of Vthp, respectively.
When Vthn and the voltages applied to the PMOS and NMOS transistors are Vmp (> 0) and Vmn (> 0), P
In the clock drive circuit that drives the MOS transistor,
The signal swinging between VDD-Vthp-Vmp and VDD is output, and the clock driving circuit that drives the NMOS transistor outputs a swinging signal between Vthn + Vmn and GND. Signal processing circuit.