JPH06120422A - Semiconductor integrated circuit and manufacture thereof - Google Patents

Abstract

PURPOSE:To supply a stable voltage by utilizing the pn junction under a thick field oxide film as a capacitance for voltage stabilization thereby to reduce the impedance of a predetermined voltage-line. CONSTITUTION:A selective ion implantation is performed in a predetermined position of a p-type Si substrate 1 to form a high doped buried layer 3 of n<+>Si. Then, a semiconductor epitaxial layer 5 of n<->Si is deposited. A p-type impurity ion implantation is performed immediately above the high doped buried layer 3 to form a high doped semiconductor region 4 of p<+>-type Si. Thereafter, a thick field oxide film 2 is formed by high-temperature thermal oxidation. Thus, a pn junction capacitance can be formed under the field oxide film, and can be utilized as a capacitance if a wiring is connected to the pn junction region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit including a voltage stabilizing capacitance.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit such as an ECL / CML (common emitter current switching logic) circuit, a reference voltage is required to operate the circuit. Therefore, the reference voltage generating circuit is provided.

However, with only the reference voltage generating function, there is a possibility that a transient voltage fluctuation due to current switching may affect the reference voltage to cause a malfunction or cause the reference voltage generating circuit to oscillate.

Therefore, a method is generally used in which a capacitance is connected to the reference voltage generating circuit to reduce the circuit impedance and suppress the voltage fluctuation due to the peak current. As the electrostatic capacitance used for this purpose, a junction capacitance obtained by reverse biasing a pn junction formed by an impurity diffusion method is usually used.

In order to obtain such a capacitance for buffering voltage fluctuations, conventionally, after forming a field oxide film on the surface of a semiconductor substrate, a pn junction is often formed in a region without a field oxide film.

[0006]

The capacitance value required for the reference voltage generating circuit is usually several hundred fF to several pF. Capacitance due to reverse bias of pn junction is 1fF / μ
Since it is about m ^2, an area of several hundreds to several thousands μm ² is required to obtain a capacitance value of several hundreds fF to several pF.

For example, a substrate area of about 30 μm square is required to form a capacitance of 1 pF. Thus, consuming the substrate area is a major obstacle to high integration. The top of the capacitance is usually covered with a thin oxide film. If wiring is formed on this oxide film, the degree of integration can be improved,
The problem of signal delay arises. That is, signal wiring and pn
A large electrostatic capacitance is formed between the (or pin) junctions, and a signal propagating through the signal wiring is delayed by a large RC time constant based on the large electrostatic capacitance, which impairs the high speed performance of the ECL / CML type integrated circuit or the like. Be done. In addition, this problem is
It is not limited to ECL / CML.

An object of the present invention is to provide a semiconductor integrated circuit including an additional electrostatic capacitance which causes less signal delay without increasing the chip size.

[0009]

A semiconductor integrated circuit according to the present invention comprises a field oxide film for element isolation / insulation provided in an element non-formation region formed so as to surround an element formation region of the semiconductor integrated circuit. Of the semiconductor region, a pn junction region selectively formed in the semiconductor region, and a bipolar transistor provided in the element forming region are included, and the pn junction region is used as a stabilizing capacitance against voltage fluctuation.

[0010]

The field oxide film has a function of completely insulating and separating the element formation region of the semiconductor integrated circuit, for example, the functional element formation region and the input / output buffer circuit formation region.

The pn junction region formed under the field oxide film can form a sufficient capacitance while reducing the influence on other circuit elements. Even if the wiring is formed on the field oxide film, electrical interference between the formed wiring and the capacitance is small. By using the field oxidation region as the capacitance forming region and the wiring region,
A high degree of integration can be obtained with a predetermined chip area.

The present invention will be described in more detail below based on examples.

[0013]

EXAMPLE FIG. 1 is a sectional view showing a state in which a pn junction type voltage stabilizing capacitance according to an example is formed immediately below a field oxide film 2.

A heavily doped buried layer 3 having a second conductivity type (n type) is formed in a predetermined region on a main surface of a semiconductor substrate 1 having a first conductivity type such as p ⁻ type single crystal Si. Formed,
A semiconductor epitaxial layer 5 having a second conductivity type such as n ⁻ type Si is deposited thereon.

In the region immediately above the heavily doped buried layer 3 of the semiconductor epitaxial layer 5, a heavily doped semiconductor region 4 having a first conductivity type such as p ⁺ type is formed by impurity ion implantation.

A pn junction is formed in the semiconductor epitaxial layer 5 by impurity diffusion from the heavily doped buried layer 3 into the semiconductor epitaxial layer 5. A thick field oxide film 2 is formed on the main surface of the semiconductor epitaxial layer 5 by thermal oxidation. The conductivity type of each region may be reversed.

The structure as shown in FIG. 1 can be manufactured by the process as shown in FIG. 2 or 3. First, the process of FIG. 2 will be described. First, as shown in FIG. 2A, for example, selective diffusion or selective ion implantation is performed using a mask (not shown) patterned at a predetermined position of the p ⁻ type Si substrate 1 to increase the n ⁺ type Si level. A heavily doped buried layer 3 is formed.

Next, as shown in FIG. 2B, a semiconductor epitaxial layer 5 made of n ⁻ type Si having a thickness of 1.5 to 2 μm, for example, is deposited. In this process, the region of the heavily doped buried layer 3 is expanded due to the impurity diffusion, and the semiconductor epitaxial layer 5 is also penetrated as shown in the figure.

Next, as shown in FIG. 2C, using the same mask as the heavily doped buried layer 3, p-type impurity ions are implanted directly above the heavily doped buried layer 3 to obtain p ^+. Type S
A heavily doped semiconductor region 4 of i is formed. p ⁺
To obtain the type Si, for example, B ⁺ is about 10 ¹⁵ cm ^-2 5
The dose may be about 60 KeV. As a result, a pn junction having a predetermined capacitance is formed.

After that, as shown in FIG. 2D, a thick field oxide film 2 is formed by high temperature thermal oxidation. For example, its thickness is 0.5 μm. In this way
A pn junction capacitor can be formed under the field oxide film.

FIG. 3 shows a process in which the steps of FIGS. 2C and 2D are reversed. 3A and 3B show p ⁻ type S
A step of forming an n ⁺ type buried layer 3 on the surface of the semiconductor substrate 1 of i and then growing an epitaxial layer 5 of n ⁻ type Si on the surface of the semiconductor substrate 1 will be described.

Thereafter, as shown in FIG. 3C, the surface of the epitaxial layer 5 is thermally oxidized to form the field oxide film 2. After forming the field oxide film 2, FIG.
As shown in (D), p-type impurity ions are implanted into the epitaxial layer 5 through the field oxide film 2.

When ion implantation is performed from above the field oxide film 2, naturally a higher acceleration voltage is required. For example, in order to ion-implant B ⁺ at the same concentration from an oxide film having a thickness of 0.5 μm, an accelerating voltage of several hundred KeV is required.

If a wiring is connected to the pn junction region formed as shown in FIGS. 2 and 3, it can be used as a capacitor.
The conductive connection to the pn junction is, for example, U as shown in FIG.
It can be performed using a groove.

As shown in FIG. 4A, a photoresist layer (not shown) is formed on the thick field oxide film 2 and the field oxide film 2 is subjected to appropriate dry etching, for example, using a CCl ₄ -based gas. A groove-shaped opening is formed by means of isotropic etching, and the exposed Si is selectively etched using an etching gas such as Freon to form a U-shaped groove 6 reaching the middle of the heavily-doped semiconductor region 4 formed by ion implantation. To do.

Next, heavily doped polysilicon 7 heavily doped with p-type impurities is formed into a U-shaped groove 6 by a CVD method or the like.
Fill inside. The polysilicon deposited on the field oxide film 2 can be removed by dry etching.

When subjected to an appropriate heat treatment, polysilicon 7
P-type impurities, such as boron, doped in
The high-concentration doped buried layer 3 is also penetrated from the bottom region of the groove 6, and the p-type region is expanded to form a pn junction, as shown in the figure. The boron diffusion region 8 simply functions as a low resistance region in the p-type heavily doped semiconductor region 4.

FIG. 4B shows a case where the U-shaped groove 6 is deeply formed to reach the inside of the n ⁺ -type heavily doped buried layer 3.
In this case, the diffusion is controlled so that the boron diffusion region 8 does not penetrate the heavily doped buried layer 3 and reach the p ⁻ type Si semiconductor substrate 1 region.

A wiring is formed on the field oxide film 2 and U
When it is necessary to completely insulate between the polysilicon 7 filled in the groove 6 and the wiring arranged on the field oxide film 2, as shown in FIG. After etching off, the SiO ₂ film 10 can be formed thereon by thermal oxidation or CVD.

The conductive connection to the polysilicon 7 once filled with the SiO ₂ film 10 is at a position where there is no problem, for example, as shown in FIG.
As shown in (B), the metal wiring 9 such as Al may be formed in the opening provided in a part of the SiO ₂ film 10.

The conductive connection to the pn junction region need not be backfilled with polysilicon by providing the U-shaped groove 6 in this way. It is also possible to perforate the field oxide film 2 in an appropriate shape and directly connect conductive wiring to the heavily doped semiconductor region 4.

For example, FIG. 6 (A) illustrates a circular perforation.
In this example, the opening is filled with metal wiring 9 such as Al.
6 (B) is Si₃N_FourArea where the contact part should be formed
After covering it, it is subjected to selective thermal oxidation by the LOCOS method and then the field.
Form oxide film 2₃N _FourAfter removing the
This is an example of performing the metal wiring 9.

The electrical connection of the pn junction to the n ⁺ -type high-concentration buried layer 3 can be made by the U-shaped groove as described above and the n ⁺ -type polysilicon filled therein.
It is also possible to form a contact on the n ⁻ type epitaxial layer 5 connected to the ⁺ type high concentration buried layer 3. Note that an electrical isolation region is formed so as to surround the pn junction region and isolate the pn junction region from other circuit elements.

FIG. 7 shows an example of connection between two adjacent pn junction regions (capacitance). Between the two pn junction regions,
A U-shaped groove 12 formed by selective etching is provided to a substrate position deeper than the pn junction region. This U-shaped groove can be used as the above-mentioned electrical isolation region.

After the side walls and bottom of the U-shaped groove 12 are completely insulated by thermal oxidation, the inside thereof is filled with polysilicon heavily doped with impurities to form a conductive region. In addition to the thermal oxide film, an insulating film may be deposited by CVD.

In each pn junction region, a U-shaped groove 6 reaching the p ⁺ -type heavily doped semiconductor region 4 is formed, and a suitable conductive material such as p ⁺ -type polysilicon is filled in the inside thereof, and the U-shaped groove 6 is formed on the surface. A metal wiring 9 made of Al or the like is formed on. The p ⁺ region of each pn junction region is electrically connected via the metal wiring 9 and the conductive region in the U-shaped groove 12.

The connection between the n ⁺ regions of the pn junction region can be similarly made. The polysilicon in the deep U-shaped groove may be p-type or n-type as long as it makes a connection between metals.

On the polysilicon filling the U-groove 12,
Once a thick field oxide film or CVD oxide film is formed, a part of the field oxide film 2 is perforated to form a U-shaped groove 12
It is also possible to carry out metal wiring reaching up to.

Further, there is also a method in which the polysilicon in the U-shaped groove 12 is doped with a high concentration by ion implantation, the surface thereof is covered with a thin oxide film, and metal wiring is formed on the surface to perform capacitive coupling wiring.

The electrostatic capacitance of the region directly under the field insulating film thus formed is connected to, for example, the bipolar transistor in the element forming region of the integrated circuit as shown in FIG. In this case, the capacitance C is connected to the collector of the bipolar transistor Tr by the metal wiring 9. The separation U-shaped groove 12 separates the capacitance C from the bipolar transistor Tr.

The connection of the capacitance for stabilizing the voltage is not limited to this. For example, the wiring line of the ECL / CML type integrated circuit is shown in FIG. In the figure, what is indicated by a diode symbol is the capacitance due to the pn junction. 9A shows a circuit diagram of the main part of the ECL / CML circuit, and FIG. 9B shows a circuit diagram of the reference voltage generating circuit thereof.

Intermediate potentials V _ref , V _cs , V that need to be stabilized
Capacitances are connected to _rm etc. and the power supply voltage. Regarding the potential shared in the integrated circuit,
The capacitance to be connected may be shared as desired.

FIG. 10 shows an example of a layout pattern of element forming regions and field oxide film regions in a semiconductor chip. Each element formation region (including the input buffer circuit region) shown by a rectangle is electrically insulated by the field oxidation region.

Since the field oxide region has a sufficiently large area as compared with the element forming region, the voltage stabilizing capacitance can be formed with a sufficient margin without increasing the chip size. For example, a capacitance for stabilizing the power supply voltage can be continuously formed under a wide field oxide film surrounding a plurality of element regions.

Although the capacitance formed in the semiconductor chip for forming an integrated circuit has been described above, the number and size of the capacitance formed in the chip can be freely selected. Further, in order to insulate the formed capacitance from the surroundings, an insulating region or the like surrounding the capacitance and penetrating the epitaxial layer may be formed.

It is also possible to form a plurality of capacitances in the chip, for example, in a stripe shape, an interdigital shape, or the like. Further, the integrated circuit is not limited to the one including the bipolar transistor, but may include the bipolar transistor and the CM.
It can also be applied to a device including an OS transistor.

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example,
It will be apparent to those skilled in the art that various changes, improvements, combinations and the like can be made.

[0048]

As described above, according to the present invention,
Since the pn junction under the thick field oxide film can be used as the voltage stabilizing capacitance, the impedance of the predetermined voltage line can be lowered and a stable voltage can be supplied.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a pn junction type capacitance according to an example.

FIG. 2 is a cross-sectional view showing a manufacturing process for obtaining the structure of FIG.

3 is a cross-sectional view showing another manufacturing step for obtaining the structure of FIG.

FIG. 4 is a cross-sectional view showing an example of conductive connection to the electrostatic capacitance of FIG.

5 is a cross-sectional view showing another conductive connection example for the capacitance of FIG.

6 is a cross-sectional view showing still another conductive connection example with respect to the capacitance of FIG.

FIG. 7 is a cross-sectional view showing a connection example of two capacitances.

8 is a cross-sectional view showing an example of connection of the electrostatic capacitance of FIG. 1 to a bipolar transistor.

FIG. 9 is a circuit diagram showing an example of capacitance wiring.

FIG. 10 is a plan view showing an arrangement pattern example of element formation regions and field oxide film regions in a semiconductor chip.

[Explanation of symbols]

1 semiconductor substrate (p ⁻ type Si) 2 field oxide film 3 heavily doped buried layer (n ⁺ ) 4 heavily doped semiconductor region (p ⁺ ) 5 semiconductor epitaxial layer (n ⁻ ) 6 U-shaped groove 7 heavily doped Polysilicon 8 Boron diffusion region 9 Metal wiring 10 SiO ₂ film 11 p ⁺ type Si 12 U-shaped groove

Claims (4)

[Claims] 1. A pn junction selectively formed in a semiconductor region below a field oxide film for element isolation / insulation provided in an element non-formation region formed so as to surround an element formation region of a semiconductor integrated circuit. Regions (3, 4) and bipolar transistors (T
r) and a structure that uses the pn junction region as a stabilizing capacitance against voltage fluctuations. 2. The semiconductor integrated circuit according to claim 1, further comprising a wiring formed on a field oxide film on the pn junction region. 3. The semiconductor integrated circuit according to claim 1, wherein the pn junction region is formed so as to surround a plurality of semiconductor element formation regions. 4. A step of forming a heavily doped buried layer having a second conductivity type at a predetermined position of a semiconductor substrate having a first conductivity type, and a semiconductor layer having a second conductivity type on the semiconductor substrate. A step of performing epitaxial growth on the epitaxially grown layer and selectively ion-implanting the epitaxially grown layer to form a pn junction with the heavily doped buried layer having substantially the same shape and area as the heavily doped buried layer; And a step of forming a field oxide film on the epitaxial growth layer in which the pn junction is formed, and a method of manufacturing a semiconductor integrated circuit.