JPH06119791A - Semiconductor integrated circuit and microcomputer - Google Patents

Abstract

PURPOSE:To properly apply high voltage of writing in a semiconductor memory where a part of a memory cell array containing an electrically writable storage element is used as read only. CONSTITUTION:VPP supply from a VPP supply circuit 10 to a common data line is stopped when WEROM* is asserted to a low level by detecting write in a ROM part by providing a ROM part write detection circuit 20. Thus, the undesired VPP supply to the ROM part 30 is inhibited, and the high voltage of writing is applied properly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and moreover, a high voltage application for programming of a semiconductor memory device in which a part of a memory cell array including electrically writable memory elements is used as read only. The present invention relates to a technique for optimizing the above, for example, a technique effectively applied to a program memory of a single-chip microcomputer.

[0002]

2. Description of the Related Art A semiconductor integrated circuit such as a microcomputer has a ROM for storing programs and data.
(Read-only memory), RAM (random access memory) for temporarily storing data,
Alternatively, an input / output circuit or the like for inputting / outputting data is mounted, and these are formed on one semiconductor substrate such as silicon. In such a semiconductor integrated circuit, in order to make the ROM electrically rewritable, EP
This can be realized by adopting a ROM (electrically programmable ROM). EPROM is FAMO
S (floating gate avalanche)
injection MOS) structure and SAMOS (stack) in which a control gate is added to FAMOS.
ed avalanche injection MO
Although there is a memory of S) structure, all of them are p-channel, and at present, the memory of n-channel type channel injection structure in which the memory cell has a one-transistor structure is predominant. In this memory, writing is performed by applying a high voltage to the control gate and drain and flowing a saturated channel current between the source and drain. In the pinch-off region near the drain, the electrons accelerated by the high electric field are ionized, and electrons with high energy (hot electrons) are generated. In order to increase the electric field in the pinch-off region, the impurity concentration in the channel region is usually increased. On the other hand, a capacitance division voltage is generated in the floating gate, and this voltage causes hot electrons to be injected into the floating gate. In the erasing, since the potential barrier between the floating gate and the oxide film is 3.2 eV in the n-channel MOS transistor, ultraviolet rays having a wavelength corresponding to energy higher than this are used.

Incidentally, as an example of a document describing a single-chip microcomputer, Japanese Patent Laid-Open No. 01-1 is available.
There is 62971.

[0004]

For example, in a single-chip microcomputer or the like, an EPROM is mounted as a program memory for storing a program executed by a central processing unit (CPU) included therein. In such an EPROM, a ROM part dedicated to reading out a part of the EPROM is formed, and this ROM part may be used for storing a test program or the like that does not require rewriting. In this case, the ROM section and the EPRO are on the same data line.
The M section is formed, and the ROM section, E
The PROM section is used properly. In the case where the ROM portion is formed by using a part of the EPROM as described above, conventionally, the write voltage supply circuit for supplying the write voltage to the memory cell is controlled by the write operation control signal regardless of the address input signal. In other words, in the write operation, the write voltage supply circuit is operated to generate the write voltage regardless of which bit on the memory matrix is selected. Therefore, when the ROM section and the EPROM section are formed on the same data line, the write voltage is applied to the data line selected by the column selection switch, and at this time, if the address signal is erroneously input or the circuit malfunctions, When the ROM section is selected, undesired writing is performed on the ROM section that is originally dedicated to reading, and the stored contents of the ROM section are rewritten. Further, the application of such an unnecessary high voltage may lead to a decrease in reliability of the memory cell.

An object of the present invention is to optimize the application of a high voltage for writing in a semiconductor memory device in which a part of a memory cell array including electrically writable memory elements is used exclusively for reading. is there. Another object of the present invention is to improve the reliability of a semiconductor memory device in which a part of a memory cell array including electrically writable memory elements is used as a read only memory.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, when a part of a memory cell array including a memory element which is electrically writable by high voltage supply is used as a read-only memory and the read-only area is addressed in the write mode to the memory cell array, A semiconductor memory device is configured by providing a control circuit for blocking high voltage supply to the read-only area.

In the memory cell, FAMOS transistors are arranged in a matrix, and the control circuit includes a logic circuit for detecting addressing of the read-only area by a row address monitor. it can.

Further, the semiconductor memory device is included to form a single-chip microcomputer.

[0011]

According to the above-mentioned means, the control circuit prevents the high voltage supply to the read-only area when the read-only area is addressed in the write mode to the memory cell array, thereby making the read-only area concerned. Prevent writing to the area. This achieves the optimization of the application of the high voltage for writing in the semiconductor memory device in which a part of the memory cell array including the electrically writable memory element is used as a read-only memory. Achieve improved reliability of the device.

[0012]

FIG. 5 shows a case where the semiconductor memory device according to the present invention is applied to a single chip microcomputer.

The single-chip microcomputer shown in FIG. 5 stores a central processing unit (hereinafter also simply referred to as CPU) 61 for controlling execution control procedures of various operations and instructions, and a program executed by the CPU 61. The program memory 63, the SRAM 66 used as a work area of the CPU 61, the DRAM 65 used as a temporary data storage area, and other peripheral circuits (not shown) such as an interrupt controller and an input / output circuit. It is coupled to the internal bus 67 and is formed on a single semiconductor substrate 1 such as silicon. The program memory is a programmable ROM such as an EPROM (Electrical Programmable Read Only Memory) in which the program can be changed, and a part of it is used as a read-only area R.
The OM portion is formed. In that case, the ROM section is not particularly limited, but it is used for storing programs such as microcomputer operation test programs that do not need to be rewritten, and the other EPROM sections are various tables needed for address calculation and the like. It is used to store and configure the required logic in a programmable manner.

FIG. 1 shows a configuration example of the program memory 63.

Reference numeral 50 denotes a memory cell array, which comprises a plurality of memory cells arranged in a matrix. Word lines W1 and W2 are representatively shown. Memory cells M1 to M4 are coupled to word line W1 and memory cells EM1 to EM4 are coupled to word line W2. Memory cells M1 to M
4 and memory cells EM1 to EM4 are FAMOS (f
loading gate avalanche in
injection MOS) structure. Word line W1
ROM section 3 by memory cells M1 to M4 coupled to
0 is formed, and this ROM section 30 is used to store a test program or the like that does not require rewriting, and basically overwrite of the stored content is prohibited. The word line W1 is driven to the selected level by the word driver 32. An X (row) decoder 31 for decoding row addresses Xpm and Xpn is arranged in front of the word driver 32, and the word line W1 is driven based on the output of the X decoder 31. The EPROM section 40 is formed by the memory cells EM1 to EM4 coupled to the word line W2. The word line W2 is driven to the selected level by the word driver 42. An X (row) decoder 41 for decoding the row addresses Xa and Xb is arranged in front of the word driver 42.
The word line W2 is driven based on the output of 1. E
The PROM unit 40 is used for storing various tables required for address calculation and the like, and for configuring required logic in a programmable manner. That is,
The ROM section 30 and the EPROM section 40 have the same data line D
1 to D4, and ROM by row address
The part 30 and the EPROM part 40 are used properly.

The data lines D1 to D4 are provided with a column selection signal YW generated by a column decoder (not shown).
It is coupled to the common data line CD via column selection switches T1 to T4 whose operations are controlled based on 1 to YW4. This common data line CD is VPP via a switch T5 which is turned on / off by a data input Din.
It is coupled to the output terminal of the (high voltage) supply circuit 10. VP
P indicates a high voltage for writing, which is a normal high potential side power source V
The potential is higher than CC. The VPP supply circuit 10
It includes a series circuit of a p-channel MOS transistor T7 and n-channel MOS transistors T8 and T9, and a p-channel MOS transistor T6 whose operation is controlled by a write reference gate voltage generated by the series circuit. p-channel MOS transistor T7
And a series circuit of n-channel type MOS transistors T8 and T9 are coupled to the high voltage VPP terminal and the low potential side power source VSS terminal, and the n-channel type MOS transistor T9 is connected.
An output signal WEROM * (* indicates low active) from the ROM section write detection circuit 20 is input to the gate electrode of the. ROM writing detection circuit 2
When the output signal WEROM * from 0 is asserted to the low level (low-potential-side power supply VSS level), the n-channel type MOS transistor T9 is turned off and the write reference gate voltage PGC is set to the high level so that the p-channel type. When the MOS transistor T6 is turned off, the high voltage V for writing to the n-channel type MOS transistor T5
PP transmission is blocked.

The ROM section write detection circuit 20 includes an RO
A 2-input NOR gate 21 for obtaining the NOR logic of the addresses Xpn and Xpm and the 2-input NOR gate 21 are used as a logic circuit for detecting the addressing of the M section 30, that is, the state of writing to the ROM section 30.
2 input NAND gate 22 for obtaining a NAND logic with the logical output of the NAND gate and the EPROM mode control signal epm indicating the EPROM mode, the logical output of the NAND gate 22 and the write enable signal W for instructing the write mode.
Two-input NAND gate 23 for obtaining NAND logic with E
And an inverter 24 that inverts its logic output. The logical output of the inverter 24 is used as the output signal WEROM * of the ROM section write detection circuit 20 and is transmitted to the VPP supply circuit 10.

FIG. 2 shows a truth table of the circuit of this embodiment.

In the above structure, E is set at the time of writing operation.
The PROM mode control signal epm and the write enable signal WE are set to the high level. In this state, when the addresses Xpn and Xpm are both set to the low level, the output signal WEROM * of the ROM section write detection circuit 20 is set to the high level because the ROM section 30 is in the non-selected state. Thus, when the output signal WEROM * is at a high level, the n-channel type MOS of the VPP supply circuit 10 is
Since the transistor T9 is in the ON state and the write reference gate voltage PGC is set to the low level, the p-channel MOS transistor T6 is turned on,
The VPP can be supplied to the common data line CD via the n-channel MOS transistor T5. That is,
Writing to the EPROM unit 40 is enabled.

On the other hand, when either or both of the addresses Xpn and Xpm become high level, the ROM
When the section 30 is selected, the logical output of the NOR gate 21 becomes the low level, and the output signal WEROM * of the ROM section write detection circuit 20 is asserted to the low level. Therefore, the n-channel MOS transistor of the VPP supply circuit 10 is selected. Since T9 is cut off and the write reference gate voltage PGC is set to the high level, the VPP supply to the common data line CD is stopped. Since the VPP supply to the common data line CD is stopped in this way, even if the ROM section 30 is erroneously addressed in the write mode, the contents stored in the ROM section 30 will not be rewritten. That is, in the write mode, the ROM section 30 is erroneously input due to an erroneous input of an address signal or a circuit malfunction.
Even when is selected, undesired writing is not performed in the ROM section 30.

According to the above embodiment, the following operational effects can be obtained.

(1) According to the prior art, the write voltage supply circuit for supplying the write voltage to the memory cell is controlled independently of the address input signal, and the ROM section and the EPROM section are formed on the same data line. In this case, a write voltage is applied to the data line selected by the column selection switch.At this time, if the ROM section is selected due to an erroneous input of an address signal or a circuit malfunction, it is originally read-only. In contrast to the undesired writing in a certain ROM section, which causes the contents stored in the ROM section to be rewritten, in the present embodiment, the ROM section write detection circuit 20 detects the ROM section write. As a result, when WEROM * is asserted to a low level, VPP from the VPP supply circuit 10 to the common data line is
By stopping the supply, undesired VPP supply and writing to the ROM section 30 are prohibited.

(2) Due to the action and effect of (1) above, RO
Since the undesired VPP supply to the M section 30 is prohibited, it is possible to prevent the breakdown voltage of the memory element from deteriorating.
It is possible to improve the reliability of the program memory and further the single-chip microcomputer including the program memory.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, in the above embodiment, the supply of the write voltage to the data line is controlled, but the application of the high voltage for write to the ROM section 30 from the word line direction may be controlled. 3 and 4, the word driver 32A on the ROM section 30 side and the EPROM section 40 in that case.
The configuration of the word driver 42A on the side is shown.

In FIG. 3, p-channel type MOS transistors T11 and T12 are connected in series to form an inverter INV1.
The output of V1 is the p-channel MOS transistor T10.
It is designed to be fed back to the input side via. The power supply on the high potential side of the inverter INV1 is normally VCC which is a read voltage. X decoder 3 shown in FIG.
When one of the outputs of 1 is indicated by XD1, this X
D1 is input to the inverter INV1. The output of the inverter INV1 is supplied to the word line of the ROM section 30. In addition, in FIG. 4, the p-channel MOS transistors T14 and T15 are connected in series to form an inverter INV2.
The output of NV2 is the p-channel MOS transistor T1.
It is adapted to be fed back to the input side via 3. The high-potential-side power source of the inverter INV2 is set to VPP1 obtained by boosting the write high voltage VPP or unboosted VPP. When one of the outputs of the X decoder 41 shown in FIG. 1 is indicated by XD2, this XD2 is input to the inverter INV2. The output of the inverter INV2 is supplied to the word line of the ORM section 30. In addition, RO
When the word driver 32A on the M section 30 side and the word driver 42A on the EPROM section 40 side are configured as described above, the high voltage supply for writing from the data line is unnecessary.

The power source of the word driver on the ROM side shown in FIG. 3 is set to the high voltage VPP as in the EPROM section.
1 or VPP may be considered, and even in such a case, the supply of the high voltage VPP1 or VPP can be controlled based on the output of the ROM section write detection circuit 20 as shown in FIG. By doing so, it is possible to obtain the same effect as in the case of the above embodiment. That is, when the ROM section is selected, the RO
Based on the output of the M section write detection circuit 20, the high voltage VPP
The supply of 1 or VPP to the ROM section is blocked. High voltage V
When there is a booster circuit for boosting PP to generate VPP1, the booster circuit is controlled based on the output of the ROM detection circuit 20 so that the high voltage VP is output from the circuit.
Instead of P1, Vcc which is a normal read voltage can be output.

Further, even in the case where the method of supplying the high voltage for writing to the data line and the method of supplying the high voltage for writing to the word line are combined as in the case of the above embodiment, the above embodiment As described above, it is possible to detect the writing to the ROM section and prevent the high voltage supply thereto.

In the above description, the case where the invention made by the present inventor is mainly applied to the program memory mounted in the single-chip microcomputer which is the background field of application has been described, but the present invention is not limited thereto. It is not a thing, but a semiconductor memory provided as a single LSI, electrically writable / erasable EEP
It can be widely applied to ROM (Electrically Erasable and Programmable Read Only Memory), PLD (Programmable Logic Device), and various semiconductor integrated circuits in which such elements are on-chip. it can.

The present invention can be applied on condition that it includes at least an electrically writable storage element.

[0031]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, when the read-only area is addressed in the write mode to the memory cell array, by blocking the high voltage supply to the read-only area, the write to the read-only area is blocked. Appropriate application of a high voltage for writing in a semiconductor memory device in which a part of a memory cell array including electrically writable memory elements is used as read only, and reliability of the semiconductor memory device is thereby improved. Improvement is achieved.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a program memory included in a single-chip microcomputer according to an embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of the program memory.

FIG. 3 is a circuit diagram of another configuration example of a main part of the program memory.

FIG. 4 is a circuit diagram of another configuration example of the main part of the program memory.

FIG. 5 is a configuration block diagram of a single-chip microcomputer according to an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 semiconductor substrate 10 VPP supply circuit 20 ROM part write detection circuit 30 ROM part 31 X decoder 32 word driver 32A word driver 40 EPROM part 41 X decoder 42 word driver 42A word driver 50 memory cell array 61 CPU 63 program memory 65 DRAM 66 SRAM 67 Internal bus

Front Page Continuation (72) Inventor Michio Fujimoto 5-20-1, Josui Honcho, Kodaira-shi, Tokyo Inside Hitate Cho-LS Engineering Co., Ltd. (72) Inventor Kenichi Ishibashi, Kodaira-shi, Tokyo 5-20-1 Honmachi, Hitachi Ltd. Musashi Factory

Claims (4)

[Claims] 1. A semiconductor memory device in which a part of a memory cell array including a memory element electrically writable by high voltage supply is used as a read-only memory, and the read-only area is used in a write mode to the memory cell array. A semiconductor memory device including a control circuit for blocking a high voltage supply to the read-only area when addressed. 2. The semiconductor memory device according to claim 1, wherein the memory cell is formed by arranging FAMOS-structured transistors in a matrix, and the read-only area can be designated by a row address. 3. The semiconductor memory device according to claim 1, wherein the control circuit includes a logic circuit for detecting addressing of the read-only area by a row address monitor. 4. A microcomputer formed on one semiconductor substrate and having the semiconductor memory device according to claim 1, 2 or 3 mounted thereon.