JPH06112846A - Error signal correction device - Google Patents

Abstract

PURPOSE:To obtain an error signal correction device incapable of error correction after demodulation due to an evident error in a modulation signal is prevented. CONSTITUTION:A device is provided with a 1st error correction execution means 5 receiving a (2, 7) RLL signal subject to modulation in a prescribed way, detecting a signal inhibit pattern and correcting it, a demodulation means 11 receiving the corrected modulation signal and demodulating it, and a syndrome calculation means 21 receiving the demodulated signal and calculating the syndrome depending on an error in the signal, and also with an error polynomial calculation means 31 calculating an error location polynomial and an error numeral polynomial from the calculated syndrome, an error location detection means 41 calculating a root of the calculated error location polynomial and detecting an error location, and a 2nd error correction execution means 51 executing the correction of an error at a detected error location. After the 1st error location detection means 41 receives a signal subject to prescribed modulation, the error location detection means 41 detects an evident error in the signal and corrects the error.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error signal correction device used for correcting an error signal when reproducing information such as an optical disk device, a magneto-optical disk device, and a DAT (digital audio tape recorder).

[0002]

2. Description of the Related Art As such an error signal correction apparatus, there is a conventional one as shown in FIG. In the figure, reference numeral 10 is a (2,7) demodulation circuit, 20 is a syndrome calculation circuit, 30 is a Euclidean arithmetic circuit, 40 is a Chien search circuit, and 50 is an error correction execution circuit.

In an information reproducing apparatus such as a magneto-optical disk device, a Reed Solomon (RS) code is generally used to correct an error in read data.
This Reed-Solomon code is, for example, 8 bits (1 byte)
Is a type of byte error correction code in which several symbols are coded as one block and error correction is performed in symbol units.

A reproduction signal read from a recording medium such as a magneto-optical disk and modulated by (2,7) RLL modulation or the like is
In the (2, 7) demodulation circuit 10, the NRZ (Non Re
turn To Zero signal, and the demodulated NRZ signal is input to the syndrome calculation circuit 20.

The demodulated signal input to the syndrome calculating circuit 20 is encoded into an RS (Reed Solomon) code having a format as shown in FIG. In the figure, 100
-1 to 100-5 are interleaved, SYNC is a sync code, Do to Dn are byte data (DATA)
(Information signal) and RS are resynchronization codes. Further, after the byte data Do to Dn, a redundant part (ECC) (redundant signal) used for calculating an error check is added. As shown in the figure, the data recording direction,
The error correction directions are perpendicular to each other, and the byte data Do to Dn include five interleaves 100-1 to 100-1.
It is divided into 100-5, and correction is performed for each interleave at the time of correction.

The syndrome calculating circuit 20 calculates the syndrome from the input signal encoded into the RS code. This syndrome is a value that depends only on an error such that a predetermined polynomial is calculated using each RS-coded signal and the predetermined polynomial becomes 0 (zero) if there is no error in each signal. Is. And this syndrome is regarded as an element of the Galois field which is an aggregate consisting of a finite number of elements, and makes good use of such properties of the Galois field.

Although the above-mentioned syndrome pattern has a one-to-one correspondence with the combination of the error position and the error size, it is very difficult to directly determine the error position and the error size from the syndrome pattern. . Therefore, when the syndrome calculated by the syndrome calculation circuit 20 is not 0, the Euclidean arithmetic circuit 30 obtains the error locator polynomial and the error number polynomial from the calculated syndrome by using the Euclidean algorithm. The error locator polynomial has only information about the error position, and the error value polynomial is a polynomial including the error value.

The error locator polynomial obtained by the Euclidean algorithm is a polynomial whose root is an element of the Galois field which has a one-to-one correspondence with the error position. Therefore, by substituting the elements of the Galois field into the error locator polynomial in order and checking whether it becomes 0, the element corresponding to the error position can be known. In order to perform this sequentially, the Chien search circuit 40 sequentially finds the root by using the Chien search algorithm.

Finally, based on the error locator polynomial and the error value polynomial, the error correction execution circuit 50 obtains the magnitude of the error at the error position obtained by the Chien search circuit 40, and executes the correction, The error correction execution circuit 50 outputs the corrected data.

[0010]

However, the above conventional error signal correction apparatus has the following problems. Among the error correction codes, the Reed-Solomon code has a strong byte error correction capability. However, for example, a large defect on a medium such as an optical disk may not be error-corrected. For example, (2,7) before demodulation by the (2,7) demodulation circuit 10
When the RLL modulation signal has a pattern that violates a predetermined rule due to the above-mentioned defects or the like, this may cause (2, 7) demodulation circuit 10 to make it impossible to perform error correction after decoding into a Reed-Solomon code. May occur. Then, this invention makes it a subject to solve the said problem.

[0011]

In order to solve the above problems, the present invention provides a first error correction executing means for inputting a predetermined modulated signal and detecting and correcting an inhibition pattern of the signal, and the above correction. Demodulation means for inputting the demodulated modulated signal and demodulating, syndrome calculation means for receiving the demodulated signal and calculating a syndrome depending on the error of the signal, and an error locator polynomial and an error from the calculated syndrome Error polynomial calculation means for calculating a numerical polynomial, error position detection means for calculating a root of the calculated error position polynomial to detect an error position, and a second error for correcting an error at the detected error position And a correction execution means.

[0012]

According to the error signal correction device having such a configuration,
When the first error correction execution means has a pattern (prohibition pattern) which is not expected to have after the input of the predetermined modulated signal and which is not expected to have the predetermined rule,
The prohibited pattern is detected and corrected. Therefore, it is possible to prevent the error correction after demodulation from being impossible due to an apparent error in such a modulated signal.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram showing an embodiment of an error signal correction apparatus according to the present invention. In the figure, reference numeral 5
Is a (2,7) correction circuit (first error correction execution means), 11
Is a (2, 7) demodulation circuit (demodulation means), 21 is a syndrome calculation circuit (syndrome calculation means), 31 is a Euclidean arithmetic circuit (error polynomial calculation means), 41 is a Chien search circuit (error position detection means), and 51 is An error correction execution circuit (second error correction execution means).

The (2, 7) demodulation circuit 11, the syndrome calculation circuit 21, the Euclidean arithmetic circuit 31, the Chien search circuit 41, and the error correction execution circuit 51 each constitute the conventional error signal correction device (2, 7). ) Demodulation circuit 1
0, the syndrome calculation circuit 20, the Euclidean arithmetic circuit 30, the Chien search circuit 40, and the error correction execution circuit 50 have the same configuration and operation. On the other hand, (2,7)
The correction circuit 5 is a new element which has not been present in the conventional error signal correction apparatus, and constitutes a characteristic part of this embodiment.

First, a (2,7) modulated signal, which is a reproduction signal read from a recording medium such as a magneto-optical disk and modulated by (2,7) RLL modulation, is first (2,7) correction circuit 5. Entered in. Here, the (2, 7) modulated signal is as shown in FIG.
As shown in, the variable length code is converted from 2 digits to 4 digits, 3 digits to 6 digits, and 4 digits to 8 digits, and "1" bit and "1" in the converted codeword string It is regulated that the number of consecutive "0" bits appearing between the bit and the bit is 2 at the minimum and 7 at the maximum including the connection part of the code word.
(2, 7) is a symbol representing this meaning, and this modulation method is a method with excellent bit storage efficiency.

For example, as can be seen from FIG. 2, the data word "10" has the modulation code word "0100" and the data word "01".
The modulation code word of "0" is "100100", and when the data words "10" and "010" are modulated successively, the modulation code word is "0100100100", which is "1",
The number of consecutive "0" s between "1" s is two. On the other hand, when the data words “011” and “0011” are successively modulated, the modulation code word is “001000000001”.
000 ”, and the number of consecutive“ 0 ”s between“ 1 ”and“ 1 ”is 7.

When any of the data words in FIG. 2 are combined and continuously modulated, the number of consecutive "0" s between "1" s and "1" s in the modulation codeword does not become less than two. There will be no more than seven. Therefore, (2,7)
In the modulated signal (modulation codeword), "11",
Patterns such as "101" and "00000000" cannot exist, and these can be defined as prohibited patterns.

When the (2,7) correction circuit 5 to which the reproduction signal modulated by the (2,7) RLL modulation is input, detects whether there is the above inhibition pattern, and when the inhibition pattern exists. Corrects the modulation signal so that the prohibited pattern becomes an originally proper pattern. For example, "1
In the case where the modulation codeword includes the prohibited pattern “11” like “100100100”, the above-mentioned “010” is included.
It is presumed that the error is "0100100" and the first "1" is corrected to "0".

In this way, by correcting the prohibited pattern existing in the signal related to the (2,7) RLL modulation into a pattern considered to be proper, an error made after demodulation described later due to the existence of the prohibited pattern. It is possible to prevent the correction from becoming impossible. The reproduction signal related to the (2,7) RLL modulation in which the prohibition pattern is corrected in this way is input to the (2,7) demodulation circuit 11 and
7) The demodulated signal demodulated by the demodulation circuit 11 is input to the syndrome calculation circuit 21.

The signal input to the syndrome calculating circuit 21 is encoded into an RS (Reed Solomon) code having a format as shown in FIG. 4, as in the conventional case. In the figure, 100-1 to 100-5 are interleaved, SYNC is a sync code, and Do to Dn are byte data (D).
ATA (information signal) and RS are resynchronization codes. Further, after the byte data Do to Dn, a redundant part (ECC) (redundant signal) used for calculation of an error check.
Has been added. As shown in the figure, the data recording direction and the error correction direction are perpendicular to each other.
Byte data Do to Dn are 5 interleaved 100
It is divided into -1 to 100-5, and correction is performed for each interleave at the time of correction.

The syndrome calculating circuit 21 calculates the syndrome from the input signal encoded into the RS code. When the syndrome calculated by the syndrome calculating circuit 21 is not 0, an error has occurred in the input signal. Therefore, the Euclidean arithmetic circuit 31 uses the Euclidean algorithm to calculate the error locator polynomial and the error value from the calculated syndrome. Find the polynomial.

Since the error locator polynomial obtained by the Euclidean algorithm is a polynomial whose root is an element of the Galois field corresponding to the error position one by one, the elements of the Galois field are substituted into the error locator polynomial in order. By checking whether it becomes 0, the element corresponding to the error position can be known. In order to perform this sequentially, the Chien search circuit 41 sequentially finds the root using the Chien search algorithm.

When the Chien search circuit 41 completes the Chien search, the magnitude of the error at the error position obtained by the Chien search circuit 41 is determined based on the error locator polynomial and the error numerical polynomial obtained by the Euclidean arithmetic circuit 31. The correction execution circuit 51 obtains the correction, executes the correction, outputs the corrected data, and ends the error correction.

In the above embodiment, the case where the Reed-Solomon code is used as the error correction code has been described, but the present invention may be applied to the case where an error correction code other than the Reed-Solomon code is used.

[0025]

As described above, according to the present invention, after the first error correction execution means inputs a predetermined modulated signal, the first error correction execution means follows a predetermined rule that the signal is not expected to have. It is designed to detect and correct a contradictory prohibited pattern. Therefore, it is possible to prevent the error correction after demodulation from being impossible due to an apparent error in such a modulated signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an error signal correction device according to the present invention.

FIG. 2 is a diagram showing a relationship between a data word before modulation and a modulation code word after modulation in the (2,7) modulation method.

FIG. 3 is a block diagram showing a conventional error signal correction device.

FIG. 4 is a diagram showing an example of a data format used in a storage medium such as a magneto-optical disk.

[Explanation of symbols]

 5 (2,7) Correction Circuit 11 (2,7) Demodulation Circuit 21 Syndrome Calculation Circuit 31 Euclidean Operation Circuit 41 Chain Search Circuit 51 Error Correction Execution Circuit

Claims (1)

[Claims] 1. A first error correction execution means for inputting a predetermined modulated signal and detecting and correcting an inhibition pattern of the signal, a demodulation means for inputting and demodulating the corrected modulated signal, A syndrome calculating means for inputting a demodulated signal and calculating a syndrome depending on an error of the signal; an error polynomial calculating means for calculating an error locator polynomial and an error value polynomial from the calculated syndrome; and the calculated An error signal comprising: an error position detecting means for calculating a root of an error locator polynomial to detect an error position; and a second error correction executing means for executing an error correction at the detected error position. Correction device.