JPH06112798A - Level conversion circuit - Google Patents

Abstract

PURPOSE:To simplify the production process, to reduce the cost by devising the circuit constitution and to eliminate a need of the Schottky barrier diode(SBD) which prevents oversaturation of a bipolar transistor TR. CONSTITUTION:This circuit converts an input signal Sin, which has a logical amplitude within the potential difference between a first potential V1 and a second potential V2, to an output signal having a logical amplitude within the potential difference between a third potential V3 and the first potential V1 and is provided with a switch means N2, a first bipolar TR Q1 which controls the magnitude of a current, a voltage generating means R1, and a signal generating means P1, and the base and the collector of the first bipolar TR Q1 are connected to a power line of the first potential V1 through second and third bipolar TRs Q2 and Q3, and bases of second and third bipolar TRs Q2 and Q3 are connected with the power line of the first potential V1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level conversion circuit, for example, a pseudo CMOS level (V _DD : 0V / V _SS :
The present invention relates to a level conversion circuit that performs level conversion from (negative potential) to a CMOS level or level conversion from the pseudo CMOS level to a TTL level, and relates to a level conversion circuit intended to reduce manufacturing cost and manufacturing man-hours.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram of a conventional level conversion circuit. In this figure, V ₁ is a first potential having a potential (0 V) corresponding to the common level of S _in and S _out , and V ₂ is a _second potential having a potential (−5 V) corresponding to the L level of S _in . The potential V ₃ is the potential (+5) corresponding to the H level of S _out.
V) is the third potential. Further, S _in is an input signal having a logical amplitude within the potential difference between the potential of V _{1 and} the potential of V ₂ (for example, H level is 0 V and L level is −5 V for convenience), and S _out is An output signal having a logical amplitude within a potential difference between the potential of V _{3 and} the potential of V ₂ (for example,
For convenience, the H level is + 5V and the L level is 0V). Further, P ₁ is a p-channel type MOS transistor, N ₁ and N ₂ are n-channel type MOS transistors,
Q ₁ is an npn type bipolar transistor, R ₁ and R ₂
Is a resistance element, D ₁ is a Schottky barrier diode (SB
D: Schottky barrier diode).

When S _in is at L level (-5V), N
₂ is turned off and the collector current I _{C1 of} Q ₁ does not flow, so that the potential of the node A becomes V ₃ and P ₁ is turned off and N
₁ is turned on. Therefore, S _out in this case is V ₁
It becomes a considerable L level (0V). On the other hand, when S _in is at the H level (0 V), N ₂ is turned on and the collector current I _{C1 of} Q ₁ flows, so that the potential of the node A changes from V ₃ to R _3.
The potential becomes lower by a voltage drop of ₁ (proportional to I _C1 ). Therefore, since P ₁ is on and N ₁ is off, S _out in this case becomes an H level (+5 V) corresponding to V ₃ .

Here, D ₁ is Q ₁ when N ₂ is on.
The collector potential (potential of the node A) of V ₁ -V _FD1 (where V _FD1 : Schottky junction forward voltage; generally 0.4 V to 0.6 V) is clamped, and Q ₁
This is to prevent "oversaturation (collector potential <base potential)". This is because when a bipolar transistor is used in supersaturation, the transition from on to off is delayed due to the accumulation of base charge.

[0005]

However, in such a conventional level conversion circuit, since the Schottky barrier diode (SBD) is formed in addition to the MOS transistor and the bipolar transistor, the manufacturing process is complicated. Therefore, there is a problem that the cost increases. [Purpose] Therefore, an object of the present invention is to realize a low-cost level conversion circuit by devising the circuit configuration to eliminate the need for a Schottky barrier diode (SBD), thereby simplifying the manufacturing process.

[0006]

In order to achieve the above object, the present invention provides an input having a logical amplitude within a potential difference between a first potential and a second potential lower than the first potential. The signal is transmitted to the third potential higher than the first potential and the first potential.
A level conversion circuit for converting into an output signal having a logical amplitude within a potential difference between the third potential and the third potential when the input signal is in the on state. Switch means for forming a current path to the second potential, and a first bipolar transistor for controlling the magnitude of the current flowing in the current path according to the first potential,
In the level conversion circuit, comprising: a voltage generating unit that generates a voltage proportional to a current flowing in the current path; and a signal generating unit that generates the output signal from the voltage generated by the voltage generating unit. The base and collector of the bipolar transistor are connected to the power supply line of the first potential through the second and third bipolar transistors, respectively, and the bases of the second and third bipolar transistors are connected to the first It is characterized in that it is connected to a power supply line having a potential of.

[0007]

In the present invention, when the switch means is in the ON state,
The base potential and collector potential of the first bipolar transistor are higher than the first potential, respectively, and the base-emitter voltage of the second and third bipolar transistors (forward voltage of the pn junction; generally 0.8 V to 1.0 V). Only clamped to a lower potential. Therefore, the potential difference between the base and collector of the first bipolar transistor becomes almost zero, and oversaturation of the first bipolar transistor is prevented. That is, the Schottky barrier diode (SB
An effect equivalent to that of providing D) is obtained.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 3 are diagrams showing an embodiment of a level conversion circuit according to the present invention. The same circuit elements as those in the conventional example are designated by the same reference numerals. In FIG. 1, S _in is V
An input signal having a logical amplitude within a potential difference between the potential of _{1 and} the potential of V ₂ , for example, the H level of S _in is 0.
The V and L levels are -5.2V. Also, S _out is V
An output signal having a logical amplitude within a potential difference between the potential of _{3 and} the potential of V ₂ , and for example, the H level of S _out is +
5V, L level is 0V.

V _{1 to} V ₃ are power supply voltages given from the outside, V ₁ has a potential (0 V) corresponding to the common level of S _in and S _out , and V ₂ corresponds to the L level of S _in. It has a potential (-5.2 V), and V ₃ has a potential (+5 V) corresponding to the H level of S _out . Note that L
₁ is a power supply line of V ₁ , L ₂ is a power supply line of V ₂ , and L ₃ is a power supply line of V ₃ .

A p-channel type MOS is provided between L ₃ and L _1.
The transistor P ₁ and the n-channel type MOS transistor N ₁ are connected to each other. These transistors P ₁ and N ₁ are a transistor P ₁ and a transistor N _1.
An inverter gate having an input threshold value determined by the size of S is formed, and when the potential of a node A described later exceeds the threshold value, P ₁ is turned off and N ₁ is turned on, and S
_While the potential of _out is equivalent to V ₁ (0V), when the potential of the node A does not exceed its threshold value, P ₁ is turned on,
N ₁ is turned off, and the potential of S _out is set to V ₃ (+ 5V). Therefore, these transistors P ₁ and N ₁ function as signal generating means for generating the output signal S _out from the voltage generated by the resistor R ₁ as the voltage generating means described below.

A resistor (voltage generating means) is provided between L ₃ and L _2.
R ₁ and npn type bipolar transistor (first bipolar transistor) Q ₁ , resistor R ₂ and n channel type MOS transistor N ₂ are connected in a connectable and disconnectable manner, and when S _in becomes H level, N ₂ is turned on to form a flow path of a current (collector current I _{C1 of} Q ₁ ) flowing from L ₃ to L ₂ . Therefore, N ₂ functions as the switch means described in the gist of the invention, and when N ₂ is off, the potential of the node A between the resistors R ₁ and Q ₁ is equivalent to V ₃ (approximately +5 V). , N ₂ is on, the potential of the node A is set to a potential lower than V ₃ by the voltage drop of R ₁ (proportional to I _C1 ).

Where Q₁The base is an npn type bipolar
Error transistor (second bipolar transistor) Q
₂Through L₁Connected to Q₁N collector
pn-type bipolar transistor (third bipolar transistor
Langista) Q₃Through L ₁Which is connected to
Al Q₂, Q₃Both bases are L₁It is connected to the.

Therefore, Q₂Emitter (Q₁The ba
S) potential is V₁Than V_BE2(V_BE2; Q₂Base of
Forward voltage of pn junction between emitters: 0.8 V to 1.0
V) clamped to a lower potential, and Q₃Emi of
(Q₁Collector) potential is V₁Than V
_BE3(V_BE3; Q₃Order of base-emitter pn junction
Directional voltage; = V _BE2) Is only clamped to a lower potential
Q₁The base potential and collector potential of the
Schottky barrier diode (SBD)
Q without using₁Oversaturation (base potential>
Potential) can be prevented.

2 and 3 are manufacturing process diagrams of a conventional example shown for comparison. According to the present embodiment, a portion related to the SBD in the process can be omitted, so that at least the cost can be reduced. You can First Step [Step of FIG. 2 (a)] First, a silicon substrate 1 of one conductivity type (for example, p conductivity type) for forming each element is prepared, and the second step [FIG. 2 (b)] Step] By implanting a p-type impurity (for example, B) or an n-type impurity (for example, As) into the element formation region of the substrate 1, p
The implantation region of the type impurities is used as a formation region of the n-channel type MOS transistor (N ₁ or N ₂ ), and the implantation region of the n-type impurities is used as the p-channel type MOS transistor (P ₁ ).
Area or Schottky barrier diode (SBD)
The creation area of

Then, the buried layer 2 of the p-channel MOS transistor, the buried layer 3 of the n-channel MOS transistor, the buried layer 4 of the SBD, and the epi layer 5 are formed by epitaxial growth, and the third step [FIG. ) Process] Impurities (for example, As) of the opposite conductivity type (here, n type) to the substrate 1 are implanted into a p-channel MOS transistor or SBD formation region, and an n-channel MOS transistor formation region is formed. The same conductivity type as the substrate 1 (here, p
Type impurities (for example, B) are implanted.

Then, by diffusion, n for each element region is obtained.
Form wells 6 and 7, p-type well 8 and then heat acid
Field oxide film was grown on the substrate 1 by chemical method
After that, a thick oxide film 9 is formed on the element isolation region by the LOCOS method.
To form.Fourth step [step of FIG. 2 (d)] Gate oxide film 1 of MOS transistor by thermal oxidation method
After forming 0 and 11, the gate oxide films 10 and 11
A gate electrode made of polysilicon, polycide, etc.
Form poles 12, 13.Fifth step [step of FIG. 3 (a)] Next, the p-channel MOS transistor fabrication area
Source / drain part and guard ring part of SBD creation area
LDD (Lightly Doped Drain) structure is formed on each
Low-concentration p-type impurities (for example, B) 14, 15
Of the n-channel MOS transistor.
LDD structure is also formed on the source / drain part of the formed region
Inject low concentration n-type impurities (eg As) 16
To enter. Sixth step [step of FIG. 3 (b)] After forming the oxide film by the CVD method, the anisotropic
Etching is performed, and the sidewalls of the gate electrodes 12 and 13 are etched.
D-walls 17 and 18 are formed, and then p-channel type
Source / drain section of MOS transistor fabrication area
And the LDD structure in the guard ring part of the SBD creation area.
High-concentration p-type impurities (for example, B) 1 for forming a structure
Injecting 9, 20 and n-channel MOS transistor
The LDD structure is also used for the source / drain part
Concentration n-type impurities (eg As) for forming structures
Inject 21.Seventh step [step of FIG. 3 (c)] After forming an oxide film by the CVD method, for example, a PSG film
Growth is performed to form a bulk insulating film 22, and a MOS transistor is formed.
Contact hoses for each of the transistor and SBD formation areas
23 to 27 are formed.Eighth step [step of FIG. 2 (d)] The contact hole 2 in the SBD formation region is formed by the PVD method.
7. Barrier metal (eg Ti) 28 and wiring metal 29 on 7
Sputtering is used to form SBD electrodes and wiring electrodes.
By the PVD method, the area of the MOS transistor formation area is
Barrier metal 30 and wiring gold in contact holes 23 to 26
Sputter metal elements 31-34 to form wiring electrodes and complete
It

The above is the process of manufacturing the conventional level conversion circuit on the common substrate. According to the present embodiment, SB is used.
Since the circuit configuration does not require the D element, it is possible to omit the step of forming the wiring electrode of the SBD element, which is different from the formation of the wiring electrode of the other element, for example, in order to obtain desired characteristics in the above steps. However, the cost can be reduced accordingly.

Incidentally, in order to improve the controllability of the characteristics of the SBD element, the formation of the guard ring layer of the SBD may be carried out as an independent separate step. However, according to this embodiment, naturally the separate step itself is formed. It can be unnecessary. Further, since the number of elements to be formed on the common substrate is reduced, the controllability of other elements is improved, and it is possible to expect improvement in yield.

[0019]

According to the present invention, since the Schottky barrier diode (SBD) is not required by devising the structure, the manufacturing process can be simplified and a low cost level conversion circuit can be realized.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment.

FIG. 2 is a process diagram (1/2) of a conventional example.

FIG. 3 is a process diagram (2/2) of a conventional example.

FIG. 4 is a configuration diagram of a conventional example.

[Explanation of symbols]

I _C1 : Collector current (current) L ₁ : Power supply line N ₁ : N-channel type MOS transistor (signal generating means) N ₂ : N-channel type MOS transistor (switching means) P ₁ : P-channel type MOS transistor (signal generating means) ) Q ₁ : npn bipolar transistor (first bipolar transistor) Q ₂ : npn bipolar transistor (second bipolar transistor) Q ₃ : npn bipolar transistor (third bipolar transistor) R ₁ : resistance (voltage generation) Means) S _in : input signal S _out : output signal V ₁ : first potential V ₂ : second potential V ₃ : third potential

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication location 9170-4M H01L 27/06 321 G 9170-4M 321 F (72) Inventor Shigenori Ichinose Kawasaki City, Kanagawa Prefecture 1015 Kamiodanaka, Nakahara-ku, Fujitsu Limited (72) Inventor Masahiro Iwamoto 2-1844 Kozoji-cho, Kasugai, Aichi Prefecture

Claims (1)

[Claims] 1. A first potential (V₁) And the first potential
(V₁) Lower second potential (V₂) And the potential difference between
An input signal having a logical amplitude within (S_in) Is the first potential (V₁) Higher third potential (V₃)
And the first potential (V ₁) And the logic swing within the potential difference between
Output signal with width (S_out) Level conversion times
The input signal (S_in) On / off depending on the logic state of
Then, in the ON state, the third potential (V₃) To second
Potential (V₂) Switch means (N
₂) And the current (I_C1) The size of the first
Potential (V₁) The first bipolar transistor controlled according to
Dista (Q₁) And the current (I_C1) Generates a voltage proportional to
Voltage generation means (R₁) And the voltage generating means (R₁From the voltage created by
Output signal (S_outSignal generating means (P)₁, N
₁), And the first bipolar transistor (Q₁) Base and
And collector to the second and third bipolar transistors, respectively.
Register (Q₂, Q₃) Through the first potential
(V₁) Power line (L₁) And the second and third bipolar transistors (Q₂,
Q₃) Is connected to the first potential (V₁) Power line
(L₁) Is connected to the level conversion circuit.