JPH06112440A - Semiconductor memory and manufacturing method thereof - Google Patents

Abstract

PURPOSE:To store four kinds of states in one planar cell structured memory cell. CONSTITUTION:Within a memory cell Tr1 in the first state, a channel region is not entirely implanted with core while within another memory cell Tr2 in the second state, both ends of the channel width are implanted with core thereby narrowing the channel width by about 1/3, furthermore, in the memory cell Tr3 in the third state, the central part of the channel width is implanted with core thereby narrowing the channel width by about 2/3. Likewise, within the memory cell Tr4 in the fourth state, the whole channel width is implanted with core. Accordingly, assuming the on-current in Tr1 to be 1d, the on-current in Tr2, Tr3, and Tr4 are respectively specified to be 21d/3, 1d/3 and 0.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type semiconductor memory device, and more particularly to a MOS type semiconductor memory device having a planar cell structure and a multi-valued memory, and a manufacturing method thereof.

[0002]

2. Description of the Related Art A memory cell structure of a mask ROM memory device currently in use is such that one bit is composed of one memory cell, and when the gate voltage of the memory cell transistor is set to a high potential, the source and drain of the transistor are formed. "1" and "0" of data, or "whether current flows between them"
Reading is performed in correspondence with the states of "0" and "1". There are various methods of writing data in the ROM, such as a field method, a depletion method, a core method, and a contact method. One bit corresponds to one memory cell.

The degree of integration of semiconductor memory devices is increasing year by year,
As a result, the area occupied by one memory cell has been reduced. In the case of a mask ROM, reducing the memory cell area means reducing the area of one memory transistor, and the memory cell has been reduced by always adopting the minimum design rule.

One epoch-making method for reducing the area of the memory cell portion is a memory cell structure called a planar structure (Japanese Patent Laid-Open Nos. 61-288464 and 63-9).
6953, etc.). In the planar cell structure,
Continuous diffusion regions for source regions of a plurality of MOS transistors and continuous diffusion regions for drain regions of a plurality of MOS transistors are alternately formed in parallel with each other on a substrate, and an insulating film is interposed on the substrate. As a result, a gate electrode intersecting both diffusion regions is formed. In the planar cell structure, it is not necessary to provide a field oxide film for element isolation, and since the source region and the drain region are shared by a plurality of transistors, the contact thereof is one for several or dozens of transistors. It is relatively easy and convenient for high integration. However, even in the planar cell structure, one bit corresponds to one memory cell.

Another method for reducing the area of the memory cell region is to increase the amount of information per memory cell by setting the current value flowing out from one memory cell to three or more values. One of the methods is to set the effective channel width to three or more types by performing core injection into the channel region (see Japanese Patent Laid-Open No. 59-148360). The proposed multi-valued memory employs a simple method of controlling the on-current between the source and drain to, for example, four values by using the core injection method.

[0006]

In the multi-valued memory by the core injection method, the on-current greatly varies due to the misalignment of the mask for core injection and the mask for the field oxide film, so that it has not been realized as a mass production process. . An object of the present invention is to provide a four-valued ROM adopting a planar cell structure and setting four kinds of ON currents in one memory cell.

[0007]

A semiconductor memory device according to the present invention has a planar cell structure in a first state in which each channel region is not core-injected at all, and the channel width is reduced by core-injecting at both ends of the channel width. The second state in which the channel width is narrowed to about 2/3, the core is injected into the central portion of the channel width and the third state in which the channel width is narrowed to about 1/3, the core is injected over the entire channel width. One of the four states that

In order to manufacture this semiconductor memory device,
According to the manufacturing method of the present invention, band-shaped diffusion regions parallel to each other are formed on a substrate, and a word line that also serves as a gate electrode is formed so as to be insulated from the diffusion regions and intersect the diffusion regions, and then, in the channel region. A first state without core injection, a second state in which core injection is applied to about 1/3 of the channel width, a third state in which core injection is applied to about 2/3 of the central portion of the channel width, and the entire channel width Of the fourth state of core injection, the second to fourth states are
The core injection process is performed once.

In the manufacturing method of the preferred embodiment, any of four states is formed in the channel region by including the following steps (A) to (C). (A) The memory in the fourth state in which core injection is performed over the entire channel width has an opening over the entire channel width, and is about 2/3 of the central portion of the channel width.
In the memory cell in the third state in which core injection is performed over the entire area, an opening having a width of about 1/3 of the channel width is formed in the central portion of the channel width, and the memory cell in the first state in which no core injection is performed and the channel width A step of forming a resist pattern to cover the memory cell in the second state in which about 1/3 of the core implantation is performed, and implanting core ions into the substrate from above the gate electrode using the resist pattern as a mask, (B) second The memory cell in the state 1 has a larger opening including the entire channel width, and the memory cell in the state 1 is
A step of forming a resist pattern to cover the memory cell in the third state and the memory cell in the fourth state, and using the mask as a mask to rotationally and obliquely implant core ions at low energy. (C) In the memory cell in the second state by diffusing the implanted ions, the channel width is narrowed to about 2/3,
In the memory cell in this state, a heat treatment process is performed so that the channel width is reduced to about 1/3. The steps (A) and (B) may be interchanged.

[0010]

In the first state, the core is not injected into the channel at all, so that the current flows over the entire channel width of the memory cell. This current value is used as a reference current. In the memory cell in the second state, the core is injected from both ends of the channel width to make the channel width about 2/3, and an on-current of about 2/3 of the standard current flows. In the third state, the core is injected into the central portion of the gate width, the gate width is set to about ⅓, and an ON current of about ⅓ of the standard current flows. In the memory cell in the fourth state, core injection is performed over the entire channel width, and no on-current flows. Thus, 2-bit information can be stored per memory cell. In the second state, core injection is performed by self-alignment by rotational oblique injection using the gate electrode as a mask, which is realized with good reproducibility.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows a four-valued memory cell in one embodiment. (A) is a plan view, (B) is a cross-sectional view taken along line BB ′ of (A), and (C) is CC ′ of (A).
It is sectional drawing in a line position. On the P-type silicon substrate 2, continuous N-type diffusion regions 4 for source regions of a plurality of memory cells and continuous N-type diffusion regions 6 for drain regions of a plurality of memory cells are alternately formed in parallel with each other. Has been done. The drain diffusion region 6 serves as a bit line to which the sense circuit is connected, and the source diffusion region 4 serves as a ground line. A gate oxide film 8 is formed on the substrate surface between the diffusion regions 4 and 6, a silicon oxide film 10 thicker than the gate oxide film 8 is formed on the diffusion regions 4 and 6, and a gate oxide film is formed on the substrate. A word line 12 is formed in a direction intersecting the diffusion regions 4 and 6 at right angles through the oxide film 8 and the oxide film 10. Although not shown in the drawing, an interlayer insulating film is further formed, a contact hole is formed at a predetermined position, and the metal wiring on the interlayer insulating film is connected to each part.

The substrate surface below the word line 12 between the diffusion regions 4 and 6 becomes the channel region of each memory cell. Boron ions are implanted as core ions to write information in the memory cell. The core injection region is shaded. In the memory cell Tr ₁ in the first state, no core is injected into the channel region. Second
In the memory cell Tr ₂ in the state of, the core width is narrowed to about 2/3 by core injection from both ends of the channel width.
In the memory cell Tr ₃ in the third state, the core is injected into the central portion of the channel width to reduce the channel width to about 1/3. In the memory cell Tr ₄ in the fourth state, core injection is performed over the entire channel width.

Here, as an example of the material and thickness, the gate oxide film 8 has a thickness of about 500 Å and the silicon oxide film 10 has a thickness of
Is 1000 to 2000Å and the word line 12 is 2000 to 4000Å and is a polycrystalline silicon film having a low resistance due to introduction of impurities.

When the on-state current in the memory cell Tr ₁ in the _first state is the standard current Id, the memory cell T in the second state is
Since the channel width of r ₂ is 2/3, the on-current is 2I
Since the channel width of the memory cell Tr ₃ in the third state becomes 1/3, the on-current becomes Id / 3,
Since the memory cell Tr _{4 in} the fourth state has the core injected into the entire channel, the on-current becomes 0. This realizes a four-valued memory.

Next, the manufacturing method of this embodiment will be described with reference to FIG. (A) A resist pattern for forming diffusion regions for band-shaped source regions and drain regions which are parallel to each other is formed on the surface of the P-type silicon substrate 2 by photolithography, and phosphorus or arsenic is ion-implanted using the resist pattern as a mask. A source region (ground line) and a drain region (bit line) are formed. Thereafter, the resist is removed, the substrate surface is oxidized to form a gate oxide film 8 on the substrate surface between the diffusion layers, and a silicon oxide film thicker than that is simultaneously formed on the diffusion layer by accelerated oxidation. . A low resistance polycrystalline silicon film is deposited to a thickness of 2000 to 4000 Å and patterned by photoengraving and etching to form strip-shaped word lines 12 in a direction orthogonal to the diffusion regions 4 and 6.

In order to perform core injection into the channel region, for the memory cell Tr _{4 in} the _fourth state, an opening a including the entire gate width of the memory cell and wider than that, and a memory cell in the third state. For Tr _3, a resist pattern 20 having an opening b having a width of about ⅓ of the channel width is formed in the central portion of the channel width of the memory cell, and boron ions are implanted using the resist pattern 20 as a mask. The implantation energy of boron is about 80 KeV, and the implantation amount is about 1 × 10 ¹³ / cm ² . Boron ions pass through the word line 12 and are implanted into the substrate surface.

(B) After removing the resist 20, a resist pattern 22 is formed again by photolithography, and the resist pattern 22 includes all the channel widths of the memory cells Tr _{2 in} the _second state, and more than that. It has a wide opening a. Boron ions are obliquely rotationally implanted using the resist pattern 22 as a mask. The implantation conditions at this time are as follows: implantation energy is about 30 KeV, inclination angle is 30 to 40 degrees, and implantation amount is about 1 × 10 ¹³ / cm ² . Boron ions are applied to the gate electrode 1 from both ends of the channel width of the memory cell Tr _2.
Also go into the lower part of the side of 2. By removing the resist 22 and then performing heat treatment, the implanted boron ions are diffused as shown in FIG. 1B to form the channel width in each state.

[0018]

According to the present invention, since the core injection is divided into the entire surface of the channel width, both ends and the center, four kinds of channel widths can be formed, and four kinds of information can be given to one memory cell. Therefore, information of 2 bits can be stored, and the storage capacity can be doubled.

According to the manufacturing method of the present invention, four kinds of states can be formed by performing the core injection twice, so that the core injection can be performed a small number of times. In order to form the second state in which the core implantation is performed at both ends of the channel region, if the impurities are implanted in a self-aligned manner by using the gate electrode as a mask at low energy by the rotational oblique implantation, the core implantation can be performed with good reproducibility. it can.

[Brief description of drawings]

1A and 1B show four kinds of memory cells in one embodiment, (A) is a plan view, (B) is BB 'of (A).
A sectional view taken along a line position, and (C) is a sectional view taken along a line CC 'in (A).

FIG. 2 is a cross-sectional view showing a core injection step in the manufacturing method of the embodiment.

[Explanation of symbols]

 2 P-type silicon substrate 4 Ground line 6 Bit line 8 Gate oxide film 12 Word line also serving as gate electrode 20, 22 Resist pattern

Claims (3)

[Claims] 1. A continuous diffusion region for a source region of a plurality of memory cells and a continuous diffusion region for a drain region of a plurality of memory cells are alternately formed in parallel with each other, and a word line is formed. Formed so as to be insulated from both diffusion regions and intersect with both diffusion regions, the substrate surface below the word line between both diffusion regions becomes the channel region of each memory cell, and each channel region is not core-injected at all. In the first state, core injection is performed at both ends of the channel width to narrow the channel width to about 2/3. In the second state, core injection is performed at the center of the channel width to reduce the channel width to about 1/3. A four-valued semiconductor memory device having either a narrowed third state or a core-injected fourth state over the entire channel width. 2. A band-shaped diffusion region parallel to each other is formed on a substrate, and a word line which also serves as a gate electrode is formed so as to be insulated from the diffusion region and intersect the diffusion region, and then a core is injected into the channel region. 1st state, 2nd state of applying core injection to about 1/3 of channel width, 3rd state of applying core injection to about 2/3 of the central part of channel width, and core injection over the entire channel width A method of manufacturing a four-valued semiconductor memory device in which the second to fourth states are divided into two core injection steps among the fourth states. 3. A band-shaped diffusion region parallel to each other is formed on a substrate, and a word line which also serves as a gate electrode is formed so as to be insulated from the diffusion region and intersect the diffusion region, and then the following step (A) is performed. To (C) and forming any of four states in a channel region. (A) Fourth in which core injection is performed over the entire channel width
In the memory in the state 1), the memory cell has an opening over the entire channel width, and in the memory cell in the third state in which the core injection is performed over about ⅔ of the central portion of the channel width, the memory cell in the third state has about 1 A memory cell having an opening with a width of / 3 and having a first state in which no core injection is performed and a memory cell in a second state in which core injection is performed to about 1/3 of the channel width form a resist pattern to be covered. Then, using the resist pattern as a mask, a step of implanting core ions into the substrate from above the gate electrode, (B) The memory cell in the second state has an opening including the entire channel width and larger than that, and A memory cell to be in a state, a memory cell to be in a third state, and a memory cell to be in a fourth state form a resist pattern to be covered,
Using the mask as a mask, a step of rotating diagonally implanting core ions at low energy. (C) The implanted ions are diffused so that the channel width is narrowed to about 2/3 in the memory cell in the second state, and the channel width is narrowed to about 1/3 in the memory cell in the third state. Heat treatment process.