JPH06112327A - Semiconductor device with multilayer interconnection structure and its manufacture - Google Patents

Abstract

PURPOSE:To provide a semiconductor device with a multilayer interconnection structure which can connect conductive layers at the same contact hole positions mutually and independently, increase the freedom for layout design of an integrated circuit, and achieve a high integration and then its manufacturing method. CONSTITUTION:In a semiconductor device with a multilayer interconnection structure where at least two conductive layers 16a, 16b, and 16c are laminated via interlayer insulation layers 14a, 14b, and 14c on a semiconductor substrate 2, a conductive side wall 20 for connecting two or more conductive layers and an insulation side wall 22 for insulating the conductive side wall 20 for a conductive plug 24 are formed inside the same contact holes, 18 formed in the conductive layers and the interlayer insulation layers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multi-layer wiring structure and a method of manufacturing the same, and more particularly, it is possible to independently connect conductive layers to each other at the same contact hole position, and to achieve high integration. The present invention relates to a method for manufacturing a semiconductor device that can be realized.

[0002]

2. Description of the Related Art A cross section of a contact hole used in a conventional semiconductor device is shown in FIG. As shown in the figure, the lower conductive layer 2 composed of an impurity diffusion layer of the semiconductor substrate, etc.
An interlayer insulating layer 4 and an upper conductive layer 8 are laminated on the upper surface, and the lower conductive layer 2 and the upper conductive layer 8 are connected through a contact hole 6. Upper conductive layer 8 is formed of a semiconductor layer such as polysilicon.

With further miniaturization, a semiconductor device having a single-layer connection structure as shown in FIG. 8 has been devised. In this semiconductor device, a plurality of conductive layers 8a and 8b are formed on the lower conductive layer 2.
Are laminated via the interlayer insulating layers 4a, 4b, 4c, the contact hole 6 is opened from the uppermost interlayer insulating layer 4c toward the lower conductive layer 2, and the conductive layer 8c is inserted so as to enter the contact hole 6. Form. With such a single-layer connection structure, all the conductive layers 4, 8a, 8b, 8c are conducted through the contact hole 6, and each layer can be set to the same potential.

[0004]

However, as the degree of integration or the three-dimensionalization of the semiconductor device further progresses, in the multilayer wiring structure, the upper conductive layer and the lower conductive layer are connected to each other. There is a need to insulate the conductive layers located in the middle or to connect only the conductive layers in the middle. The conventional contact holes shown in FIGS. 7 and 8 cannot satisfy such a need.

The present invention has been made in view of the above situation, and it is possible to connect the conductive layers to each other independently at the same contact hole position, thereby increasing the degree of freedom in the layout design of the integrated circuit and increasing the layout. An object of the present invention is to provide a semiconductor device having a multi-layer wiring structure that can be integrated and a method for manufacturing the same.

[0006]

In order to achieve the above object, the present invention provides a semiconductor device having a multilayer wiring structure in which at least two or more conductive layers are laminated on a semiconductor substrate through an interlayer insulating layer. , A conductive sidewall that connects two or more conductive layers in the same contact hole formed in the conductive layer and the interlayer insulating layer, and an insulating property that insulates the conductive sidewall from the conductive plug. The sidewall is formed.

The method for manufacturing a semiconductor having a multi-layer wiring structure according to the present invention comprises a step of alternately laminating two or more interlayer insulating layers and conductive layers on a semiconductor substrate, and the interlayer insulating layer and conductive layers. A step of forming a contact hole having a predetermined depth that does not reach the surface of the semiconductor substrate, a step of forming a conductive thin film layer so as to enter into the contact hole, and anisotropy of the conductive thin film layer. A step of forming a conductive sidewall connecting two or more conductive layers in the contact hole by etching, and an insulating thin film layer so that the conductive sidewall enters the contact hole in which the conductive sidewall is formed. And the bottom of the insulating thin film layer that has entered the contact hole is etched, and the insulating sidewall is formed on the inner peripheral side of the conductive sidewall. And a step of forming, a step of bottom to form a conductive plug in the contact hole etched.

The etching of the bottom of the insulating thin film layer that has entered the inside of the contact hole utilizes that the thickness of the insulating thin film layer deposited on the bottom is smaller than that of other portions,
The contact holes can be self-aligned. Alternatively, a resist film may be used. The conductive plugs are formed by polysilicon etchback, tungsten etchback, selective tungsten growth, or other methods.

[0009]

In the multi-layered semiconductor device of the present invention, the conductive side wall connecting two or more conductive layers in the same contact hole and the insulating side wall insulating the conductive side wall from the conductive plug. Since the side wall is formed, it is possible to connect arbitrary conductive layers in the same contact hole by using the conductive side wall and the insulating side wall in combination. As a result, the number of contacts as a whole can be reduced, the degree of freedom in the layout design of the integrated circuit is increased, and high integration can be achieved.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device having a multilayer wiring structure according to an embodiment of the present invention will be described in detail below with reference to the drawings. 1 is a cross-sectional view of an essential part of a semiconductor device having a multilayer wiring structure according to an embodiment of the present invention, FIGS. FIG. 9 is a cross-sectional view of a main portion of a semiconductor device having a multilayer wiring structure according to another embodiment of the invention.

As shown in FIG. 1, in a semiconductor device 10 having a multilayer wiring structure of this embodiment, two intermediate conductive layers 16a, 1 are formed on a semiconductor substrate 2 with interlayer insulating layers 14a, 14b interposed therebetween.
6b are laminated. An upper conductive layer 16c is laminated on the intermediate conductive layers 16a and 16b with an interlayer insulating layer 14c interposed therebetween.

The semiconductor substrate 2 is composed of, for example, a silicon wafer, an impurity diffusion layer is formed in a predetermined pattern, and a conductive region is formed on the surface thereof. The conductive layers 16a, 16b, 16c are not particularly limited, and are composed of a wiring layer laminated on the surface of the semiconductor device or a semiconductor region layer such as a TFT. Specifically, the conductive layer is composed of a single crystal silicon layer, a polysilicon layer, or a metal layer such as aluminum. In addition, the interlayer insulating layer 14a,
Although not particularly limited, 14b and 14c are, for example, a silicon oxide film, a silicon nitride film, a phosphorus-doped silicate glass film (PSG film), a boron-doped silicate glass film (BSG), an arsenic-doped silicate glass film (AsSG).
Membrane) etc.

In this embodiment, the same contact hole 1
8, the conductive sidewalls 20 are sequentially arranged from the outer peripheral side.
The insulating side wall 22 and the conductive plug 24 are formed. The conductive sidewall 20 is made of, for example, a polysilicon film. The insulating sidewalls 14a, 14b, 14c are made of the material exemplified as the interlayer insulating layer, for example. In addition, the conductive plug 24
May be simultaneously formed of the same material when forming the upper conductive layer 16c, but may be formed of another material. For example, tungsten formed by selective growth may be used.

A semiconductor device 10 having such a multilayer wiring structure.
2A, first, on the surface of the semiconductor substrate 2, the interlayer insulating layers 14a, 14b, 14c and the intermediate conductive layers 16a, 16 are formed on the surface of the semiconductor substrate 2 by the CVD method or the like.
Alternately stack b. Next, as shown in FIG.
A contact hole 18 having a predetermined depth that does not reach the surface of the semiconductor substrate 2 is formed by etching from the uppermost interlayer insulating layer 14c. In this embodiment, the contact holes 18 are formed in the intermediate conductive layers 16a and 16b in a self-aligned manner with respect to the contact holes formed in the insulating layer, and the surface of the lowermost intermediate insulating layer 14a is exposed. , Stop the etching.

Next, as shown in FIG. 3C, the conductive thin film layer 20a is CV so as to enter the contact hole.
It is formed by the D method or the like. The conductive thin film layer 20a is made of, for example, a polysilicon film. The film thickness of the thin film 20a is 1/2 or less of the width of the contact hole 18, and preferably 1/5 to 3/10. Next, as shown in FIG. 3D, the conductive thin film layer 20a is subjected to anisotropic etching treatment such as RIE so that the conductive sidewall 20 remains in the contact hole 18 and the thin film layer 2 is formed.
Remove 0a. The conductive sidewall 20 connects the intermediate conductive layers 16a and 16b to each other.

Next, as shown in FIG. 3 (E), the insulating thin film layer 22a is inserted into the contact hole 18.
Is formed on the interlayer insulating layer 14c. The insulating thin film layer 22a is made of the same material as the interlayer insulating layers 14a, 14b, 14c, and is made of, for example, silicon oxide, silicon nitride or the like. If a general atmospheric pressure CVD method or a general low pressure CVD method is used when forming the insulating thin film 22a,
Surface side film 22b and bottom side film 22 of contact hole 18
b and a film thickness can be made different, and the bottom side film 22c can be ½ or less of the front side film 22b. This film thickness difference can be used in the next step.

In the next step, the insulating thin film layer 22a is entirely etched back as shown in FIG. At that time, by selecting the parameters of the conditions described below,
The bottom side film 22c of the insulating thin film layer 22a and the interlayer insulating layer 14a that have entered the contact hole 18 are etched and removed in a self-aligning manner to expose the surface of the semiconductor substrate 2 and the conductive sidewall 20. The insulating sidewall 22 can be left on the inner peripheral side. this is,
This is because the bottom side film 22c is thinner than the front side film 22b.

Parameters for conditions for removing the bottom side film 22c in the contact hole 18 while leaving the insulating side wall 22 are (i) the thickness of the interlayer insulating layer 14a, and (ii) FIG. 2 (B). Contact hole 1 in the process shown
8 for forming 8 and (iii) FIG.
The amount of overetching when forming the conductive sidewall 20 in the step shown in (D), (iv) the film thickness difference between the bottom side film 22c and the front side film 22b, and the like. It is also possible to remove only the bottom of the contact hole 18 by etching by covering the portion other than the contact hole with a resist film.

Next, as shown in FIG. 3G, the upper conductive layer 16c is laminated so as to enter the contact hole 18, and the conductive plug 24 is formed in the contact hole. The upper conductive layer 16c is made of, for example, a polysilicon film formed by a CVD method, and the conductive plugs 24 may be made of the same material at the same time. In addition, the contact hole 18
The conductive plug layer 24 embedded inside is the upper conductive layer 1
Separately from 6c, it can also be formed by an etching back method of polysilicon or tungsten, or a selective growth method of tungsten.

The present invention is not limited to the above-mentioned embodiments, but can be variously modified within the scope of the present invention.
For example, according to the present invention, it is possible to obtain a semiconductor device having a multilayer wiring structure as shown in FIG. In this embodiment, the intermediate conductive layers 30a, 30b, 3 are formed on the semiconductor substrate 2.
0c are laminated via interlayer insulating layers 32a, 32b, 32c, 32d, and these conductive layers are connected by conductive sidewalls 34. An insulating sidewall 36 is formed on the inner peripheral side of the conductive sidewall 34, and a conductive plug 38 is formed on the inner peripheral side. The conductive plug 38 connects the uppermost conductive layer 30d to the surface of the semiconductor substrate 2. The semiconductor device having the multilayer wiring structure according to this embodiment can be easily manufactured by combining the processes shown in FIGS.

In the embodiment shown in FIG. 5, the intermediate conductive layers 40a, 40b, 40c and 40d are laminated on the semiconductor substrate 2 via the interlayer insulating layers 42a, 42b, 42c, 42d and 42e. Among the conductive layers, the conductive layer 40b,
40c is connected by a conductive sidewall 44a, and conductive layers 40a and 40b are connected by a conductive sidewall 44b. The conductive sidewalls 44a and 44b are mutually
It is insulated by the insulating sidewall 46a. An insulating sidewall 46b is formed on the inner peripheral side of the conductive sidewall 44b, and a conductive plug 48 is formed on the inner peripheral side. With this conductive plug 48,
The uppermost conductive layer 40d is connected to the surface of the semiconductor substrate 2. The semiconductor device having the multilayer wiring structure according to this embodiment can also be easily manufactured by combining the processes shown in FIGS.

In the embodiment shown in FIG. 6, the intermediate conductive layers 50a, 50b, 50c, 50d and 50 are formed on the semiconductor substrate 2.
e is an interlayer insulating layer 52a, 52b, 52c, 52d, 5
2e and 52f are laminated, and the conductive layers 50a, 50b, and 5 among these conductive layers except the conductive layer 50c are stacked.
0d is connected by a conductive sidewall 54. An insulating sidewall 56 is formed on the inner peripheral side of the conductive sidewall 54, and the conductive plug 5 is formed on the inner peripheral side.
8 is formed. The conductive plug 58 allows the uppermost conductive layer 50f, the intermediate conductive layer 50e, and the semiconductor substrate 2 to be formed.
Is connected to the surface of. The semiconductor device having the multilayer wiring structure according to this embodiment can also be easily manufactured by combining the processes shown in FIGS.

[0023]

As described above, according to the present invention, a conductive sidewall for connecting two or more conductive layers in the same contact hole, and this conductive sidewall with respect to a conductive plug. Insulating sidewalls for insulation are formed, so by using these conductive sidewalls and insulating sidewalls in combination, any conductive layers can be connected to each other in the same contact hole. It will be possible. As a result, the number of contact holes can be reduced as a whole, the degree of freedom in layout design of the integrated circuit is increased, and high integration can be achieved.

For example, when applied to a unit cell of SRAM, the number of contact holes can be reduced and the cell area can be reduced. In addition, there is an effect that the number of steps for forming a resist pattern by the photolithography technique can be reduced.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of essential parts of a semiconductor device having a multilayer wiring structure according to an embodiment of the present invention.

FIG. 2 is a main-portion cross-sectional view showing the method for manufacturing the semiconductor device of the embodiment.

FIG. 3 is a main-portion cross-sectional view showing the method for manufacturing the semiconductor device of the embodiment.

FIG. 4 is a cross-sectional view of essential parts of a semiconductor device having a multilayer wiring structure according to another embodiment of the present invention.

FIG. 5 is a cross-sectional view of essential parts of a semiconductor device having a multilayer wiring structure according to another embodiment of the present invention.

FIG. 6 is a cross-sectional view of essential parts of a semiconductor device having a multilayer wiring structure according to another embodiment of the present invention.

FIG. 7 is a cross-sectional view of essential parts of a semiconductor device according to a conventional example.

FIG. 8 is a cross-sectional view of essential parts of a semiconductor device according to another conventional example.

[Description of Reference Signs] 2 ... Semiconductor substrate 10 ... Semiconductor devices 14a, 14b, 14c ... Interlayer insulating layers 16a, 16b ... Intermediate conductive layer 16c ... Upper conductive layer 18 ... Contact hole 20 ... Conductive sidewall 22 ... Insulating side Wall 24 ... Conductive plug 30a, 30b, 30c ... Intermediate conductive layer 30d ... Upper conductive layer 32a, 32b, 32c, 32d ... Interlayer insulating layer 34 ... Conductive side wall 36 ... Insulating side wall 38 ... Conductive plug

Claims (4)

[Claims] 1. A semiconductor device having a multi-layer wiring structure in which at least two or more conductive layers are laminated on a semiconductor substrate via an interlayer insulating layer, and the same contact formed on the conductive layer and the interlayer insulating layer. A semiconductor device having a multilayer wiring structure in which a conductive sidewall connecting two or more conductive layers and an insulating sidewall insulating the conductive sidewall from a conductive plug are formed in the hole. 2. A step of alternately laminating two or more interlayer insulating layers and conductive layers on a semiconductor substrate, and a predetermined depth at which the interlayer insulating layers and the conductive layers do not reach the surface of the semiconductor substrate. By forming a contact hole, a step of forming a conductive thin film layer so as to enter the contact hole, and by anisotropically etching the conductive thin film layer,
A step of forming a conductive sidewall connecting two or more conductive layers in the contact hole, and a step of forming an insulating thin film layer so as to enter the contact hole in which the conductive sidewall is formed. , A step of etching the bottom of the insulating thin film layer that has entered inside the contact hole in a self-aligned manner with respect to the contact hole to form an insulating sidewall on the inner peripheral side of the conductive sidewall, and And a step of forming a conductive plug in a contact hole that is conformally etched. 3. A step of alternately laminating two or more interlayer insulating layers and conductive layers on a semiconductor substrate, and a predetermined depth at which the interlayer insulating layers and conductive layers do not reach the surface of the semiconductor substrate. By forming a contact hole, a step of forming a conductive thin film layer so as to enter the contact hole, and by anisotropically etching the conductive thin film layer,
A step of forming a conductive sidewall connecting two or more conductive layers in the contact hole, and a step of forming an insulating thin film layer so as to enter the contact hole in which the conductive sidewall is formed. A step of etching a bottom portion of the insulating thin film layer that has entered the contact hole by covering a portion other than the contact hole with a resist film, and forming an insulating sidewall on the inner peripheral side of the conductive sidewall, And a step of forming a conductive plug in a contact hole whose bottom is etched. 4. The method of manufacturing a semiconductor device having a multilayer wiring structure according to claim 2, wherein the conductive plug is formed by selective growth of tungsten.