JPH06112314A - Analog integrated circuit - Google Patents

Abstract

PURPOSE:To reduce offset error and improve noise resistance by providing an analog circuit group which is laid out in an array and at least one set of power supply wirings which are connected from the same direction as the array direction for each of the analog circuit group. CONSTITUTION:A plurality of chopper type comparators CC1, CC2,..., CCn used for an A/D converter are placed in a line. Each two wirings of a power supply VDD and a ground VSS are connected from the same direction as n array direction to the comparators CC1, CC2,..., Cn, thus avoiding interference between the adjacent comparators which are easily affected by switching noise each other and efficiently suppressing the influence of noise between the adjacent comparators.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in an analog integrated circuit when offset error or noise due to parasitic impedance added to each wiring of power supply and ground has a great influence on the characteristics of the analog circuit. The present invention relates to an analog integrated circuit with an improved wiring pattern of power supply and ground of a comparator circuit group of a D converter.

[0002]

2. Description of the Related Art Conventionally, as a typical example of an analog integrated circuit, one in which a large number of chopper type comparators for an A / D converter as shown in FIG. 1 are integrated is known.

That is, this chopper type comparator has an analog input SW1 and an analog input SW1 which are input to the terminal A _IN and a reference voltage input to the terminal V _ref , respectively.
By commonly applying to the input of the inverter I1 via SW2, the output of the inverter I1 is changed to the output terminal OUT.
The output signal is derived from the output terminal.

Here, the analog switch S3 connected to the input / output terminal of the inverter I1 is the analog switch S.
The switching operation is performed in a predetermined state together with 1 and S2.

[0005]

By the way, in an analog integrated circuit in which a large number of such chopper type comparators are integrated, the problem is that undesired resistance, inductance and capacitance parasitically formed in the inverter I1 section. It is an adverse effect of the ingredients.

2A and 2B are P channel MOSs.
Parasitic resistances Rs1 and Rs2 added between the power supply line and the ground line of the inverter I1 including the transistor 1 and the N-channel MOS transistor 2, and the parasitic inductance L.
s1, Ls2 and parasitic capacitance Cs1 are shown.

That is, such a parasitic component causes a ringing noise or a simultaneous switching noise which causes a malfunction due to an undesired noise disturbance in the analog integrated circuit. Of these, ringing noise is noise generated by a parasitic inductance component and a capacitance component of wiring.

Further, the simultaneous switching noise is a parasitic component of the power supply line and the ground line with respect to the time-varying component of the charging / discharging current when a plurality of outputs are switched when a device having a plurality of outputs is present inside the integrated circuit. It is noise that appears in the output that is not switched due to the inductance component and the capacitance component that are generated.

In particular, since these ringing noise and simultaneous switching noise are generated by the inductance component and the capacitance component of the bonding wire and the lead frame in the analog integrated circuit (IC), it is necessary to take measures inside the IC. For this reason, conventionally, measures have been taken to minimize the length of the bonding wires and the lead frame inside the IC to reduce the parasitic inductance and capacitance components.

However, such measures are practically
Since it requires extremely difficult work and has limits on the parasitic inductance and capacitance components that can be suppressed, it is not such an effective measure.

On the other hand, as shown in FIG. 3, the analog integrated circuit in which a large number of chopper type comparators as described above are integrated has a large number of chopper type comparators CC1 to CCn.
Are arranged in an array in a predetermined direction.

The form of the power supply wiring for the arrayed chopper type comparators CC1 to CCn is as follows.
As shown in FIG. 3, the power supply V _DD and the ground V _SS are connected from different directions.

Therefore, the parasitic impedance component added between each wiring of the power supply and the ground in such an array chopper type comparator is the resistance component (Rs1,
Rs2 ... Rsn, Rs1 ', Rs2' ... Rsn ') are representatively shown, and comparators CC1, CC2 ... CC of each stage are shown.
It is unavoidable that n is not uniform.

The non-uniformity of the parasitic impedance in each stage causes the non-uniformity of the offset error between the comparators, especially the resistance component thereof, and the abruptness of the inductance and capacitance components generated at the time of comparison of the comparators. It has a serious problem that noise is generated due to a change in current.

Such a problem, together with the problem due to the ringing noise and the simultaneous switching noise described above, has been a major obstacle in realizing a high-speed and highly accurate A / D conversion circuit.

Further, in the conventional array-type chopper type comparator, since the wirings of the power supply and the ground are connected from different directions with respect to the array direction, it is necessary to make the wiring lengths as short as possible. Not only that, but in a dual-in-package type IC in which a digital circuit and an analog circuit are mixedly mounted, it is difficult to separately arrange pins (especially output pins) of the digital circuit and the analog circuit on both sides. there were.

Therefore, the present invention has been made in view of the above points, and a parasitic impedance component added to each wiring of the analog circuit group, particularly, each power supply and ground for each comparator circuit in the A / D converter. The object of the present invention is to provide an analog integrated circuit having uniform characteristics (resistance, capacitance inductance) to reduce offset error, improve noise resistance, and have high-speed and high-precision characteristics. There is.

[0018]

An analog integrated circuit according to the present invention comprises an analog circuit group arranged in an array and at least one set or more connected to each of the analog circuit groups in the same direction as the array direction. It is characterized by including a power supply wiring.

[0019]

According to the above-mentioned structure, since the parasitic impedance components added to each wiring of the power supply and the ground for each analog circuit are evenly arranged, the offset error can be reduced and the noise resistance can be improved. .

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 5 shows, as an analog circuit group, a plurality of chopper type comparators CC1, CC2 ... CCn used in an A / D converter as described above are arranged in a line in an array, and each of these comparators CC1, CC2 is arranged. … C
Is an example of the wires are connected two by two each from the array direction in the same direction as the power source V _DD and the ground V _SS relative cn.

FIG. 6 is similar to FIG. 5 in that a plurality of chopper type comparators CC11, CC12 ... C used in the A / D converter.
In this example, C1n and CC21, CC22 ... CC2n are arranged in two rows in an array.

That is, in this example, the comparators CC11, CC12 ... CC1n on the right side of the drawing are used for an A / D converter of a video device which requires high speed, low power consumption and miniaturization.
Is used as the lower side, and the comparators CC21, CC22 ... CC2n on the left side of the drawing are used as the upper side.

The power supply wiring of this example is similar to that of FIG. 5, and the lower and upper comparators CC11, CC12, ...
Two wires for the power supply V _DD and two wires for the ground V _SS are connected to C1n and CC21, CC22 ... CC2n from the same direction as the array direction.

By wiring as shown in FIGS. 5 and 6, the resistance and inductance components of the power supply and the ground are evenly arranged between the comparators, so that the above-mentioned offset error is reduced and the noise resistance is improved. It is possible to achieve the purpose. A metal having a low resistance is used as the wiring material.

In this case, even if a pattern-like portion where the power supply and the ground wiring intersect with each other occurs, the recent multilayer metal technology (2
Due to the layers, the three layers ...), the treatment of the intersection does not pose any particular problem. An actual example is shown in FIG. That is, in FIG. 7, 6 is each comparator 6-1, 6-2, ..., 6-n.
Is a comparator array in which one line is wired in an array.

For this comparator array 6, as in FIG. 5, wirings for the power supply V _DD and the ground V _SS from the same direction as the array direction for the respective comparators 6-1, 6-2, ..., 6-n. Are connected by metal 1, 2 and 3, respectively.

Since the metal 3 portion shown by hatching in the drawing among the wirings of the metals 1, 2 and 3 is provided in a layer different from the other metals 1 and 2, there is no particular problem even if the crossing portion 5 occurs. Absent. In FIG. 7, reference numeral 4 is a contact hole for interlayer connection with the metals 2 and 3. Figure 8
Shows another more specific example.

In this example, inverter chopper type comparators CC31, CC32, ... C arranged in a line in an array.
For C3n, two wirings for the power supply V _DD and the ground V _SS are provided in the same direction as the array direction, respectively V _DD1 , V _DD2 and V _SS1 , V _SS2 , and at least different power supplies and grounds for adjacent comparators. It is connected from the wiring.

That is, first, as shown in the figure, the power supply V _DD and the ground V _SS connected to the inverter I1 section of the first comparator CC31 are connected via the first power supply line V _DD1 and the first ground line V _SS1 . Next, when connecting to the second comparator CC32, the second power supply line V _DD2 and the second ground line V _SS2
Connect through. Hereinafter, similarly, the power supply wiring is connected to each comparator via a power supply line and a ground line which are different for each adjacent comparator.

By doing so, it is possible to avoid the interference between the adjacent comparators, which are easily affected by the switching noise, and to effectively suppress the influence of the noise between the adjacent comparators. Will be able to. FIG. 9 is an enlarged view of the inverter chopper type comparator used in FIG.

That is, the switch SW11 for switching the analog input (Ain), the switch SW12 for switching the reference voltage V _ref , and the switch SW13 for switching between the input and output ends of the inverter I1 are a pair of P and N channel MOS transistors, respectively. And a control signal φ applied to each of these gates.
Switching is performed in a predetermined state by an inverted signal of _A and φ _A or an inverted signal of φ _r and φ _r .

The inverter I11 is composed of P and N channel MOS transistors, the signals from the switches SW11 and SW12 are input to the common gate portion through the capacitor C, and the buffer circuit inverter is connected from the drain-source connection portion. An output signal is output to the output terminal OUT via I12. Here, the power source V is supplied to the upper drain and the lower source of the inverter I11 as described above.
Each wiring between _DD and the ground V _SS is connected in a predetermined form. The inverter chopper type comparator of FIG. 9 may be used not only in FIG. 8 but also in FIGS. 5, 6 and 7.

As shown in each of the above embodiments, a plurality of comparators used in analog circuit groups, particularly A / D converters, are arranged in an array, and at least one set of power supply wiring for each comparator is arranged in the array direction. Since they are connected in the same direction, the parasitic impedance components added to each wiring can be made uniform.

As a result, it is guaranteed that the analog integrated circuit according to the present invention has characteristics of high speed and high accuracy by reducing the offset error between the analog circuits and improving the noise resistance.

Further, according to the present invention, since the power supply wiring structure is capable of reducing the offset error and improving the noise resistance as described above, it is extremely difficult and limited as in the conventional case. Not only does it become unnecessary to shorten the wiring length as much as possible, but in a dual-in-package type IC in which a digital circuit and an analog circuit are mixedly mounted, the pins of the digital circuit and the analog circuit (particularly the output pin) are separated on both sides. It becomes easy to arrange. That is, according to the present invention, a structure resistant to noise can be obtained from both sides of the package and the chip.

[0037]

As described above, according to the present invention, it is possible to provide an analog integrated circuit having high-speed and high-accuracy characteristics by reducing the offset error and improving the noise resistance. It will be possible.

[Brief description of drawings]

FIG. 1 is a diagram showing a conventional chopper type comparator circuit.

FIG. 2 is a diagram showing a resistance, an inductance, and a capacitance parasitically added to each wiring of the power supply and the ground of the inverter unit of FIG.

FIG. 3 is a diagram showing a wiring example of power supply and ground when a large number of conventional chopper type comparators are arranged.

FIG. 4 is a diagram showing an example of an equivalent circuit when only parasitic resistance is considered in FIG.

FIG. 5 is a diagram showing an embodiment of the present invention.

FIG. 6 is a diagram showing another embodiment of the present invention.

FIG. 7 is a diagram showing yet another embodiment of the present invention.

FIG. 8 is a diagram showing an embodiment in which the present invention is more embodied.

9 is an enlarged view showing an inverter chopper type comparator used in FIG.

[Explanation of symbols]

V _DD ... Power supply, V _SS ... GND (ground), CC1 to CCn ... Chopper type comparator.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshinasa Kawai 25-1 Ekimaehonmachi, Kawasaki-ku, Kawasaki-shi, Kanagawa 1 Toshiba Microelectronics Corporation

Claims (4)

[Claims] 1. An analog circuit, comprising: analog circuit groups arranged in an array; and at least one set of power supply wirings connected to each of the analog circuit groups in the same direction as the array direction. Integrated circuit. 2. The analog integrated circuit according to claim 1, wherein the analog circuit group is a comparator circuit group used in an A / D converter. 3. At least one of the power supply wirings has at least two power supply wiring patterns, and the analog circuit groups are connected from different power supply wiring patterns for at least adjacent analog circuits. The analog integrated circuit according to claim 1. 4. The analog integrated circuit according to claim 3, wherein the analog circuit group is a comparator circuit group used in an A / D converter.