JPH06112224A - Field effect transistor - Google Patents

Abstract

PURPOSE:To alleviate concentration of electric current into a drain electrode terminal for improved drain withstand voltage by forming an insulation area at a part of active layer between a gate electrode and a drain electrode. CONSTITUTION:On a semi-insulation GaAs substrate 1, a non-dope GaAs buffer layer 2 and an N-type GaAs active layer 3, carrier concentration 2X10<17>cm<-2>, are sequentially grown by MBE, MOCVD, etc. Then a recess is formed in an expected gate electrode area by wet etching. Then after a metal is vapor- deposited, a gate electrode 6 is farmed by selective-etching. Then a source electrode 5 and a drain electrode 8, establishing an ohming contact l=2 go away from the recess, are formed.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to field effect transistors, and more particularly to GaAs MESFETs.

[0002]

2. Description of the Related Art A conventional GaAs MESFET will be described with reference to FIG. Via a high resistance non-doped AlGaAs buffer layer 2 on a semi-insulating GaAs substrate 1,
N-type GaAs active layer (active layer) 3 in which a channel is generated
Are formed. A source electrode 5 and a drain electrode 4 are formed on both sides of the surface of the N-type GaAs active layer 3.
A recess is formed in the surface of the N-type GaAs active layer 3. A gate electrode 6 is formed on the surface of the recess.

The source electrode 5 of this GaAs MESFET
When is grounded and a positive potential is applied to the drain electrode 8, electrons flow from the source electrode 5 toward the drain electrode 4, causing a current to flow. The magnitude of the drain current can be controlled by the potential applied to the gate electrode 6.

[0004]

[Problems to be Solved by the Invention] Conventional GaAs MES
In the FET, current concentrates on the drain electrode end 8 as shown by the arrow (→) in FIG. There is a problem in that even if the gate-drain voltage is relatively low, thermal breakdown occurs due to current concentration and a source-drain short circuit occurs.
An object of the present invention is to alleviate the concentration of drain current and improve the drain breakdown voltage.

[0005]

In the field effect transistor of the present invention, an insulating layer is formed from the end of the drain electrode on the surface of the semiconductor layer where the channel is formed toward the gate electrode.

[0006]

EXAMPLE FIG. 1A shows a first example of the present invention.
Will be described in order of steps.

First, MB on the semi-insulating GaAs substrate 1
A non-doped GaAs buffer layer 2 and an N-type active layer 3 having a carrier concentration of 2 × 10 ¹⁷ cm ⁻² are sequentially grown by E or MOCVD. Next, a recess is formed in the intended gate electrode region by wet etching. Next, metal is deposited and then selectively etched to form the gate electrode 6. Next, the source electrode 5 and the drain electrode 8 which are in ohmic contact with each other at a distance of 1 to 2 μm from the recess are formed.

At this time, the insulating layer 7 is formed by ion-implanting ¹¹ B ⁺ , ¹⁶ O ⁺ or ¹ H ⁺ into the drain electrode end 8 to a depth similar to that of the recess.

As shown by the arrow (→) in FIG. 1A, this insulating layer 7 alleviates the concentration of current on the drain electrode end 8 and prevents the occurrence of thermal breakdown.

Next, a second embodiment of the present invention will be described with reference to FIG.

In this embodiment, by forming the insulating region 7 also on the end of the source electrode 5, the concentration of current at the end of the source electrode 7 can be alleviated.

[0012]

By forming the insulating region in a part of the active layer between the gate electrode and the drain electrode, the concentration of current at the end of the drain electrode can be relaxed and the drain breakdown voltage can be improved.

[Brief description of drawings]

FIG. 1A is a sectional view showing a first embodiment of the present invention. (B) is a sectional view showing a second embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a conventional field effect transistor.

[Explanation of symbols]

 1 semi-insulating GaAs substrate 2 non-doped AlGaAs buffer layer 3 N-type AlGaAs active layer 4 drain electrode 5 source electrode 6 gate electrode 7 insulating layer 8 drain electrode end

Claims (1)

[Claims] 1. A field effect transistor having an insulating layer formed on a surface of a semiconductor layer between a drain electrode and a gate electrode.