JPH0611072B2 - Semiconductor non-volatile memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor nonvolatile memory device in which a spare element for remedying a defect in a memory cell array caused by a process defect is redundantly configured.

[Conventional technology]

When manufacturing a mask programmable ROM (read only memory), a defect may occur in a memory cell array due to a process factor such as a pattern defect, which causes a decrease in yield. Therefore, the spare memory cell array is redundantly configured to relieve the defect. 2. Description of the Related Art As a semiconductor non-volatile memory device that is conventionally designed to relieve a defect by this type of redundant configuration, for example, an ECC (error Ccheck-ing and correc) that corrects a defective bit is used.
ting) circuit or FAMOS (floating)
It is known that a variable threshold nonvolatile memory having a gate ava-lanche injection MOS) structure is provided as a redundant memory cell, that is, a spare element.

FIG. 3 is a configuration diagram showing a conventional semiconductor nonvolatile memory device using the variable threshold nonvolatile memory. In the figure, 1 is a regular main mask programmable memory cell array arranged in a matrix of rows and columns, 2 is a memory cell array of a spare row made of FAMOS, 3 is a regular decoder, and 4 is an address signal. Is input to the address buffer, 5 is a defective address storage unit formed of FAMOS, 6 is a decoder for a spare row, 7 is a read circuit for reading data, and 8 is a memory cell array 2 for the spare row.
This is a writing circuit for writing data to.

As described above, FAMOS is used as the programmable ROM of the defective address storage unit 5 and the memory cell array 2 of the spare row.
In a memory device configured to use, the expected data that has been written by the memory tester and the data of the regular memory cell array 1 are first tested and compared, and if a defect is found, the defective address is stored in the tester. To do. Then, it is determined whether or not the memory cell of the defective address can be repaired by the memory cell array 2 of the spare row which is provided in advance. Here, if relieving is possible, that is, if the defective memory cell can be replaced by the memory cell of the memory cell array 2 in the spare row, the defective address is programmed in the defective address storage unit 5, and the memory cell array 2 in the spare row is further programmed. A designated circuit composed of FAMOS for designating a spare row is programmed so that the spare row can be selected. In this state, the spare row memory cells of the spare row memory cell array 2 are selectively programmed corresponding to the expected data of the memory cells of the regular memory cell array 1 to be replaced. When all the above operations are completed, the defective memory cell of the normal memory cell array 1 is switched to the memory cell of the memory cell array 2 in the spare row, and the defective memory can be relieved.

[Problems to be solved by the invention]

The conventional semiconductor non-volatile memory device is configured as described above, and has problems such as an increase in chip area.
That is, the spare memory cell array 2 using FAMOS
In order to write data to the FAMOS, a high voltage is required to write data to the FAMOS. Therefore, the normal memory cell array 1 needs the high voltage spare row write circuit 8 which is completely unnecessary. Since it may be applied to the cell array 1, the distance between the diffusion layers in the memory cell array 1 needs to be set wider than usual, which causes a problem that the chip area must be increased. or,
Even with the built-in ECC circuit, there is a problem in that the chip area increases correspondingly and the access time becomes slow.

The present invention has been made to solve such a problem, and provides a semiconductor non-volatile memory device that requires no extra circuit, has a short access time, has a small chip area, and has a high degree of integration. It is an object.

[Means for solving problems]

In the semiconductor nonvolatile memory device of the present invention, a regular memory cell array having a plurality of memory cells arranged in a matrix in a plurality of rows and a plurality of columns, and arranged in a plurality of rows in the regular memory cell array, A plurality of word lines connected to memory cells arranged in corresponding rows,
A plurality of bit lines arranged in a plurality of columns in the regular memory cell array and connected to memory cells arranged in corresponding columns, and a plurality of columns corresponding to a plurality of columns in the regular memory cell array Are connected between a transistor element having one main electrode connected to a bit line arranged in a corresponding column and the other main electrode of the transistor element and a line to which a predetermined potential is applied. A spare memory cell array having a plurality of spare memory cells having a fuse element composed of a polycrystalline silicon link, and controlling the transistor elements of the spare memory cells arranged in corresponding rows of the spare memory cell array. A spare word line connected to the electrodes is provided.

[Action]

When a defect occurs in the original memory cell array, the defective memory cell is switched to the spare memory cell array. At this time, a spare memory cell is formed by fusing the polycrystalline silicon link with laser light, and the above defect can be relieved.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a semiconductor nonvolatile memory device according to the present invention, in which the same parts as those of the conventional one (see FIG. 3) are designated by the same reference numerals. In the figure, 1 is a regular memory cell array in which mask programmable memory cells are arranged in a matrix in a plurality of rows and a plurality of columns, 3 is a regular decoder, 4 is an address buffer to which an address signal is input,
Reference numeral 5 designates a defective address storage section for judging and storing a defective address when a defect occurs in the memory cell array 1.
6 is a decoder for a spare row, 7 is a read circuit for reading data from the memory cell array 1, 8 is a regular memory cell array 1
In a memory cell array of a spare row provided adjacent to the above, a poly (polycrystal) silicon fusible link that can be blown by laser light is configured as a spare memory cell.

FIG. 2 is a diagram showing a specific structure of the spare memory cell array 8, FIG. 2 (a) shows a cell structure, and FIG. 2 (b) shows an equivalent circuit thereof. In the figure, 9 is a diffusion layer, 10 is a contact hole, BL ₁ and BL ₂ are arranged in a plurality of columns in the regular memory cell array 1, and a plurality of bits connected to the memory cells arranged in corresponding columns respectively. It is a line (bit line) and is arranged by A1 (aluminum). W ₁ and W ₂ are regular word lines (word lines),
Arranged in a plurality of columns in the regular memory cell array 1,
Each is connected to the memory cells arranged in the corresponding row. SW ₁ is a spare word line, F ₁ and F ₂ are spare blown polysilicon links that can be blown by laser light, and Q _{1 to} Q ₄ are regular memory cells, which are formed as transistors in this case. SQ ₁ and SQ ₂ are spare memory cells and are similarly formed as transistors.

The spare memory cell array 8 is arranged in a plurality of columns corresponding to the plurality of columns of the regular memory cell array 1, and each has a main electrode connected to one of the bit lines arranged in the corresponding column. And a plurality of spare memory cells each having a fuse element formed of a polycrystalline silicon link connected between the other main electrode of the transistor element and a line to which a predetermined potential is applied. The spare word line SW ₁ is connected to the control electrodes of the transistor elements of the plurality of spare memory cells arranged in the corresponding row of the spare memory cell array 8.

Next, the operation will be described. The original memory cell array 1 is composed of a mask programmable ROM of 1 W bit or more, and even if the semiconductor process technology is improved, even if the minimum processing dimension of 2 μm or less and one million elements or more are integrated on one chip, all Memory cells are not always good. That is, some defects include defective memory cells of 1 bit or more due to defects in the silicon wafer, manufacturing defects due to foreign substances such as dust during processing, and the like. Therefore, the wafer, which has undergone a series of steps in accordance with a normal semiconductor integrated circuit manufacturing process, is first checked for electrical characteristics in the same state. If the defective memory cell is included, the defective address is taken in by the memory tester and it is determined whether or not the spare memory cell array 8 provided in advance can replace the defective address. If the defective address can be replaced, the defective address is written in a programmable element such as a polysilicon link of the defective address storage unit 5.
Further, in order to activate the spare row decoder 6, the spare row used in the spare row designating ROM circuit is programmed, and further, the spare row is programmed based on the data originally programmed in the row including the defective memory cell. The polysilicon links F ₁ and F ₂ forming the memory cell array 8 are programmed with laser light. At this time, if the polysilicon links F ₁ and F ₂ are blown by the laser light, for example, “0” is stored in the spare memory cell, and if not blown, “1” is stored in the spare memory cell. Through the above process, the original memory cell array 1
Defective memory cells occurring in the polysilicon link F _1,
The spare memory cell array 8 made of F ₂ is switched to be relieved and becomes a non-defective chip, which greatly contributes to improvement in yield.

In the above embodiment, the polysilicon links F ₁ and F ₂ are blown by the laser light to rewrite the data of the defective memory cell to the memory cell array 8 of the spare row. The same effect can be obtained even when it is used as a program element by changing the resistance value of the polysilicon link.

〔The invention's effect〕

As described above, according to the present invention, since the spare memory cell array having the polycrystalline silicon link that can be blown by the laser beam as the spare memory cell is provided adjacent to the regular memory cell array, the special write circuit is provided. Is unnecessary, the yield can be improved without increasing the chip area, and the access time is not delayed.

[Brief description of drawings]

1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a concrete block diagram of the memory cell array of FIG. 1, and FIG. 2 (a)
Is a diagram showing a cell structure, FIG. 2 (b) is a diagram showing an equivalent circuit thereof, and FIG. 3 is a configuration diagram showing a conventional example. 1 ...... regular memory cell array 2, 8 ...... spare row of memory cell array F _1, F ₂ ...... poly (polycrystalline) silicon links Q _1, Q ₄ ...... memory cells SQ ₁ regular, SQ ₂ ...... pre The same reference numerals in the drawings indicate the same or corresponding portions.

Claims (2)

[Claims] 1. A regular memory cell array having a plurality of memory cells arranged in a matrix in a plurality of rows and a plurality of columns, and arranged in a plurality of rows in the regular memory cell array, each arranged in a corresponding row. A plurality of word lines connected to the memory cells arranged in a plurality of columns in the regular memory cell array, and a plurality of bit lines connected to the memory cells arranged in a corresponding column, A transistor element having a plurality of columns corresponding to the plurality of columns of the memory cell array, each of which has one main electrode connected to a bit line disposed in the corresponding column, and the other main electrode of the transistor element. A spare memory cell having a plurality of spare memory cells each having a fuse element formed of a polycrystalline silicon link connected to a line to which a predetermined potential is applied. Array, semiconductor nonvolatile memory device having a spare word line connected to the control electrode of the transistor of the plurality of spare memory cells arranged in rows corresponding in this spare memory cell array. 2. The semiconductor nonvolatile according to claim 1, wherein the fuse element in the spare memory cell array can be formed by changing the resistance value by annealing the laser light. Storage device.