JPH0610801B2 - Main memory access controller - Google Patents

Description

DETAILED DESCRIPTION [Table of Contents] Outline Industrial field of application Conventional techniques and problems to be solved by the invention Means for solving the problems Action Example Working effect of the invention [Outline] One or more Of the main memory unit (MSU), which is composed of a plurality of segments and has an access request bus corresponding to each segment. The above main memory of access requests in which the execution order for executing a program is defined per unit machine cycle from one or a plurality of processing units 2 logically connected to Main memory control unit (MCU) that controls whether to send to the device (MSU) 1
A computer system having: a main storage control unit (MCU) 1 and a main storage unit (MSU), each of which has one or more access request buses corresponding to a unit data length. Storage control unit (M
CU) 1 is the main memory control unit (M
CU) 1 for valid bit, access address,
One or a plurality of first request ports for setting an access request corresponding to the access element, which has an access request composed of an operation code or the like, with the unit data length or a data length shorter than that as one access element. And a main memory access control device in the above computer system in which the execution order of the access elements is specified for executing the program, and is specified for executing the program for the unit data when a random access request is made. After selecting an access element in the execution order that is set, the main memory device (M
For the purpose of improving the usage efficiency of the main memory (MSU) by transmitting in sequence from the unit data (element) that can access (SU), (1) In the output of the first request port 10 above ,
A second request port corresponding to the access request bus is selected by selecting an access request bus to the main memory unit (MSU) according to the designated position of the access address of an arbitrary access request.
When setting to 12, check the bus conflict &
In another check unit 11, the conflict check between the segments and the execution order of the access requests, which is stipulated in executing the program, are performed while being guaranteed.
In the output, only the contention between the segments in the local access bus is checked and the intra-segment bank busy check unit
The check is made in 13 to determine whether or not to issue the own access request.

(2) In the main memory access control device, the bus conflict check & other check unit provided in the main memory control unit (MCU) 1 for each segment of the main memory device (MSU) 11 The first priority cycle mechanism 11 that sets the access request in the second request port 12 in order based on the result of the bus conflict check of the access request and the pointer 11e that defines the order in executing the program. And a second priority cycle mechanism 13 for performing a bank busy check on unit data in each segment. In the first priority cycle mechanism 11, the request port 10 of the first request port 10
The bus conflict check between the buses provided corresponding to the & bus conflict check in the other check unit 11 and the access request from the first request port indicated by the pointer 11a are given the highest priority, and the above program is executed. The access request selected in accordance with the rule of execution order for execution is set in the second access port 12 corresponding to each segment in the main memory unit (MSU), and in the second priority cycle mechanism 13, A bank busy check is performed in the bus for each of the second request ports 12, and if it is not busy, an access request for each unit data is issued to each bank.

[Industrial application field]

The present invention has one or more main storage units (MSUs),
The main memory unit (MSU) is composed of a plurality of segments, has an access request bus corresponding to each segment, and is one or more logically connected to the main memory unit (MSU). The main storage device for access requests for which one or a plurality of access requests are defined per unit machine cycle from each processing device 2 in order to execute a program.
A computer system having a main memory control unit (MCU) 1 for controlling whether or not transmission to (MSU) is possible, and one or more units are provided between the main memory control unit (MCU) 1 and the main memory unit (MSU). Of the main memory control unit (MCU) 1 having the access request bus corresponding to each unit data length of
Is the main memory control unit (MCU) 1 from the above processing unit 2.
One or a plurality of access requests including valid bits, access addresses, operation codes, etc. for each of the above-mentioned unit data lengths or data lengths shorter than that as one access element. The present invention relates to a main memory access control device in the computer system, which has a plurality of first request ports 10 and the processing order of the access elements is specified for executing a program.

Generally, in the above computer system, the logic of the priority check mechanism that takes priority of the transmission of the access request to the main storage unit (MSU) is deep, and the logical delay due to the priority check mechanism causes the machine cycle of the computer system. Since it may be long and may seriously affect the processing capacity of the computer system, the logical delay of the priority check mechanism is required to be as short as possible.

On the other hand, even if the logical delay in the priority check mechanism is short, the main memory device (MS
In the mechanism that issues an access request to (U),
For example, the throughput of data transfer in the case of randomly accessing unit data (8 bytes) or less is significantly reduced.

Therefore, in the computer system that performs the random access, a priority check method that can transmit the data every machine cycle while guaranteeing the order specified for executing the program is required.

[Problems to be Solved by Prior Art and Invention] FIG. 4 is a diagram for explaining a conventional main memory access control method, and FIG. 4 (a) is a diagram schematically showing a priority check mechanism. (b) is a figure explaining a problem at the time of random access.

In a conventional main memory control unit (MCU) 1, a processing unit such as a central processing unit (CPU) or vector unit (VU) 2
The random access request sent from the main memory control unit (MCU) 1 to the main memory control unit (MCU) 1 is the total unit data (or the unit data length or less) set in the access port 10 ′ in the priority cycle shown in FIG. Access request (including the data of the above), check that there is no bus conflict and that there is no bank busy. Then, in that cycle, set the value of the pointer 11e that indicates the highest priority port (for example, the port number). Based on that, when the order of executing the program is guaranteed,
The access requests set for each port were sequentially sent to the main memory unit (MSU).

In this method, as described above, for all unit data (called elements) of each access request, all the race conditions are checked at the same time. For example, in the example shown in (a), "bus conflict check" and "bank busy check" are performed. ”,“ Other conflict check ”in each of the check units 11a to 11c, and then, based on the result of the check, in the priority control unit 11d, the pointer 11e that defines the order for executing the program is Since the highest priority access request is determined based on the indicated priority and the determined highest priority access request can be sequentially transmitted, the main memory is required unless all the race conditions are cleared. The access request cannot be sent to the device (MSU), and especially when the number of competing conditions is increasing due to the multiprocessor, etc. There has been a problem that the reduction in the increases.

For example, as shown in (b), when the access requests for the elements 0 to 3 are issued from the respective ports A to D 10 ', since the pointer 11e points to the port A, the above priority cycle ( In cycle 1), even if elements 0 to 3 can be transmitted by the bus conflict check, if element 0 of port A is bank busy (indicated by “x” in the figure) in the bus, other elements 1 In order to guarantee the order of program execution, all of the 4 elements are waiting, and in the next priority cycle (cycle 3), the bank busy for the element 0 of the port A is released and the call is transmitted. Even if the pointer 11e designates the element 1 of the port B as the highest priority,
In the element 1 of 1., when the bank is busy on the basis of the condition of the access request from the other processing device, the remaining 3 elements are waiting, and this element group is at least the bank busy cycle (for example, after the cycle 3). There is a problem in that it has to wait for 8 cycles in the case of fetch and 12 cycles in the case of store.

In view of the above-mentioned conventional drawbacks, the present invention has one to a plurality of main storage units (MSU), and the main storage unit (MSU) is composed of a plurality of segments. An access request bus is provided, and one or more programs are executed per unit machine cycle from one or more processing units 2 logically connected to the main memory unit (MSU). A computer system having a main memory control unit (MCU) 1 for controlling whether or not to issue access requests to the main memory unit (MSU) whose execution order is specified by the main memory control unit (MCU). One or a plurality of access request buses corresponding to unit data lengths are provided between the main memory unit (MSU) and the main memory control unit (MSU).
CU) 1 is the main memory control unit (M
CU) 1 for valid bit, access address,
One or a plurality of first request ports for setting an access request corresponding to the access element, which has an access request composed of an operation code or the like, with the unit data length or a data length shorter than that as one access element. And the order of execution in executing the program is guaranteed in the above computer system in which the processing order of the access elements is specified in executing the program,
An object of the present invention is to provide a main memory access control device that improves the efficiency of use of the main memory unit (MSU) by transmitting in sequence from the elements that can access the main memory unit (MSU) in each access request bus. It is what

[Means for solving problems]

The above problems are solved by the main memory access control system having the following configuration.

(1) It has one to a plurality of main storage units (MSU), and the main storage unit (MSU) is composed of a plurality of segments, and has an access request bus corresponding to each segment. , Per unit machine cycle from one or more processing units 2 logically connected to the main memory (MSU),
One or a plurality of the main storage devices (MSs) of access requests for which the execution order for executing the programs is defined.
U) Main memory control unit that controls whether to make a call
A computer system having (MCU) 1, wherein one or more access request buses corresponding to unit data lengths are provided between the main memory control unit (MCU) 1 and the main memory unit (MSU). The main memory control unit (M
CU) 1 is the main memory control unit (M
CU) 1 for valid bit, access address,
One or a plurality of first request ports for setting an access request corresponding to the access element, which has an access request composed of an operation code or the like, with the unit data length or a data length shorter than that as one access element. In the computer system in which the processing order of the access elements is specified for executing the program, the output of the first request port 10 is based on the designated position of the access address of the arbitrary access request. A second request port corresponding to the access request bus for selecting the access request bus to the main memory unit (MSU)
When setting to 12, check the bus conflict &
In another check unit 11, the conflict check between the segments and the execution order of the access requests, which is stipulated in executing the program, are performed while being guaranteed.
In the output, only the contention between the segments in the local access bus is checked and the intra-segment bank busy check unit
The check is made in 13 to determine whether or not to issue the own access request.

(2) In the main memory access control device, the bus conflict check & other check unit provided in the main memory control unit (MCU) 1 for each segment of the main memory device (MSU) 11 The first priority cycle mechanism 11 that sets the access request in the second request port 12 in order based on the result of the bus conflict check of the access request and the pointer 11e that defines the order in executing the program. And a second priority cycle mechanism 13 for performing a bank busy check on the unit data in each segment. In the first priority cycle mechanism 11, the second priority cycle mechanism 13 is provided corresponding to the first name request port 10. Bus conflict check between other buses & other check units
Bus conflict check at 11 and the above pointer 1
The access request from the first request port indicated by 1a is given the highest priority, and the access request selected according to the rules of the execution order for executing the above-mentioned program is associated with each segment in the main memory unit (MSU). , The second access port 12 is set, and in the second priority cycle mechanism 13, a bank busy check is performed in the bus for each of the second request ports 12 and if not busy, each bank is checked. On the other hand, the access request is transmitted for each unit data.

[Action]

That is, according to the present invention, the output of the first access port of the main memory control unit (MCU), that is, the access request consisting of one to a plurality of unit data, is transmitted in the first priority cycle, for example, to each A pointer that indicates the execution order on the program is checked for access requests that are checked for bus conflicts corresponding to each segment that makes up the main memory unit (MSU) and that there is no bus conflict. The data of the indicated port is given the highest priority, the order of execution in executing the program is guaranteed, and the data is set to the second access port corresponding to each segment.

In the first priority cycle, the access request set in the second access port has no conflict between the buses regardless of unit data or block data. In (1), for example, only a contention condition check in the segment, such as a bank busy check in each segment, is performed, and it is determined whether or not the access request is sent to the main storage unit (MSU) depending on whether the check is possible or not.

By controlling in this way, the main memory control unit (M
CU), for example, in the second access port provided corresponding to each segment, there is no need to wait due to a race condition with elements other than the element set in each port of the second request port. , If the bank is not busy, the call can be sent immediately and the main memory (M
This has the effect of increasing the access efficiency for SU).

〔Example〕

 Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram schematically showing an embodiment of the present invention,
FIG. 2 is a diagram for explaining the operation of random access according to the present invention, FIG. 3 is a diagram for explaining the operation of the request pointer control circuit of the present invention, and (a1) shows the first access port. , (A2) shows a logical expression for setting unit data in the second access port, (b) shows a concrete configuration example of the logical expression shown in (a2), and (c) shows a pointer. FIG. 1 shows a transition example. In FIG. 1, access requests from each device are checked for conflicts between buses, guarantee of order in executing programs, and bank busy check in the bus are performed in two priority cycles. The means for checking with is the means necessary for carrying out the present invention. The same reference numerals indicate the same objects throughout the drawings.

The main memory access control device of the present invention will be described below with reference to FIGS.

Main storage (MSU) is typically multiple segments (SEG)
And a bus is set up corresponding to the segment (SEG), for example.

Therefore, in the present invention, the first to
For example, for an access request from the vector unit (VU) 2 received by the request port 10 (hereinafter, may be referred to as an access port for convenience of description) 10, first, a race condition check between buses and a program are executed. The above order guarantee is performed by the bus conflict check & other check unit 11 and the pointer 11e, and the access request for which the priority is acquired is set in the second access port 12 corresponding to each bus.

Since the access request set in the second access port 12 has acquired the right to use the bus corresponding to the access port 12 as described above, the bank busy check unit 13 in the SEG makes the access request in the bus Priority in
That is, if the priority can be obtained in the bank busy check, it can be immediately sent to the main storage unit (MSU).

In this figure, this state is referred to as "MS G 0 MSU
0, SEG 0 ”and so on. That is, main memory (MUS 0)
It indicates that an access request can be issued to a specific bank in segment (SEG) 0 of.

By controlling in this way, it becomes possible to independently issue an access request for each bank, for example, for each unit data length of 8 bytes, corresponding to each segment of each main memory unit (MSU).

The transmission operation at this time will be described with reference to FIG. 2. In the first priority cycle, for example, the access request sent from the vector unit (VU) 2 is set in the first access port (A to D) 10. For each element data of the first access port (A to D) 10, the bus conflict check & other check unit 1
Performs a bus conflict check at 1 and points to the element data for which a race condition between buses has been confirmed.
Based on the access port number designated by 1e, it is assumed that the second access port 12 is set with element data 0 to 3 in which the order of execution of the programs is guaranteed. (This is indicated by'S ') In the second priority cycle (cycle 1) shown in FIG. 1, a unit data (element) in which data from a certain processing device, that is, the vector unit (VU) 2 is continuous. 0,1,2,3, ..., even if the element 0 is bank busy, other elements 1
If ~ 3 is not bank busy, the bank busy cancellation is indicated by "○" and the bank busy state is indicated by "x"}, and in the second priority cycle (cycle 1), competition between banks is generated. Since there is no condition, the access request for which the bank busy is released is immediately sent to the main storage unit (MSU).

Then, in the next same second priority cycle (cycle 2), unless the bank busy of the element 0 which was busy in the previous cycle is released,
The state of the same continues. That is, since the order of the program is not guaranteed, the following elements (4 to 7) are not set in the second access port 12.

In the next cycle 3, when the bank busy for the element 0 is released, the element 0 is immediately transmitted to the main memory unit (MSU), but in the same cycle,
In the first priority cycle, the pointer 1 for guaranteeing the order in executing the program for the following elements 4 to 1 until the element is transmitted 1
Since 1e is the one pointing to the access port A 10,
Second access port 1 to the following element 4
The setting to 2 is not done yet.

Then, in the next cycle 4, when the pointer 11e points to the access port B10, the order of executing the program is guaranteed for the subsequent elements 4 to 7, and the pointer 11e is accessed. Moving to the port BCDA, the elements 4 to 7 are set to the corresponding ports of the second access port 12 (indicated by'S ') as shown, and only the bank busy check in each port is performed. Be seen.

Next, referring to FIG. 3, a concrete example of the guarantee operation of the order (that is, the order of execution) in executing the program by the pointer 11e will be described.

In the figure, four first access ports (A, B, C,
D) Assuming 10 and vector unit (VU) at the port 10.
When the access request from 2 is set, the second
7 shows an example of the VU pointer 11e that indicates the highest priority port to be set in the access port 12 (provided for the bus as described above).

It is assumed that (a1) in the figure shows the first access port 10 and that the VU pointer 11e points to the access port A as shown.

At this time, the logic for guaranteeing the order in executing the program for the access port A 10, that is, the condition for setting the second access port 12 is defined as “AP in FIG.
ORT SET ENABLE ”.

In the figure (a2), “POINT A · A EN” can set the element data of the port A 10 to the second access port 12 when the VU pointer 11e points to the first access port A 10. The conditions are shown.

Here, “A EN” means that the bus corresponding to the destination address of the element data set in the first access port A 10 is “vacant” or the bus is in use (called “valid”). ), The access request that used the bus is released (released) in this cycle. The same applies to "B EN", ....

Also, “BC MTCH”, “CD MTCH”, ... In the figure are bus conflicts from the first access port B, C or the ports C, D to the second access port 12, which is the destination of the data. (Bus match) indicates that, for example, the element of the access port B 10 cannot be transmitted to the second access port 12. The same applies hereinafter.

Therefore, for example, when the VU pointer 11e points to the first access port B 10, each port B, C,
The above-mentioned "B EN", "C EN", ... which indicate the destination conditions of each element data of D and A 10 are all "OK".
And the second access port at the destination 12
If there is no bus match for {this condition , ...}, the element data of the port A 10 can be set in the second access port 12.

The same applies to the conditions when the pointer 11e points to the ports C and D, and the same applies to the element of the port A 10 when the logical condition of the relevant term shown in (a2) is satisfied. The data will be able to be set on the second access port 12.

This is the above-mentioned "A PORT SET ENABLE" condition.

With respect to the element data of the first access ports B, C and D 10, the set condition for the second access port 12 can be obtained under the same logical condition.

For example, the logical condition of “B PORT SET ENABLE” is AB, BC, CD, in the logical expression of FIG. 3 (a2).
It can be obtained by substituting DA.

The logical expression shown in (a2) of this figure is formed in a specific circuit in (b). A to D in this figure are respectively
"A PORT SET ENABLE", "B PORT SET ENABLE", ...
Is a logic circuit that generates

Next, a transition example of the VU pointer 11e will be described with reference to FIG.

The VU pointer 11e is A of the first access port 10.
When pointing to a port, elements 0, 1 of elements 0-3 sent from the vector unit (VU) 2
Meets the above-mentioned logical condition and the second access port 12
When set to (denoted by'S '), the VU
The pointer 11e indicates the C port 10 as shown in the figure, and the A port and the B port 10 have the following elements 4 and 4, respectively.
5 is set.

When the elements 2 to 4 are sent out in this state, the VU pointer 11e points to the B port 10, and when the element 5 is sent out, the VU pointer 11e points to the C port 10. To transition.

As described above, the present invention provides one to a plurality of main storage devices (M
SU), the main memory unit (MSU) is composed of a plurality of segments, has an access request bus corresponding to each segment, and is logically connected to the main memory unit (MSU). Per unit machine cycle from one or a plurality of processing units 2 to the main memory unit (MSU) of access requests for which one or a plurality of execution orders for executing programs are defined. A computer system having a main memory control unit (MCU) 1 for controlling transmission / reception, wherein one or a plurality of unit data are provided between the main memory control unit (MCU) 1 and the main memory unit (MSU). It has the access request bus corresponding to the length of the main memory control unit (M
CU) 1 is the main memory control unit (M
CU) 1 for valid bit, access address,
One or a plurality of first request ports for setting an access request corresponding to the access element, which has an access request composed of an operation code or the like, with the unit data length or a data length shorter than that as one access element. In the above computer system having the processing order of the access elements specified for executing the program, an access request from each processing device is sent to the main storage unit (MSU) in the first priority cycle. In the bus conflict check & other check section provided for the segment, the conflict check between the buses and the order guarantee in executing the program are guaranteed and set to the second request port. Therefore, in the second priority cycle, the set element is Even in the case of a random access request consisting of multiple unit data by performing only the bank busy check within the segment, the accessible unit data can be transmitted to the main storage unit (MSU) from moment to moment in each segment. There is a feature in doing so.

〔The invention's effect〕

As described above in detail, the main memory access control device of the present invention has an access request of a unit data length or a smaller data length to the main memory control unit (MCU) from one or more processing devices. A bus conflict check between the first access ports in which is set and the order in which the programs are executed is guaranteed by using a pointer, and the second access port is set to the second access port. As for the access request set in the port, only the bank busy in the port is checked and sent to the main memory unit (MSU). Therefore, it corresponds to each segment in the main memory control unit (MCU). In the second access port provided in the above, the above-mentioned pro- It is guaranteed ordering on running the ram element which is set to the second access port, an access efficiency is improved effect against possible transmission of every cycle and become main memory (MSU).

[Brief description of drawings]

FIG. 1 is a diagram schematically showing an embodiment of the present invention, FIG. 2 is a diagram for explaining a random access operation according to the present invention, and FIG. 3 is a diagram for explaining an operation of a request pointer control circuit of the present invention. 4 and FIG. 4 are diagrams for explaining the conventional main memory access control method. In the drawing, 1 is a main memory control unit (MCU), 10 is a first access port, 1st request port 10 'is an access port, 11 is a bus conflict & other check unit, 11a is a bus conflict check unit, 11b Is a bank busy check unit, 11c is another conflict check unit, 11d is a priority control unit, 11e is a pointer or VU pointer, 12 is a second access port, and a second request port 13 is a bank busy check unit in the SEG. , Are shown respectively.

Claims (2)

[Claims] 1. A main memory unit (MSU) comprising one to a plurality of main memory units (MSU), wherein the main memory unit (MSU) comprises a plurality of segments, and an access request bus is provided corresponding to each segment. Execution of one or more programs per unit machine cycle from one or more processing units (2) logically connected to the main memory unit (MSU) A computer system having a main memory control unit (MCU) (1) for controlling whether or not an access request having a specified order is issued to the main memory unit (MSU), the main memory control unit (MCU) (MCU) 1) and the main memory unit (MSU) have one or a plurality of access request buses corresponding to the unit data lengths respectively, and the main memory control unit (M
CU) (1) is the main memory control unit from the above processing unit (2)
(MCU) (1) access request consisting of valid bits, access address, operation code, etc., the unit data length or less than the data length as one access element, the access request corresponding to the access element In the computer system, which has one to a plurality of first request ports (10) to be set, and the execution order of the access elements is defined for executing a program, the first request port (10 ) Output, the access request bus to the main memory unit (MSU) is selected according to the designated position of the access address of any access request, and the second request port corresponding to the access request bus is selected.
When setting to (12), check the bus conflict &
In the other check unit (11), the conflict check between the segments and the execution order of the access requests, which is stipulated in executing the program, are guaranteed and performed.
In the output, only the contention between the segments in the local access bus is checked and the intra-segment bank busy check unit
A main memory access control device characterized by checking in (13) to decide whether or not to issue the own access request. 2. The main memory access control device, wherein the main memory control unit (MCU) (1) includes the main memory device (MSU).
The bus conflict check result of the access request in the bus conflict check & other check unit (11) provided for each segment of the above and a pointer (11e for defining the execution order in executing the program) )
Based on the second request port (1
First priority cycle mechanism (11) set to 2)
And a second priority cycle mechanism (13) for performing a bank busy check on the unit data in each segment in the intra-segment bank busy check unit (13), and in the first priority cycle mechanism (11), A bus conflict check provided for each request port of the first request port (10) and a conflict check between buses in another check unit (11),
The first request port (1
Access request from (0) is given the highest priority, and the access request is made in correspondence with each segment in the main memory unit (MSU) selected according to the rule of execution sequence for executing the program, and the second access port Set to (12), and in the second priority cycle mechanism (13), the intra-segment bank busy check unit (13) performs a bank busy check in the bus for each second request port (12). The main memory access control device according to claim 1, wherein an access request for each unit data is issued to each bank if it is not busy.