JPH06105862B2 - Non-linear signal processor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-linear signal processing device applied to a video tape recorder (hereinafter referred to as a VTR), a video disc or the like.

Conventional technology One of the non-linear signal processing devices is to enhance the high frequency range only when there is a large energy component in the high frequency range in order to secure the S / N ratio in the high frequency range by enhancing the high frequency range of the video signal. There is a non-linear emphasis that lowers the adverse effect of excessive emphasis. Figure 16 shows a model of the circuit for nonlinear emphasis. 1 is a first connection body in which a capacitor 2 and a resistor 3 are connected in parallel, 4 is a second connection body in which a resistor 8 is connected in parallel to a connection body in which a capacitor 7 is serially connected to two diodes 5 and 6 which are connected in anti-parallel Body, 9
Is an input terminal and 10 is an output terminal. Reference numeral 11 is an amplifier for adjusting the level of the output signal. In the above configuration, the capacitances of capacitor 2 and capacitor 7 are C ₁ and C ₂ , respectively, and the resistance
3. Let the resistance values of the resistor 8 be R ₁ and R ₂ , respectively. At this time, C ₁ ,
C ₂ , R ₁ and R ₂ have a relationship of C ₁ R ₁ = C ₂ R ₂ . Next, since the current flowing through the anti-parallel connection body of the two diodes 5 and 6 changes depending on the voltage applied to both ends of the diode, the anti-parallel connection body of the diodes 5 and 6 changes from conducting state to infinity by the voltage applied to both ends. It is regarded as a variable resistance, and its resistance value is Rd. The amplifier 11 uses the reciprocal R ₁ + R ₂ / R ₂ of the coefficient R ₂ / R ₁ + R ₂ divided by the resistors 3 and 8 as the amplification coefficient in order to make the signal levels of the input signal and the output signal the same.

The operation of the above configuration will be described. First, when the signal level of the input signal applied to the input terminal 9 is sufficiently low, the voltage across the anti-parallel connection body of the diodes 5 and 6 is also small, so almost no current flows, and its internal resistance Rd is infinite. Become. As a result, the second connection body 4 becomes equivalent to the configuration having only the resistor 8, and the example of FIG. 16 shows an emphasis characteristic that emphasizes a high frequency band like the gain characteristic of FIG. 17A. However, when the signal level of the input signal increases, the diode 5,
The voltage across both ends of the anti-parallel connection body of 6 also increases, and the current begins to flow. As a result, if the signal level of the input signal becomes sufficiently large, the current flowing through the antiparallel connection body of the diodes 5 and 6 becomes large, and the internal resistance thereof becomes conductive. Therefore, the second connection body 4 is equivalent to a parallel connection body of the resistor 8 and the capacitor 7. Here, the impedance of the second connection body 4 and the first connection body 1 is C ₁ R ₁ = C ₂ R _{2 described above.}
, The gain characteristics become constant as shown in FIG. 17B.

The above description will be given using the Laplace transform equation representing a continuous time system. Now, the transfer function H (s) of the example of FIG.
If C ₁ , C ₂ , R ₁ , R ₂ and Rd are used, the following equation is obtained.

Here, X, T, and Td are defined as follows.

X = R ₁ / R ₂ ………… (2) T = C ₁ R ₁ ＝ C ₂ R ₂ ………… (3) Td ＝ C ₂ Rd ………… (4) Above X If T, T, and Td are used, then H (s) is given by the following equation.

Or Now, the resistance Rd becomes infinite when the signal level of the input signal is sufficiently small, so that Td also becomes infinite according to the equation (4). Therefore, if Td is infinite in Eq. (6), then H
(S) is as follows.

Since the second term on the right side of the equation (7) is a high-pass filter, H (s) represents an emphasis characteristic that emphasizes high frequencies.

Next, when the signal level of the input signal is sufficiently high, the resistance Rd
Is zero in the conductive state, Td is also zero according to the equation (4). If Td is set to zero in the equation (6), H (s) = 1 (8), and a flat gain characteristic is obtained.

As explained above, the non-linear emphasis of FIG. 16 emphasizes the signal in the high frequency range when the signal level of the input signal is small, but has the characteristic that the degree of high frequency emphasis is reduced as the signal level of the input signal increases. It is used for VTRs and video discs to improve the S / N ratio in the high frequency range while preventing the harmful effects of excessive emphasis.

Problems to be Solved by the Invention However, the non-linear signal processing device such as the non-linear emphasis described above is configured by analog signal processing technology.
This is inferior to the digital IC in terms of integration, stability, etc. when the device is integrated into an IC. But the 16th
As in the case of nonlinear emphasis in the figure, a device that nonlinearly controls frequency characteristics according to the signal level of a signal in a wide band such as a video signal is realized by using digital signal processing technology in terms of circuit scale and speed. It wasn't easy in terms.

In view of the above points, the present invention provides a non-linear signal processing device that has a non-linear characteristic equivalent to that of a conventional analog signal processing technique, and that can be easily realized as a device using a digital signal processing technique with high integration and stability of the device. The purpose is to do.

Means for Solving the Problems The present invention relates to a first signal processing device for subjecting an input signal to predetermined processing, and a differential circuit for extracting a change per unit time of signal processing obtained from the first signal processing circuit, A non-linear circuit that non-linearly compresses the amplitude of the signal according to the amplitude of the signal, a delay circuit that delays the signal obtained from the non-linear circuit for a predetermined time, and a signal obtained from the delay circuit and the signal obtained from the difference circuit are introduced to the non-linear circuit. Non-linear signal processing circuit configured by an adder circuit and a multiplication circuit that multiplies a signal obtained from the non-linear circuit by a predetermined value and outputs the second signal processing that subjects the signal obtained from the non-linear signal processing circuit to predetermined processing Circuit,
A non-linear signal processing device comprising: an arithmetic operation circuit that arithmetically operates a signal obtained from a second signal processing circuit and the input signal and outputs the arithmetically operated signal.

The present invention has the above-described configuration, which applies a non-linear process to a time-varying component of a signal by a differential circuit and a closed-loop configuration including a non-linear circuit that performs non-linear compression for a signal obtained by subjecting an input signal to a predetermined process. After that, the signal that has been subjected to the predetermined processing and the input signal are arithmetically operated to obtain a characteristic equivalent to the non-linear characteristic by the conventional analog signal processing technology in terms of integration and stability. Can be realized by using the existing digital signal processing technology.

Practical Example FIG. 1 is a block diagram showing a first practical example of the nonlinear signal processing apparatus of the present invention. In FIG. 1, reference numeral 12 is an input terminal of a video signal digitized at a sampling period Δ, 13 is a first signal processing circuit for performing pre-processing for performing non-linear processing on the input video signal, and 14 is a first signal processing circuit. Signal processing circuit
A non-linear signal processing circuit for applying non-linear signal processing to the output 13, a second signal processing circuit 15 for post-processing the output of the non-linear signal processing circuit 14, and a reference numeral 16 for the input signal obtained from the input terminal 12 and the second And an output terminal for outputting the output of the arithmetic operation circuit 16 as an output signal of the present nonlinear signal processing device.

Here, FIG. 2 is a block diagram showing the configuration of the non-linear signal processing circuit 14. In FIG. 2, reference numeral 18 denotes an input terminal of the non-linear signal processing circuit 14, which is the first signal processing circuit 13
The signal derived from is input. 19 is the sampling period Δn
It is a difference circuit that extracts a signal change per unit time (n is an integer), and delays the signal for n times the sampling period nΔ, and subtracts the output of the delay circuit 20 from the input of the delay circuit 20. The subtraction circuit 21 is used. Reference numeral 22 is a non-linear circuit that non-linearly compresses the amplitude of the signal according to the amplitude of the signal. At this time, F is a compression coefficient multiplied to compress the amplitude of the signal.

Next, 23 is a delay circuit for delaying the output of the non-linear circuit 22 by nΔ. An adder circuit 24 adds the output of the differential circuit 19 and the output of the delay circuit 23 and guides it to the nonlinear circuit 22. Further, 25 is a multiplication circuit for multiplying the output of the non-linear circuit 22 by a predetermined value (K), 26 is an output terminal of the non-linear signal processing circuit 14, and the signal output from this terminal 26 is the second signal. It is guided to the processing circuit 15.

The operation of the non-linear signal processing apparatus according to this embodiment will be described below with reference to a circuit model diagram and a transfer function representing the characteristics of the circuit. As the transfer function, z represents a discrete-time system by using a Laplace transform formula representing a continuous-time system and a delay operator z ⁻¹ representing a signal delay of one sampling period Δ.
Use a conversion formula.

First, FIG. 3 is a diagram in which the antiparallel connection body of the diodes 5 and 6 is replaced by the variable resistor 27 in the model diagram of the circuit of the non-linear emphasis shown in FIG. The resistance value Rd of the variable resistor 27 changes to be equal to the internal resistance of the antiparallel connection body of the diodes 5 and 6 depending on the voltage that can be taken out from the terminal 28. The transfer function H (s) of the output signal from the output terminal 10 with respect to the input signal applied to the input terminal 9 is expressed by the above equations (1), (5) and (6). The function Hd (s) is as follows.

Further, by using X, T, Td from the equations (2), (3) and (4), Becomes Substituting this Hd (s) into the equation (6) gives H
Find (s).

Here, H ₁ (s), H ₂ (s), H ₃ (s) are defined as follows.

From equations (12), (13), and (14), XHd on the right side of equation (11)
(S) becomes XHd (s) = H ₁ (s) · H ₂ (s) ... (15), and H (s) is H (s) = 1 + H ₁ (s) · H ₂ (s ) ・ H ₃ (s) ………
It is expressed as (16). The circuit model of this equation (16) is as shown in FIG. In the figure, 29 is a circuit model of H ₁ (s), 30 is a circuit model of H ₂ (s), and 31 is a circuit model of H ₃ (s). The capacitance of capacitors 32 and 36 is C ₁ ,
Capacitance of capacitors 38 and 41 is C ₂ , resistance of resistor 33 is R ₁ , resistance of resistors 34 and 42 is R ₂ , resistance of resistor 37 is R ₁ R ₂ / R ₁ + R
₂ (resistor 37 is a parallel connection body of R ₁ and R ₂ ), and the resistance value of variable resistor 39 is Rd. Reference numerals 35 and 43 are buffers, and 40 is an amplifier having an amplification coefficient X (= R ₁ / R ₂ ). 44 is an adder, and 45 and 46 are an input terminal and an output terminal, respectively.

The circuit model 29 of H ₁ (s) shows a configuration in which the variable resistor 27 is infinite in the circuit model of FIG. 3, that is, a non-linear emphasis characteristic when the signal level of the input signal is sufficiently small.

The H ₂ (s) circuit model 30 constitutes a combined impedance of the H ₁ (s) circuit model 29 by the parallel connection body of the capacitor 36 and the resistor 37, and by the capacitor 38 and the variable resistor 39.
Configure HPF. At this time, when the signal level is sufficiently low, the resistance value Rd of the variable resistor 39 becomes infinite and passes the high frequency component as it is, but when the signal level increases, Rd decreases and its amplitude is compressed. Indicates. The circuit model 31 of H ₃ (s) is the HPF, and the adder 44
It plays the role of level adjustment when adding with the input signal.

Next, pay attention to the circuit model 30 of H ₂ (s). Capacitor 38
And the configuration of variable resistor 39 is HP that extracts only the high frequency component of the signal
It is F. Therefore, in order to simplify the circuit, the capacitor 36 and the resistor 37 immediately before the capacitor 38 are
The parallel connection of is approximated by a capacitor that does not pass low frequency components. Generally, the impedance of a capacitor is determined by the angular frequency of the signal at that time. Therefore, in order to determine the capacitance of the approximating capacitor, the angular frequency most required for approximating accuracy may be arbitrarily selected. For example, if the angular frequency is selected as the resonance angular frequency of the parallel connection body of the capacitor 36 and the resistor 37, the capacitance will be And if the infinite angular frequency is selected, the capacity becomes C ₁ . For convenience, the capacitance will be described as C ₁ . Capacitor
Approximating the parallel connection body of 36 and the resistor 37 with the capacitor of the capacitance C ₁ is nothing but the configuration in which the resistor 37 is removed. The structure is shown in FIG. In FIG. 5, the circuit model 47 is obtained by removing the resistor 37 in the circuit model 30 of FIG. 4, and the transfer equation H ₄ (s) is as follows.

Hereinafter, the model of the non-linear emphasis circuit shown in FIG. 5 is converted into a discrete time system.

As the sz conversion method for converting from the Laplace conversion formula to the z conversion formula, there are various effective methods such as the difference method and the bilinear conversion method, but in this description, the difference method is used as the simplest method. Perform sz conversion. The method based on this difference is a method of utilizing the fact that s in the Laplace transform equation is a differential operator and replacing this s with the difference operation in the z transform equation to transform. Using the delay operator z ⁻¹ and sampling period Δ, the conversion by the difference is as follows.

Using this equation (18), the circuit model H ₁ of 29, 47, 31 in FIG.
(S), H ₄ (s), H ₃ (s) are sz-converted to obtain H
Calculate ₁ (z), H ₄ (z), H ₃ (z).

From the above equations (19), (20), and (21), the transfer function H (z) of the nonlinear signal processing device of FIG.

H (z) = 1 + H ₁ (z) ・ H ₄ (z) ・ H ₃ (z) …………
(22) Here, in particular, H ₄ (z) in the equation (20) is modified to obtain the following equation.

From the above description, the nonlinear signal processing device of FIG. 1 according to the present embodiment exhibits the characteristic of non-linear emphasis by operating according to H (z) of the equation (22).
The first signal processing circuit 13 in FIG.
The second signal processing circuit 15 has an emphasis characteristic that is expressed by ₁ (z) and emphasizes the high frequency range of the signal, and the second signal processing circuit 15 uses the equation (21).
It has the characteristics of HPF represented by H ₃ (z). Further, the non-linear signal processing circuit 14 has the characteristic represented by the equation (23) H ₄ (z). Therefore, in the diagram showing the configuration of the non-linear signal processing circuit 14, the time at which the delay circuit 20 and the delay circuit 23 delay the signal from this H ₄ (z) is one sampling period Δ.
That is, the integer n is 1. The multiplier K by which the multiplication circuit 25 multiplies the signal is X. Then, the multiplier F by which the nonlinear circuit 22 multiplies the signal in order to compress the signal nonlinearly is It is represented by. Since Td on the right side of the equation (24) is proportional to the internal resistance Rd of the antiparallel connection body of the two diodes 5 and 6 (Fig. 16) according to the equation (4), its value also depends on the signal amplitude. It changes non-linearly. Therefore, the equation (24) F is also a non-linear coefficient, and this F determines the input / output characteristics of the non-linear circuit 22. This input / output characteristic is shown in FIG. In the figure, U on the horizontal axis represents an input signal to the non-linear circuit 22, and V on the vertical axis represents an output signal. The input / output characteristics will be described below.

Since Rd represents the internal resistance of the antiparallel connection of two diodes, its value is determined by the voltage-current characteristics of the diodes. The voltage-current characteristic of this diode is such that almost no current flows when the voltage applied to both ends of the diode is very small, and when the voltage exceeds the Knee potential, the current that flows sharply increases and approaches a conducting state. From this, the input / output characteristics of the non-linear circuit 22 will be examined using FIG. Now, if the amplitude of the input U is smaller than U _O and the current does not flow when the voltage across the diode is very small, then Rd becomes infinite in that range. Therefore, from equation (4), Td is infinite,
Furthermore, F takes a constant value of 1 from the equation (24). From the above,
When the input U is in the range of −U _O <U <U _O , the output V and the input U have a linear relationship (shown by the alternate long and short dash line in FIG. 6), and the inclination a (FIG. 6) at that time is 1. Next, the input / output relationship of the non-linear circuit 22 with respect to the input having a relatively large amplitude in which the amplitude of the input U exceeds U _O is examined. As the voltage across the diode increases, a current begins to flow out and the internal resistance Rd and Td decrease. Therefore, since F also becomes smaller than 1 from the equation (24), the curve showing the input / output characteristics (shown by the solid line) in FIG. 6 is separated from the straight line of V = aU when U exceeds U _O , and the amplitude of the output V is increased. Shows a compressed non-linear relationship. However, even if the voltage across the diode exceeds the Knee potential and becomes close to the conducting state, the internal resistance Rd does not become zero, so the output amplitude for a larger amplitude input is smaller than the output for a smaller amplitude input. The output amplitude is monotonically increasing with respect to the input amplitude, as shown in FIG. In addition,
In order to realize this input / output characteristic by a digital signal processing technique, it is possible to linearly approximate the characteristic and use a switch circuit, an addition / subtraction circuit or the like (shown by a broken line in FIG. 6).
ROM (Read Only Memory) that stores characteristics in advance
Is a very effective method without waveform distortion at the switch point.

As described above, according to the present embodiment, the first signal processing circuit 13 showing the emphasis characteristic, the non-linear signal processing circuit 14 that non-linearly compresses the temporal change of the signal, and the second signal processing circuit showing the HPF characteristic. By providing the signal processing circuit 15, the digital signal processing technology, which is superior in terms of integration and stability to the characteristics of non-linear emphasis that changes the emphasis amount nonlinearly according to the signal level of the input signal, is superior to the analog signal processing technology. Can be realized by

Next, a linear signal processor according to a second embodiment of the present invention will be described. Similar to the first embodiment showing the characteristic of non-linear emphasis, this embodiment also shows the characteristic of non-linear emphasis. FIG. 7 shows a block diagram of this embodiment. The configuration of FIG. 7 corresponds to the first of FIG.
In this embodiment, the output of the linear signal processing circuit 14 is directly led to the adding circuit 16 so that the second signal processing circuit 15 is not provided. The configuration of the linear signal processing circuit 14 is also the first
It is equivalent to the embodiment of FIG. The operation of this embodiment will be described below using a circuit model diagram and a transfer function.

In the circuit model of FIG. 5 used in the first embodiment, the transfer function of the circuit model 47 is H ₄ (s) of the equation (17),
The transfer function of the circuit model 31 is represented by H ₃ (s) in the equation (14). Both of these H ₄ (s) and H ₃ (s) are HPF. If H ₅ (s) is defined as the following equation, H ₅ (s) = H ₄ (s) ・ H ₃ (s) …………… (25) H ₅ (s) is also the HPF. is there. H ₅ (s) is (17), (1
From H ₄ (s) and H ₃ (s) in the equation 4), it is expressed as the following equation.

The circuit is simplified at this H ₅ (s). To know the gain and phase characteristics in the frequency domain of the circuit, s =
A common method is to use jω. At this time, ω represents the angular frequency of the signal, and when considering the gain characteristics, it may be considered that s becomes large for high frequency components and s becomes small for low frequency components. Now, in formula (26), H ₅
Since (s) has a characteristic as an HPF, consider simplification of the circuit that approximates the response in the high frequency region. The denominator in the fraction on the right side of Expression (26) is a quadratic expression of s. Therefore, if s is sufficiently large in this quadratic equation, the Oth order term of s, that is, the constant term can be approximately eliminated. If the transfer function approximated in this way is H ₆ (s), then H ₆ (s) is as follows.

From this equation, it can be seen that H ₆ (s) also has the characteristics of HPF.

According to the above approximation by the transfer function, the circuit model (FIG. 5) of the first embodiment can be obtained as shown in FIG. 8th
The circuit model shown in the figure differs from the circuit model shown in FIG. 5 in that the circuit model 48 and the circuit model 31 are not provided. In the circuit model 48, a variable resistor 39 and a resistor 49 are added in parallel. The resistance value can be represented by R ₁ + R ₂ .
This is because the circuit model 47 and the circuit model 31 in FIG. 5 are approximated to the circuit model 48 in FIG. 8 by the equation (27).

Hereinafter, the non-linear emphasis circuit model shown in FIG. 8 is sz-converted into a discrete-time system by using the difference method as in the first embodiment.

In FIG. 8, the characteristic H ₁ (s) of the circuit model 29 is the same as that of the circuit model 29 of FIG.
It is exactly equivalent to H ₁ (z) in the equation.

Next, regarding the characteristic H ₆ (s) of the circuit model 48,
8) s-z to convert equation becomes H ₆ of the formula (z).

This H ₆ (z) is transformed Becomes

From the above description, the characteristic H (z) of the non-linear signal processing device according to the present embodiment operates according to the following equation: H (z) = 1 + H ₁ (z) · H ₆ (z) (30) Non-linear emphasis It shows the characteristics of. 7th
In the figure, the first signal processing circuit 13 has exactly the same emphasis characteristic as in the first embodiment to emphasize the high frequency band of the signal, and the nonlinear signal processing circuit 14 has the equation ( ₆ ) H ₆
The delay circuit 20 and the delay circuit shown in FIG.
The delay time of 23 is Δ and the multiplier K of the multiplication circuit 25 is X, which is equivalent to the first embodiment, but the multiplier F multiplied by the nonlinear circuit 22 to nonlinearly compress the signal is (29). From the formula, It is represented by. Considering the multiplier F in the same way as described in the input / output relationship of the nonlinear circuit 22 of the first embodiment, T becomes infinite when the signal level is low, so that F
Is a constant value And F decreases as the signal level increases. Therefore, the input / output relationship is shown in FIG.
The input / output slope a when the signal level of It has the characteristics of

As described above, according to the present embodiment, by providing the first signal processing circuit 13 exhibiting the emphasis characteristic and the non-linear signal processing circuit 14 that non-linearly compresses the time variation of the signal,
The characteristic of non-linear emphasis, which changes the emphasis amount nonlinearly according to the signal level of the input signal, can be realized by the digital signal processing technique, and the second signal processing is different from the first embodiment of the present invention described above. The feature is that the circuit 15 is unnecessary and the circuit scale is reduced.

Next, a third embodiment of the present invention will be described. The configuration of this embodiment is represented by the same block diagram as FIG. 1, which is the first embodiment of the present invention. The third embodiment differs from the first embodiment in that the characteristic of the first signal processing circuit 13 in FIG. 1 is the characteristic of the HPF for extracting the high frequency component of the signal. Hereinafter, description will be made using a circuit model.

First, in the above description of the first embodiment of the present invention, the parallel connection body of the capacitor 36 and the resistor 37 of the circuit model 30 of FIG. 4 is approximated by a capacitor that does not pass a reducing component, and the circuit model of FIG. The circuit has been simplified to 47. In a similar manner to this, the parallel connection body of the capacitor 32 and the resistor 33 of the circuit model 29 of FIG. 5 is immediately followed by the circuit model 47 having the HPF characteristic.
In the sense that the above is configured, the circuit model 29 in FIG. 5 can be configured by the circuit model 50 as shown in the circuit model of non-linear emphasis in FIG. The angular frequency for determining the capacitance of the capacitor that is approximated by the circuit model 50 is the 5th
The resonance frequency of the parallel connection body of the resistor 33 of the capacitor 32 in the figure may be used, but in the present embodiment as well, as in the case of the first embodiment, an infinite angular frequency is selected for convenience, and Make the configuration without 33.

The ninth model obtained by approximating the circuit model 29 shown in FIG.
The transfer function H ₇ (s) of the circuit model 50 shown in the figure is expressed by the following equation.

This H ₇ (s) is sz-converted by the method of the difference according to the equation (18) to obtain H ₇ (z) of the following equation.

As can be seen from H ₇ (s) in this equation, H ₇ (z) has the characteristic of HPF that allows only the high frequency components of the signal to pass.

From the above description, the configuration of the non-linear signal processing apparatus of this embodiment is shown in FIG. 1, and the characteristic of the first signal processing circuit 13 in the figure is the characteristic of the HPF represented by H ₇ (z) in the equation (33). The characteristics of the non-linear signal processing circuit 14 and the second signal processing circuit 15 are the same as those of the first embodiment (23).
It is represented by H ₄ (z) in the equation and H ₃ (z) in the equation (21). Therefore, the characteristic H (z) of this embodiment operates according to the following equation, and H (z) = 1 + H ₇ (z) · H ₄ (z) · H ₃ (z) ....
(34) It shows the characteristics of non-linear emphasis.

As described above, according to the present embodiment, the first signal processing circuit 13 that passes the high frequency component of the signal, the non-linear signal processing circuit 14 that non-linearly compresses the temporal change of the signal, and the HPF characteristic By providing the second signal processing circuit 15 and the second signal processing circuit 15, it is possible to realize the characteristic of non-linear emphasis in which the emphasis amount is changed nonlinearly according to the signal level of the input signal by the digital signal processing technique.
In comparison with the embodiment of FIG. 3, the characteristic of the first signal processing circuit 13 has the HPF characteristic that passes only the high frequency component, not the emphasis characteristic in which the high frequency component is added to the DC component. Is small and the circuit scale is small.

Next, a fourth embodiment of the present invention will be described. The configuration of this embodiment is the same as that of FIG. 7 showing the configuration of the second embodiment described above, but in FIG. 7, the characteristic of the first signal processing circuit 13 is that of the HPF for extracting the high frequency component of the signal. It shows the characteristics. The circuit model will be described below.

First, in the third embodiment, the circuit model 29 of FIG. 5 is simplified to the circuit model 50 of FIG. In the second embodiment, the circuit model 47 and the circuit model 31 shown in FIG.
The circuit model 48 in the figure has been simplified. It has been explained that both the circuits shown in FIGS. 9 and 8 operate as non-linear emphasis. However, as shown in FIG. 10, the circuit composed of the circuit models 50 and 48 also operates as non-linear emphasis. To do. The characteristic H (s) is H (s) = 1 + H ₇ (s) · H ₆ (s) ... Using H ₇ (s) of the equation (32) and H ₆ (s) of the equation (27). It is expressed as (35), and this H (s) is s-
The z-transformed characteristic H (z) is given by H ₇ (z) of the equation (33),
Using H ₆ (z) in equation (29), H (z) = 1 + H ₇ (z) · H ₆ (z) ……………… (36) (Z) also operates as non-linear emphasis. Moreover, with the above-mentioned configuration, the output dynamic range can be reduced because the characteristic of the first signal processing circuit 13 has the HPF characteristic as compared with the second embodiment, and in addition to the third embodiment. On the other hand, since the second signal processing circuit 15 is not provided, the circuit scale is small.

Next, a non-linear signal processing device which is a fifth embodiment of the present invention will be described. In the same way that the first to fourth embodiments show the characteristics of non-linear emphasis, this embodiment also shows the characteristics of non-linear emphasis. A block diagram of this embodiment is shown in FIG. 11, in which the same components as those in FIG. 1 are designated by the same reference numerals. The input signal obtained from the input terminal 12 is directly guided to the non-linear signal processing circuit 14 and processed by the second signal processing circuit 15 to add the input signal and the output of the second signal processing circuit 15 in the post-arithmetic operation circuit 51. Lead to output terminal 17. The arithmetic operation circuit 51 has an addition function and will be described below as the addition circuit 16.

In the circuit model of FIG. 9 used in the description of the third embodiment, the transfer function of the circuit model 50 is the equation (32) H ₇ (s)
Further, the circuit model 47 is represented by the equation (17) H ₄ (s), and both H ₇ (s) and H ₄ (s) have the characteristics of HPF. With respect to the two HPF H ₇ (s) and H ₄ (s) connected to each other, the method ((25), (2
6) and (27) are used) to simplify the circuit.
First, H ₈ (s) is defined by the following equation.

This H ₈ (s) also has the characteristic of HPF. Here, paying attention to the high frequency component, the quadratic expression of s, which is the denominator in the fraction on the right side of Expression (37), is approximated to a linear expression. Considering that s is sufficiently large in response to high frequency components, the quadratic equation eliminates the constant term. In this way, the transfer function approximating H ₈ (s) is
When _{9 (s), H 9 (} s) is expressed by the following equation.

From this equation, it can be seen that H ₉ (s) also has HPF characteristics.

When the transfer function is approximated as described above, the rotation model of this embodiment is as shown in FIG. This circuit model differs from the circuit model of FIG. 9 in that there is no circuit model 50 and the circuit model 52. Circuit model 52 has its characteristics (38)
Since it is expressed by the formula H ₉ (s), it becomes a variable resistor 39 of the circuit model 47 of FIG. 9 to which a resistor 53 (resistance value (R ₁ + R ₂ ) R ₂ / R ₁ is added in parallel.

Hereinafter, the model of the circuit of non-linear emphasis shown in FIG. 12 is sz-converted into a discrete-time system using the method by the difference of the above equation (18). From the equation (38), the transfer function H ₉ (z) of the circuit model 52 is The circuit model 31 is H ₃ (z) in the equation (21).

From the above description, the characteristic (Hz) of the non-linear signal processing device according to the present embodiment operates according to the following equation: H (z) = 1 + H ₉ (z) · H ₃ (z) (40) Non-linear emphasis It shows the characteristics of.

Since the nonlinear signal processing circuit 14 in this embodiment is expressed by the equation (39), H ₉ (z), the delay time of the delay circuit 20 and the delay circuit 23 in FIG. 2 is Δ.
And the multiplication K by which the multiplication circuit 25 multiplies the signal is X.
However, the multiplier F that the non-linear circuit 22 multiplies to compress the signal in a non-linear manner is given by the equation (39). It is represented by. This value of F is a constant value from the equation (41) because Td becomes infinite when the signal level of the signal input to the nonlinear circuit 22 is small. Therefore, the input / output relationship in the nonlinear circuit 22 is However, when the signal level increases, Td decreases accordingly, so that F also decreases and the signal is compressed. The above input / output relationship shows that the slope a when the signal level of the input U is small in FIG. Has the same shape characteristics as.

As described above, according to the present embodiment, by providing the non-linear signal processing circuit 14 that non-linearly compresses the time change of the signal and the second signal processing circuit 15 that exhibits the characteristics of the HPF, the signal of the input signal is The characteristic of non-linear emphasis which changes the amount of emphasis non-linearly depending on the level can be realized by the digital signal processing technique, and there is no first signal processing circuit 13 as compared with the first or third embodiment of the present invention. Therefore, there is a feature that the circuit scale can be extremely reduced.

The embodiments having the characteristics of non-linear emphasis have been described above as the non-linear signal processing device of the present invention. However, in the following, a non-linear signal processing device having a characteristic of non-linear de-emphasis which is an inverse characteristic of non-linear emphasis will be described.

FIG. 13 is a block diagram of a nonlinear signal processing device which is a sixth embodiment of the present invention. The present embodiment is different from the configuration of FIG. 11 described above in that the signal input to the input terminal 12 is a non-linearly emphasized video signal, and the output terminal 17
The signal outputted from the input terminal 12 is a signal obtained by non-linear de-emphasis of the signal inputted to the input terminal 12, and the second signal processing circuit from the signal obtained by the arithmetic operation circuit 51 from the input terminal 12
It has a subtraction circuit 54 for subtracting the signal obtained from 15.
Further, the non-linear signal processing circuit 14 is exactly the same as the configuration of FIG. 2, but in order to distinguish it from the case of the non-linear emphasis, the non-linear circuit 22 in FIG. 2 compresses the signal non-linearly. For this purpose, the multiplier to be used is F ', and the multiplier to be used by the multiplication circuit 25 to multiply the signal is K'. The operation will be described below.

The transfer function representing the characteristic of the non-linear emphasis described in the prior art is shown in equation (6). H in this equation (6)
In order to return the signal non-linearly emphasized by (s) to the original signal, the characteristic of non-linear de-emphasis of 1 / H (s) is required. Now, let G (s) be the characteristic of this non-linear de-emphasis.
(S) is given by the following equation.

Here, G ₁ (s) and G ₂ (s) are defined by the following equation.

These G ₁ (s) and G ₂ (s) are s− by the above equation (18).
Z-transform is performed to obtain the following G ₁ (z) and G ₂ (z).

Therefore, G (Z) obtained by s-z conversion of the transfer function G (s) showing the non-linear de-emphasis characteristic of the equation (42) is
From equations (45) and (46), G (z) = 1-G ₁ (z) · G ₂ (z) …………… (47) From the above, in the configuration of FIG. The signal processing circuit 14 is G ₁ (z), and the second signal processing circuit 15 is
It shows the characteristics of HPF and is represented by G ₂ (z). The nonlinear signal processing circuit 14 is shown in FIG.
And the delay circuit 23 delays the signal by time Δ, the value of the multiplier K'multiplied by the multiplication circuit 25 on the signal is X / 1 + X according to the equation (45), and is multiplied by the nonlinear circuit 22 to compress the signal nonlinearly. The multiplier F ′ is Is. The value of this F'is a constant value 1 from Eq. (48) because Td becomes infinite when the signal level of the input of the non-linear circuit 22 is small, so the input / output relationship is linear with a slope of 1, but non-linear. If the signal level at the input of circuit 22 becomes high, Td
As the value of becomes smaller and F becomes smaller, the signal is compressed. The input / output relationship of the non-linear circuit 22 is the same as that in the case where the inclination a when the signal level of the input U is small is set to 1 in FIG.

As described above, according to the present embodiment, the non-linear circuit 14 that non-linearly compresses the time variation of the signal and the second HPF characteristic.
By providing the signal processing circuit 15 and the arithmetic operation circuit 51 having a subtraction function, it is possible to easily realize the characteristics of non-linear de-emphasis for returning the non-linear emphasis signal to the original signal by the digital signal processing technology. is there.

Next, a seventh embodiment of the present invention will be described. A block diagram of this embodiment is shown in FIG. Compared to the configuration shown in FIG. 13, the configuration shown in FIG.
16) and the subtraction function (subtraction circuit 54) can switch between these two outputs and lead them to the output terminal 17, and the configuration of the nonlinear signal processing circuit 14 is as shown in the block diagram of FIG. is there. The configuration of the non-linear signal processing circuit 14 of FIG. 15 is 22a (K), 22b even if the non-linear circuit 22 compresses the signal non-linearly as compared with the second configuration.
Two characteristics can be switched as in (K '), and the multiplier circuit 25 can switch and output two multipliers as in 25a (K) and 25b (K'). .

With the above configuration, the nonlinear signal processing device of the present embodiment,
Multiplier F of the nonlinear circuit 22 configuring the nonlinear signal processing circuit 14
And F ', the multipliers K and K'of the multiplication circuit 25, and the addition and subtraction functions of the arithmetic operation circuit are switched to show the characteristic of non-linear emphasis and the characteristic of non-linear de-emphasis. The operation will be described below.

First, the fifth embodiment of the present invention has a characteristic of non-linear emphasis, and its transfer function is H of the equation (40).
Is expressed by (z), and H ₉ (z) is expressed by Eq.
₃ (z) is expressed by equation (21). On the other hand, the sixth embodiment has the characteristic of non-linear de-emphasis, and the transfer function is represented by G (z) in the equation (47),
G ₁ (z) is expressed by the equation (45), and G ₂ (z) is expressed by the equation (46). Here, from equations (21) and (46), H ₃ (z) = G ₂ (z) ………… (49) Therefore, the configuration showing the characteristics of the nonlinear emphasis of FIG. In the configuration showing the characteristic of non-linear de-emphasis in the figure, the second signal processing circuit 15 is
It has the characteristics of HPF as shown on the right side of equation (1) or equation (46). The differences are the characteristics of the nonlinear signal processing circuit 14 and the arithmetic function of the arithmetic operation circuit 51. Therefore, in the present embodiment, the second signal processing circuit 15 in FIG.
The characteristics of the HPF expressed by the formula (1) (formula (46)) are provided, and the configuration of the nonlinear signal processing circuit 14 is as shown in FIG. So that the nonlinear circuit 22b can be switched to the multiplier F'of the equation (48) so that the multiplier K of the multiplier circuit 25a is set to X according to the equation (21).
The multiplier K'of is set to X / 1 + X from the equation (46). Further 14th
The arithmetic operation circuit 16 shown in the figure can switch two operation functions like the addition circuit 16 and the subtraction circuit 54. According to the above configuration, the nonlinear circuit 22 is the nonlinear circuit 22a, the multiplication circuit 25 is the multiplication circuit 25a, and the arithmetic operation circuit 16 is the addition circuit 1.
The characteristics of this embodiment are the same as the above (4
The characteristic of the non-linear emphasis of the expression (0) is shown, and conversely, the characteristic of the non-linear de-emphasis of the expression (47) is shown when switching to the non-linear circuit 22b, the multiplying circuit 25b and the subtracting circuit.

As described above, according to the present embodiment, two characteristics of non-linear emphasis and non-linear de-emphasis are realized with the same configuration and the circuit is shared, so that the circuit scale can be reduced and it is very effective.

The second and third embodiments are smaller than the first embodiment in terms of circuit scale, but in terms of the degree of approximation of the characteristics of non-linear emphasis, the first embodiment is better. Can be said to have a high degree of approximation. The same can be said for the fourth and fifth embodiments.

As described above, according to the present invention, the characteristics and the degree of integration equivalent to the nonlinear characteristics obtained by the conventional analog signal processing technique,
It can be realized by using the digital signal processing technology which is excellent in stability, and it can be used especially for the IC of the signal processing unit such as VTR and video disk, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of a non-linear signal processing device in one embodiment of the present invention, FIG. 2 is a block diagram of a non-linear signal processing circuit constituting the same embodiment, and FIGS. 3 to 5 are the same embodiments. 6 is a circuit model diagram for explaining the operation of FIG. 6, FIG. 6 is an input / output relational diagram of a non-linear circuit constituting the non-linear signal processing apparatus of the present invention, and FIGS. 7, 11, 13, and 14 are other diagrams. 8 is a block diagram of the non-linear signal processing device in the embodiment of FIG.
10 and 12 are circuit model diagrams for explaining the operation of another embodiment, and FIG. 15 is a block diagram showing another configuration of the non-linear signal processing circuit constituting the non-linear signal processing device of the present invention. FIG. 16 is a circuit model diagram of a conventional nonlinear signal processing device, and FIG. 17 is a characteristic diagram of the conventional example. 13 ... First signal processing circuit, 14 ... Non-linear signal processing circuit, 15 ... Second signal processing circuit, 16, 24 ... Addition circuit, 1
9 ... Difference circuit, 20,23 ... Delay circuit, 21,54 ... Subtraction circuit, 22 ... Non-linear circuit, 25 ... Multiplication circuit, 51 ... Arithmetic operation circuit.

Claims (10)

[Claims] 1. A first signal processing circuit for subjecting an input signal to a predetermined processing, a difference circuit for extracting a change amount of a signal obtained from the first signal processing circuit per a predetermined time, and a signal based on the amplitude of the signal. A non-linear circuit that compresses the amplitude of the non-linearity, a delay circuit that delays a signal obtained from the non-linear circuit for a predetermined time, and a signal obtained from the delay circuit and the signal obtained from the difference circuit A non-linear signal processing circuit including a circuit and a multiplication circuit that multiplies a signal obtained from the non-linear circuit by a predetermined value and outputs the multiplied signal; second signal processing that subjects the signal obtained from the non-linear signal processing circuit to predetermined processing A non-linear signal processing device, comprising: a circuit; and an adder circuit that adds and outputs the signal obtained from the second signal processing circuit and the input signal. 2. A non-linear circuit outputs a signal compressed by a certain compression ratio when the amplitude of the signal input to the non-linear circuit is small, and when the amplitude of the signal is large or large, the above-mentioned constant value is maintained. Output a signal compressed with a compression ratio greater than the compression ratio, but ensure that the amplitude of the output for a signal with an amplitude is not greater than the amplitude of the output for a signal with an amplitude greater than that amplitude. 3. The nonlinear signal processing device according to claim 1, wherein the first signal processing circuit has an emphasis characteristic and the second signal processing circuit has a high-pass filter characteristic. 3. A non-linear circuit outputs a signal compressed by a certain compression rate when the amplitude of the signal input to the non-linear circuit is small, and when the amplitude of the signal is large, the larger the signal amplitude is, the more the constant value becomes. Output a signal compressed with a compression ratio greater than the compression ratio, but ensure that the amplitude of the output for a signal with an amplitude is not greater than the amplitude of the output for a signal with an amplitude greater than that amplitude. The nonlinear signal processing device according to claim 1, wherein the first signal processing circuit has a high-pass filter characteristic and the second signal processing circuit has a high-pass filter characteristic. 4. A first signal processing circuit for subjecting an input signal to a predetermined processing, a difference circuit for extracting a variation of the signal obtained from the first signal processing circuit per a predetermined time, and a signal based on the amplitude of the signal. A non-linear circuit that compresses the amplitude of the non-linearity, a delay circuit that delays a signal obtained from the non-linear circuit for a predetermined time, and a signal obtained from the delay circuit and the signal obtained from the difference circuit A non-linear signal processing circuit including a circuit and a multiplication circuit that multiplies a signal obtained from the non-linear circuit by a predetermined value and outputs the product; an adder circuit that adds and outputs the signal obtained from the non-linear signal processing circuit and the input signal A non-linear signal processing device comprising: 5. A non-linear circuit outputs a signal compressed by a certain compression ratio when the amplitude of the signal input to the non-linear circuit is small, and when the amplitude of the signal is large or large, the above-mentioned constant value is maintained. Output a signal compressed with a compression ratio greater than the compression ratio, but ensure that the amplitude of the output for a signal with an amplitude is not greater than the amplitude of the output for a signal with an amplitude greater than that amplitude. The nonlinear signal processing device according to claim 4, wherein the first signal processing circuit has an emphasis characteristic. 6. A non-linear circuit outputs a signal compressed by a certain compression ratio when the amplitude of the signal input to the non-linear circuit is small, and when the amplitude of the signal is large or large, the above-mentioned constant value is maintained. Output a signal compressed with a compression ratio greater than the compression ratio, but ensure that the amplitude of the output for a signal with an amplitude is not greater than the amplitude of the output for a signal with an amplitude greater than that amplitude. The nonlinear signal processing device according to claim 4, wherein the first signal processing circuit has a high-pass filter characteristic. 7. A differential circuit for extracting a change amount of an input signal per predetermined time, a non-linear circuit for nonlinearly compressing the amplitude of the signal according to the amplitude of the signal, and a delay for delaying a signal obtained from the non-linear circuit for a predetermined time. A circuit, an adder circuit for adding a signal obtained by the delay circuit and a signal obtained by the difference circuit to the non-linear circuit, and a multiplication circuit for multiplying the signal obtained by the non-linear circuit by a predetermined value and outputting the product. A non-linear signal processing circuit, a second signal processing circuit for subjecting a signal obtained from the non-linear signal processing circuit to a predetermined process, and an arithmetic operation of the signal obtained from the second signal processing circuit and the input signal to output the signal. A nonlinear signal processing device comprising an arithmetic operation circuit. 8. A non-linear circuit outputs a signal compressed by a certain compression ratio when the amplitude of a signal input to the non-linear circuit is small, and when the amplitude of the signal is large or large, the above-mentioned constant value is maintained. Output a signal compressed with a compression ratio greater than the compression ratio, but ensure that the amplitude of the output for a signal with an amplitude is not greater than the amplitude of the output for a signal with an amplitude greater than that amplitude. The nonlinear arithmetic operation according to claim 7, wherein the arithmetic operation circuit adds the signal obtained from the second signal processing circuit and the input signal, and the second signal processing circuit has a high-pass filter characteristic. Signal processing device. 9. A non-linear circuit outputs a signal compressed by a certain compression ratio when the amplitude of a signal input to the non-linear circuit is small, and when the amplitude of the signal is large or large, the above-mentioned constant value is maintained. Output a signal compressed with a compression ratio greater than the compression ratio, but ensure that the amplitude of the output for a signal with an amplitude is not greater than the amplitude of the output for a signal with an amplitude greater than that amplitude. 8. The non-linear signal according to claim 7, wherein the arithmetic operation circuit subtracts the signal obtained from the second signal processing circuit from the input signal, and the second signal processing circuit has a high-pass filter characteristic. Processing equipment. 10. A non-linear circuit outputs a signal compressed by a certain compression ratio when the amplitude of a signal input to the non-linear circuit is small, and when the amplitude of the signal is large or large, the above-mentioned constant value is maintained. Outputs a signal compressed at a compression rate higher than the compression rate, but has two compression characteristics such that the output for a signal of a small amplitude does not become larger than the output for a signal of a large amplitude. So that the multiplication circuit multiplies a predetermined value by using two values and the arithmetic circuit can input the signal obtained from the second signal processing circuit With the two calculation functions, that is, a calculation function for adding a signal and a calculation function for subtracting the signal obtained from the second signal processing circuit from the input signal, the two calculation functions are arbitrarily switched. Of the two non-linear circuits, the two values of the multiplication circuit, and the two arithmetic functions of the arithmetic operation circuit, so that the second signal processing circuit has the characteristics of a high-pass filter. Claim 7: The characteristics of the device when one of the characteristics, the value and the arithmetic function are combined, and the characteristics of the other when the characteristics, the value and the arithmetic function are combined are opposite to each other. Non-linear signal processing device according to item.