JPH06105289A - Muse decoder - Google Patents

Abstract

PURPOSE:To enlarge a band width in a vertical direction for a still picture area which can not be detected by a two-frame difference movement detecting circuit. CONSTITUTION:A movement detecting circuit discriminates a still picture, animation, and sub-still picture. A selector circuit selects one of a signal obtained after an inter-frame and inter-field insertion processing is operated to the still picture area by an inter-frame and inter-field insertion processing circuit, and the signal obtained after an inter-field and in-field insertion processing is operated to the sub-still picture area by an inter-field and in-field insertion processing circuit, based on the first output signal outputted from the movement detecting circuit. An MIX circuit proportionally mixes the signal obtained after an in-field insertion processing is operated to an animation area by an in-field insertion processing circuit with the signal selected by the selector circuit, based on the second output signal outputted from the movement detecting circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MUSE decoder installed in a MUSE type television receiver for decoding a MUSE signal.

[0002]

2. Description of the Related Art At present, the development of a high-definition television (high definition television) system using satellite broadcasting has already reached the stage of practical application.
The ub-nyquist Sampling Encoding) method is used.

In this MUSE system, the bandwidth is 22 MHz.
Frequency conversion is performed on the baseband signal including the luminance signal and the chrominance signal having a bandwidth of 7 MHz, and this is converted into a satellite broadcast bandwidth 27.
This baseband signal is band-compressed to about 8.1 MHz for transmission using one channel of MHz. This band compression is performed by thinning out a complete sampling point group extracted from the original video signal according to a predetermined rule.
At the time of thinning out the sampling points, the offset between fields is adjusted by utilizing the physiological characteristics of the viewer that the resolution in the diagonal direction on the screen is lower than in the vertical and horizontal directions.
Sampling is performed. It also utilizes the physiological characteristic of the viewer that the image quality does not deteriorate so much in the moving area even if the resolution is slightly reduced.

The decoder on the receiving side reproduces the sampling points decimated by the encoder on the transmitting side based on the sampling point groups before and after actually transmitted and received, so-called interpolation processing. Is supposed to do. This interpolation processing includes field interpolation performed using adjacent sampling point groups in the same field and inter-field interpolation performed using sampling point groups at corresponding positions in adjacent fields. In this interpolation processing, the moving image area and the still image area are detected from the reception screen,
Field interpolation is performed for the moving image area, and interfield interpolation is performed for the still image area. Of these, inter-frame interpolation processing may be used as a special type of inter-field interpolation.

The interpolation process will be described in detail below.

FIG. 9 shows a main part of a conventional MUSE decoder. This device is provided with an interframe interfield interpolation processing circuit (11), a motion detection circuit (12), and a field interpolation processing circuit (13), and MUSE converted from an input terminal (14) into a digital signal. A signal is input.

Of these, the inter-frame inter-field interpolation processing circuit (11) is adapted to perform so-called inter-frame inter-field interpolation for interpolating pixels over four fields in a still image area and reproducing an image. The side is connected to an input terminal (16) of a mixing circuit (hereinafter referred to as MIX circuit) (15).

The field interpolation processing circuit (13) is adapted to perform so-called field interpolation for reproducing an image by interpolating pixels in only one field in the moving image area, and its output side is a MIX circuit (15). ) Input terminal (1
8) is connected.

The output side of the motion detection circuit (12) is M
It is connected to the input terminal (17) of the IX circuit (15).

The output signal from the MIX circuit (15) is output from the output terminal (19) and input to the circuit in the subsequent stage.

In the conventional MUSE decoder having the above-mentioned structure, different processing is performed in the still picture area and the moving picture area. Therefore, the motion detection circuit (12) discriminates between the still image area and the moving image area.

FIG. 10 shows a motion detection circuit (1
2) is a detailed representation. This circuit is provided with 1-frame delay circuits (21) and (22) that delay each pixel by 1 frame. Of these, the first
The 1-frame delay circuit (21) includes an input terminal (23)
One of the three MUSE signals that are input from the MUX signal is input. The other two signals divided into three are respectively fed to the first and second subtractors (24) and (2
Input to 5).

The output side of the first one-frame delay circuit (21) is branched into two and connected to the second one-frame delay circuit (22) and the first subtractor (24), respectively.

The output side of the second one-frame delay circuit (22) is connected to the second subtractor (25).

The first subtractor (24) is connected to one of the inputs of the maximum value selection circuit (28) via the low pass filter (26) (LPF) and the first absolute value circuit (27),
The second subtractor (25) is connected to the other input of the maximum value selection circuit (28) via the second absolute value circuit (29).

The output side of the maximum value selection circuit (28) is connected to a non-linear constant generation circuit (31) having an output terminal (32).

The motion detection circuit (12) having the above-mentioned configuration
The operation of will be described.

The motion detection circuit (12) detects a region in which motion is intense, that is, a high frequency component at a time frequency, by a so-called interframe coding method, and determines a still image or a moving image for each pixel.

In FIG. 10, the difference between the signal input from the input terminal (23) and the signal delayed by one frame by the first one-frame delay circuit (21) is calculated by the first subtractor (24). Desired. This difference signal has its high frequency band cut by a low-pass filter (26) of 4.05 MHz,
After the absolute value is taken by the absolute value circuit (27), it is input to the maximum value selection circuit (28) as the first motion detection signal (34).

On the other hand, the signal input from the input terminal (23) and the signal further delayed by one frame by the second one-frame delay circuit (22) are the second subtractor (25).
Then, the difference is obtained. This difference signal has its absolute value taken by the second absolute value circuit (29) and is input to the maximum value selection circuit (28) as the second motion detection signal (35).

Here, the reason why one frame difference is also taken into consideration is as follows. Generally MUSE
In the case of the method, motion detection based on a 2-frame difference is mainly used, but aliasing distortion due to interframe / interline offset subsampling does not exist in the horizontal frequency band of 0 to 4.05 MHz of the MUSE signal. Therefore, this 0
Even in the 4.05 MHz region, it is possible to detect the motion by the difference of one frame.

The maximum value selection circuit (28) selects the larger one of these two types of motion detection signals (34) and (35) and inputs it to the non-linear constant generation circuit (31).

The non-linear constant generating circuit (31) outputs from the output terminal (32) a motion detection signal having a finite number, that is, a 2n level value represented by n bits (n is a natural number). For example, when it is determined that the result of the 2-frame difference detection is the moving image area and the result of the 1-frame difference detection is the still image area, or the result of the 2-frame difference detection is the still image area and the result of the 1-frame difference detection is the moving image area. If determined, this circuit determines that it is a moving image area.

The motion detection signal output from the output terminal (32) is input to the input terminal (17) of the MIX circuit (15).

FIG. 11 shows the MIX circuit (15) in detail. With this circuit, three input terminals 16-1
Output signals of the interframe interfield interpolation processing circuit (11), the motion detection circuit (12), and the field interpolation processing circuit (13) of FIG. 9 are input from 8 respectively.

Of these, the data input from the inter-frame inter-field interpolation processing circuit (11) via the input terminal (16) and the input signal from the motion detection circuit (12) (1
The data input via 7) and the polarity of which is inverted by the inverter circuit (37) are multiplied by the first multiplier (36) and input to the adder (39).

On the other hand, the field interpolation processing circuit (13)
From the input terminal (18) and the data input from the motion detection circuit (12) via the input terminal (17) are multiplied by the second multiplier (38) and added. (39) is input. Further, the adder (39) adds these and outputs from the output terminal (19).

That is, in this MIX circuit (15), the still picture path input from the inter-frame inter-field interpolation processing circuit (11) and the moving picture path input from the field interpolation processing circuit (13). The pixels are proportionally mixed for each pixel by the motion detection signal output from the motion detection circuit (12).

Assuming that the signal of the moving picture path is A, the signal of the still picture path is B, and the motion detection signal is K, the output signal M of the MIX circuit (15) is as follows. However, K
Is a positive number less than or equal to 1.

M = K · A + (1−K) · B In Japanese Patent Laid-Open No. 2-100484, a still picture processing system and a moving picture processing system having a moving picture enhancing function are provided, and their outputs are converted into motion signals. A configuration is disclosed in which a still image enhancer is provided in which the amount of enhancement can be varied by a motion signal after proportional mixing.

[0031]

Since the conventional MUSE decoder has the structure as described above,
There is a problem in that a still image area that cannot be detected by the frame difference detection is processed for the moving image area.

Therefore, there is a problem that the above problems must be solved.

The present invention has been made to solve the above problems, and provides a MUSE decoder capable of expanding the vertical bandwidth for a still image area that cannot be detected by the two-frame differential motion detection circuit. With the goal.

[0034]

The MUSE decoder according to the present invention (i) determines whether the input MUSE baseband signal is a still picture area, a moving picture area, or a quasi still picture area, A motion detection circuit that outputs first and second determination result output signals; (ii) an inter-frame inter-field interpolation processing circuit that performs inter-frame inter-field interpolation processing for an image belonging to a still image area; and (iii) An inter-field field interpolation processing circuit for performing inter-field field interpolation processing for images belonging to the quasi-still image area, and (iv) a field interpolation processing circuit for performing field interpolation processing for images belonging to the moving image area. , (V) The output signal of the inter-frame inter-field interpolation processing circuit and the inter-field inter-field interpolation based on the first determination result output signal output from the motion detection circuit. Within the field, the output signal selected by the selection circuit and the output signal selected by the selection circuit based on the second determination result output signal output from the motion detection circuit and the selection circuit selecting the corresponding one of the output signals of the processing circuit And a mixing circuit for proportionally mixing the output signal of the insertion processing circuit.

[0035]

In the present invention, the still image area and the moving image area are respectively subjected to the inter-frame inter-field interpolation processing and the field interpolating processing similar to the conventional ones, and the semi-still image area is defined separately from these. By performing inter-field interpolation processing on this area, it is possible to reproduce an image having a high vertical frequency.

[0036]

EXAMPLES The present invention will be described in detail below with reference to examples.

FIG. 1 shows MUSE in one embodiment of the present invention.
The main part of the decoder is shown. Here, the same parts as those in the conventional example (FIG. 9) are designated by the same reference numerals, and the description thereof will be appropriately omitted.

This apparatus is provided with an inter-field inter-field interpolation processing circuit (41) and includes an inter-frame inter-field interpolation processing circuit (11), a motion detection circuit (42), and a field interpolating processing circuit (41). 13) and the input terminal (14) are connected in parallel. Of these, the output sides of the inter-frame inter-field interpolation processing circuit (11) and the inter-field inter-field interpolation processing circuit (41) are connected to terminals (44) and (45) of the selector circuit (43), respectively. .

The selector circuit (43) has a first output signal (4) and a second output signal (4) output from the motion detection circuit (42).
6) allows interframe interfield interpolation processing circuit (1
1) or inter-field interpolation processing circuit (4
1) select one of the output signals and select the MIX circuit (1
Input is made to the input terminal (16) of 5).

Second output from the motion detection circuit (42)
Output signal 47 of the MIX circuit (15) input terminal (1
It is designed to be input to 7).

The connection relationship of the other parts is the same as that of the conventional example, and therefore the description thereof is omitted here.

The operation principle of the MUSE decoder having the above configuration will be described.

Compared with the conventional example, in the present invention, the dotted line part (49) and the first output signal (46) of the motion detection circuit (42) in FIG. 1 are added. Then, in the present invention, a quasi-still image area is newly provided in addition to the still image area and the moving image area, and the interfield field interpolation processing circuit (41) performs interfield field interpolation processing on such an area. I am supposed to do it.

This quasi-still picture area is a moving picture area in the two-frame difference detection described in the conventional example (FIG. 9) but a still picture area in the one-frame difference detection. This is the area where the corresponding interpolation processing was performed.

Next, a specific operation of the MUSE decoder shown in FIG. 1 will be described.

When the MUSE baseband signal converted into a digital signal is input to the input terminal (14) of FIG. 1, this is branched into four and the interframe interfield interpolation processing circuit (11) It is input to the inter-field interpolation processing circuit (41), the motion detection circuit (42), and the field interpolation processing circuit (13). Of these, interframe interfield interpolation processing circuit (11)
Performs inter-frame inter-field interpolation in which pixels are interpolated over four fields in a still image area to reproduce an image, and the resulting reproduced data is input to an input terminal (44) of a selector circuit (43).

On the other hand, the inter-field field interpolation processing circuit (41) performs inter-field field interpolation processing on the above-mentioned quasi-still image area, and the data reproduced as a result is input to the input terminal (45) of the selector circuit (43). ).

The field interpolation processing circuit (13) performs field interpolation for reproducing an image by interpolating pixels in only one field in the moving image area, and the resulting reproduced data is input to the input terminal 18 of the MIX circuit (15). To enter.

The motion detection circuit (12) also monitors the MUSE baseband signal input from the input terminal (14) and outputs the first output signal (46) for controlling the operation of the selector circuit (43). , And outputs a second output signal (47) for controlling the operation of the MIX circuit (15).

The MIX circuit (15) includes a selector circuit (4
Based on the second output signal 47 of the motion detection circuit (12), the still image path or the semi-still image path input from 3) and the moving image path input from the field interpolation processing circuit (13) are input. The pixels are proportionally mixed and output from the output terminal (19) to the circuit in the subsequent stage.

FIG. 2 shows the motion detection circuit (42) in FIG.
Is shown in detail. In this figure, the conventional example (Fig. 1
The same parts as those in (0) are designated by the same reference numerals and the description thereof will be appropriately omitted. This circuit is provided with a still image / semi-still image determination circuit (51), and first and second absolute value circuits (27), (28)
Therefore, the 1-frame difference detection signal and the 2-frame difference detection signal are input respectively. An output terminal (5) is provided on the output side of the still image / quasi still image determination circuit (51).
2) is provided.

Further, this circuit is provided with a non-linear constant generating circuit (31) similar to that of the conventional example (FIG. 10) so that only the two-frame detection signal from the second absolute value circuit (28) is inputted. It has become.

Other configurations are similar to those of the conventional example.

A motion detection circuit (42) having the above-mentioned configuration
The operation of will be described.

In this motion detection circuit (42), the still image / semi-still image determination circuit (51) is the first and second absolute value circuit (2).
Based on the 1-frame difference detection signal and the 2-frame difference detection signal respectively input from 7) and (28), a still image or a quasi-still image is determined for each pixel, and the determination result is 1
It outputs a binary signal of bits. This signal is given to the selector circuit (43) (FIG. 1) via the output terminal (52) as a selector switching signal.

The selector circuit (43) selects the inter-field field interpolation processing circuit (41) only when it is judged by the motion detection circuit (42) to be a quasi-still image area by the given selector switching signal. In other cases, the inter-frame inter-field interpolation processing circuit (11) is selected.

On the other hand, the nonlinear constant generating circuit (31) has a second
Based on only the two-frame detection signal from the absolute value circuit (28), a non-linear constant similar to the conventional example is generated, and the input terminal (17) of the MIX circuit (15) (FIG. 1) is output through the output terminal (32). ) Give to.

Since the operation from the input terminal (23) to the first and second absolute value circuits (27) and (28) is the same as that of the conventional example, the description is omitted here.

As a result, the image proportionally mixed by the MIX circuit (15) has a shape closer to a still image, and the resolution is increased.

FIG. 3 shows an interpolation processing process by the MUSE decoder of the present invention. As shown in this figure, two-dimensional low-frequency pass processing, that is, field interpolation processing is apparently performed on the data one field before (marked by □ in the figure) and the data of the current field (marked by ◯). Give. The reason why the image is "apparent" is that the image of the previous field and the image of the current field can be considered to be the same when it is determined that the image is a quasi-still image. That is, there is no problem even if the field interpolation is performed.

The difference between this interpolation processing and the processing of the moving image area is that the number of scanning lines, that is, the number of vertical samples is doubled.

FIGS. 4 to 7 show a transmittable area by various interpolation processes, that is, a luminance signal. In these figures, the vertical axis represents the number of vertical scanning lines and the horizontal axis represents the horizontal frequency. Also, each shaded area indicates a transmittable area.

Of these, FIG. 4 is a transmittable area of primitive sampling, FIG. 5 is a transmittable area by interframe interfield interpolation, FIG. 6 is a transmittable area by interfield interfield interpolation, and FIG. 7 is field interpolate. Indicates a transmittable area by. As is apparent from these figures, it is understood that the inter-field interpolating process can reproduce an image having a higher vertical frequency than the field interpolating process.

FIG. 8 shows an embodiment of the inter-field interpolation processing circuit (41) shown in FIG.

This circuit includes six 1-pixel delay circuits (61), which operate in synchronization with a 32.4 MHz clock.
(66) is provided. One of the 16.2 MHz MUSE baseband signals input from the input terminal (67) and branched into three is input to the first one-pixel delay circuit (61). The other branched signal is input to the 562 line delay circuit (68).

The output side of the first one-pixel delay circuit (61) is branched into two, one is input to the second one-pixel delay circuit (62), and the other is input to one of the first selector circuits (69). It is designed to be input to the input terminal.

The output side of the second one-pixel delay circuit (62) is connected to the first adding circuit (71). One of the signals branched from the input terminal (67) and branched into three is input to the adder circuit (71), which is created by the first and second one-pixel delay circuits (61) and (62). It is added to the data two pixels before. The result of this addition is input to the other input terminal of the first selector circuit (69) via the constant multiplication circuit (72).

The output side of the 562 line delay circuit (68) is branched into three branches, and the third one pixel delay circuit (6
3), the second adder circuit (73), and the 1-line delay circuit (74). The second adder circuit (73) is 5
The data before 562 lines output from the 62-line delay circuit (68) and the third and fourth 1-pixel delay circuits (6
3), 562 line plus 2 created by (64)
The data before the pixel is added and input to one input terminal of the second selector circuit (76) via the constant multiplication circuit (75). The data of 562 lines plus one pixel before is input from the third one-pixel delay circuit (63) to the other input terminal of the second selector circuit (76).

The output side of the 1-line delay circuit (74) is branched into two, which are input to the fifth 1-pixel delay circuit (65) and the third addition circuit (77), respectively. The third adder circuit (77) is created by the 563 line previous data output from the 1-line delay circuit (74) and the fifth and sixth 1-pixel delay circuits (65) and (66). The data of 563 lines plus the data two pixels before are added and input to one input terminal of the third selector circuit (79) via the constant multiplication circuit (78). This third selector circuit (79)
The data of 563 lines plus one pixel before is input from the fifth one-pixel delay circuit (65) to the other input terminal.

The first to third selector circuits (69), (7
6) and (79) are the first to third control signals (81) to
Due to (83), either one of the data input to the two input terminals is output. These control signals (81) to (83) are created based on a signal on which the MUSE signal is superimposed, such as the Y sub-sample phase and the C sub-sample phase, and a reset signal such as a frame, field and line. Thus, by switching the selector circuits (69), (76), (79), only the transmitted pixels are selected.

First and third selector circuits (69),
The output side of (79) is connected to a fourth adder circuit (84), and this adder circuit (84) further includes a constant multiplier circuit (8).
It is connected to the 5th addition circuit (86) via 5). In the fifth adder circuit (86), the data from the constant multiplication circuit (85) and the data from the second selector circuit (76) are added, and further, from the output terminal (88) via the constant multiplication circuit 87. Is output.

After all, the inter-field interpolation processing circuit (41) operates at a clock of 32.4 MHz and substitutes a zero value for a pixel that has not been transmitted, thereby equalizing the original filter. Will be performed.

As described above, in the present embodiment, the inter-field inter-field interpolation processing circuit (11) and the inter-field inter-field interpolation processing circuit (41) are appropriately switched by the selector circuit (43), which is similar to the conventional case. MIX circuit can be used.

That is, the selector circuit (43) operates the inter-field field only when the still image / quasi-still image determination circuit (51) (FIG. 2) of the motion detection circuit (12) determines that it is a quasi-still image area. Select the interpolation processing circuit (41),
In other cases, the interframe interfield interpolation processing circuit (11) is selected.

[0075]

As described above, according to the present invention,
Since an area called a quasi-still image area is set upon detection of a moving area, and inter-field inter-field interpolation processing is performed on this area, it is possible to obtain an image with high vertical resolution. Further, since the selector circuit switches between the interpolation processing in the still image area and the quasi still image area, the conventional MIX circuit can be used as it is.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of a MUSE decoder according to an embodiment of the present invention.

FIG. 2 is a block diagram showing in detail the motion detection circuit in FIG.

FIG. 3 is an explanatory diagram for explaining an interpolation processing process by the MUSE decoder of the present embodiment.

FIG. 4 is an explanatory diagram showing a transmittable area of primitive sampling.

FIG. 5 is an explanatory diagram showing a transmissible area by inter-frame inter-field interpolation.

FIG. 6 is an explanatory diagram showing a transmittable area by inter-field interpolation between fields.

FIG. 7 is an explanatory diagram showing a transmittable area by field interpolation.

8 is a block diagram showing an embodiment of an inter-field interpolation processing circuit between fields in FIG. 1. FIG.

FIG. 9 is a block diagram showing a main part of a conventional MUSE decoder.

FIG. 10 is a block diagram showing in detail a motion detection circuit in a conventional MUSE decoder.

FIG. 11 is a block diagram showing in detail a MIX circuit in a conventional MUSE decoder.

[Explanation of symbols]

 (11) Interframe Interfield Interpolation Processing Circuit (13) Field Interpolation Processing Circuit (15) MIX Circuit (21) First One Frame Delay Circuit (22) Second One Frame Delay Circuit (31) Nonlinear Constant Generation circuit (41) Inter-field interpolation processing circuit (42) Motion detection circuit (43) Selector circuit (51) Still image / quasi-still image determination circuit

[Procedure amendment]

[Submission date] October 18, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction content]

[Document name] Statement

Title of the invention MUSE decoder

[Claims]

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MUSE decoder installed in a MUSE type television receiver for decoding a MUSE signal.

[0002]

2. Description of the Related Art At present, the development of a high-definition television (high definition television) system using satellite broadcasting has already reached the stage of practical application.
The ub-nyquist Sampling Encoding) method is used.

In this MUSE system, the bandwidth is 22 MHz.
Frequency conversion is performed on the baseband signal including the luminance signal and the chrominance signal having a bandwidth of 7 MHz, and this is converted into a satellite broadcast bandwidth 27.
This baseband signal is band-compressed to about 8.1 MHz for transmission using one channel of MHz. This band compression is performed by thinning out a complete sampling point group extracted from the original video signal according to a predetermined rule.
At the time of thinning out the sampling points, the offset between fields is adjusted by utilizing the physiological characteristics of the viewer that the resolution in the diagonal direction on the screen is lower than in the vertical and horizontal directions.
Sampling is performed. It also utilizes the physiological characteristic of the viewer that the image quality does not deteriorate so much in the moving area even if the resolution is slightly reduced.

The decoder on the receiving side reproduces the sampling points decimated by the encoder on the transmitting side based on the sampling point groups before and after actually transmitted and received, so-called interpolation processing. Is supposed to do. This interpolation processing includes field interpolation performed using adjacent sampling point groups in the same field and inter-field interpolation performed using sampling point groups at corresponding positions in adjacent fields. In this interpolation processing, the moving image area and the still image area are detected from the reception screen,
Field interpolation is performed for the moving image area, and interfield interpolation is performed for the still image area. Of these, inter-frame interpolation processing may be used as a special type of inter-field interpolation.

The interpolation process will be described in detail below.

FIG. 9 shows a main part of a conventional MUSE decoder. This device is provided with an interframe interfield interpolation processing circuit (11), a motion detection circuit (12), and a field interpolation processing circuit (13), and MUSE converted from an input terminal (14) into a digital signal. A signal is input.

Of these, the inter-frame inter-field interpolation processing circuit (11) is adapted to perform so-called inter-frame inter-field interpolation for interpolating pixels over four fields in a still image area and reproducing an image. The side is connected to an input terminal (16) of a mixing circuit (hereinafter referred to as MIX circuit) (15).

The field interpolation processing circuit (13) is adapted to perform so-called field interpolation for reproducing an image by interpolating pixels in only one field in the moving image area, and its output side is a MIX circuit (15). ) Input terminal (1
8) is connected.

The output side of the motion detection circuit (12) is M
It is connected to the input terminal (17) of the IX circuit (15).

The output signal from the MIX circuit (15) is output from the output terminal (19) and input to the circuit in the subsequent stage.

In the conventional MUSE decoder having the above-mentioned structure, different processing is performed in the still picture area and the moving picture area. Therefore, the motion detection circuit (12) discriminates between the still image area and the moving image area.

FIG. 10 shows a motion detection circuit (1
2) is a detailed representation. This circuit is provided with 1-frame delay circuits (21) and (22) that delay each pixel by 1 frame. Of these, the first
The 1-frame delay circuit (21) includes an input terminal (23)
One of the three MUSE signals that are input from the MUX signal is input. The other two signals divided into three are respectively fed to the first and second subtractors (24) and (2
Input to 5).

The output side of the first one-frame delay circuit (21) is branched into two and connected to the second one-frame delay circuit (22) and the first subtractor (24), respectively.

The output side of the second one-frame delay circuit (22) is connected to the second subtractor (25).

The first subtractor (24) is connected to one of the inputs of the maximum value selection circuit (28) via the low pass filter (26) (LPF) and the first absolute value circuit (27),
The second subtractor (25) is connected to the other input of the maximum value selection circuit (28) via the second absolute value circuit (29).

The output side of the maximum value selection circuit (28) is connected to a non-linear constant generation circuit (31) having an output terminal (32).

The motion detection circuit (12) having the above-mentioned configuration
The operation of will be described.

The motion detection circuit (12) detects a region in which motion is intense, that is, a high frequency component at a time frequency, by a so-called interframe coding method, and determines a still image or a moving image for each pixel.

In FIG. 10, the difference between the signal input from the input terminal (23) and the signal delayed by one frame by the first one-frame delay circuit (21) is calculated by the first subtractor (24). Desired. This difference signal has its high frequency band cut by a low-pass filter (26) of 4.05 MHz,
After the absolute value is taken by the absolute value circuit (27), it is input to the maximum value selection circuit (28) as the first motion detection signal (34).

On the other hand, the signal input from the input terminal (23) and the signal further delayed by one frame by the second one-frame delay circuit (22) are the second subtractor (25).
Then, the difference is obtained. This difference signal has its absolute value taken by the second absolute value circuit (29) and is input to the maximum value selection circuit (28) as the second motion detection signal (35).

Here, the reason why one frame difference is also taken into consideration is as follows. Generally MUSE
In the case of the method, motion detection based on a 2-frame difference is mainly used, but aliasing distortion due to interframe / interline offset subsampling does not exist in the horizontal frequency band of 0 to 4.05 MHz of the MUSE signal. Therefore, this 0
Even in the 4.05 MHz region, it is possible to detect the motion by the difference of one frame.

The maximum value selection circuit (28) selects the larger one of these two types of motion detection signals (34) and (35) and inputs it to the non-linear constant generation circuit (31).

The non-linear constant generating circuit (31) outputs from the output terminal (32) a motion detection signal having a finite number, that is, a 2n level value represented by n bits (n is a natural number). For example, when it is determined that the result of the 2-frame difference detection is the moving image area and the result of the 1-frame difference detection is the still image area, or the result of the 2-frame difference detection is the still image area and the result of the 1-frame difference detection is the moving image area. If determined, this circuit determines that it is a moving image area.

The motion detection signal output from the output terminal (32) is input to the input terminal (17) of the MIX circuit (15).

FIG. 11 shows the MIX circuit (15) in detail. With this circuit, three input terminals 16-1
Output signals of the interframe interfield interpolation processing circuit (11), the motion detection circuit (12), and the field interpolation processing circuit (13) of FIG. 9 are input from 8 respectively.

Of these, the data input from the inter-frame inter-field interpolation processing circuit (11) via the input terminal (16) and the input signal from the motion detection circuit (12) (1
The data input via 7) and the polarity of which is inverted by the inverter circuit (37) are multiplied by the first multiplier (36) and input to the adder (39).

On the other hand, the field interpolation processing circuit (13)
From the input terminal (18) and the data input from the motion detection circuit (12) via the input terminal (17) are multiplied by the second multiplier (38) and added. (39) is input. Further, the adder (39) adds these and outputs from the output terminal (19).

That is, in this MIX circuit (15), the still picture path input from the inter-frame inter-field interpolation processing circuit (11) and the moving picture path input from the field interpolation processing circuit (13). The pixels are proportionally mixed for each pixel by the motion detection signal output from the motion detection circuit (12).

Assuming that the signal of the moving picture path is A, the signal of the still picture path is B, and the motion detection signal is K, the output signal M of the MIX circuit (15) is as follows. However, K
Is a positive number less than or equal to 1.

M = K · A + (1−K) · B In Japanese Patent Laid-Open No. 2-100484, a still image processing system and a moving image processing system having a moving image enhancing function are provided, and their outputs are converted into motion signals. A configuration is disclosed in which a still image enhancer is provided in which the amount of enhancement can be varied by a motion signal after proportional mixing.

[0031]

Since the conventional MUSE decoder has the structure as described above,
There is a problem in that a still image area that cannot be detected by the frame difference detection is processed for the moving image area.

Therefore, there is a problem that the above problems must be solved.

The present invention has been made in order to solve the above problems, and provides a MUSE decoder capable of expanding the vertical bandwidth for a still image area that cannot be detected by the two-frame differential motion detection circuit. With the goal.

[0034]

The MUSE decoder according to the present invention (i) determines whether the input MUSE baseband signal is a still picture area, a moving picture area, or a quasi still picture area, A motion detection circuit that outputs first and second determination result output signals; (ii) an inter-frame inter-field interpolation processing circuit that performs inter-frame inter-field interpolation processing for an image belonging to a still image area; and (iii) An inter-field field interpolation processing circuit for performing inter-field field interpolation processing for images belonging to the quasi-still image area, and (iv) a field interpolation processing circuit for performing field interpolation processing for images belonging to the moving image area. , (V) The output signal of the inter-frame inter-field interpolation processing circuit and the inter-field inter-field interpolation based on the first determination result output signal output from the motion detection circuit. Within the field and the output signal selected by the selection circuit based on the selection circuit that selects the corresponding one of the output signals of the processing circuit and (vi) the second determination result output signal output from the motion detection circuit. And a mixing circuit for proportionally mixing the output signal of the insertion processing circuit.

[0035]

In the present invention, the still image area and the moving image area are respectively subjected to the inter-frame inter-field interpolation processing and the field interpolating processing similar to the conventional ones, and the semi-still image area is defined separately from these. By performing inter-field interpolation processing on this area, it is possible to reproduce an image having a high vertical frequency.

[0036]

EXAMPLES The present invention will be described in detail below with reference to examples.

FIG. 1 shows MUSE in one embodiment of the present invention.
The main part of the decoder is shown. Here, the same parts as those in the conventional example (FIG. 9) are designated by the same reference numerals, and the description thereof will be appropriately omitted.

This apparatus is provided with an inter-field inter-field interpolation processing circuit (41) and includes an inter-frame inter-field interpolation processing circuit (11), a motion detection circuit (42), and a field interpolating processing circuit (41). 13) and the input terminal (14) are connected in parallel. Of these, the output sides of the inter-frame field interpolation processing circuit (11) and the inter-field field interpolation processing circuit (41) are connected to the terminals (44) and (45) of the selector circuit (43), respectively. .

The selector circuit (43) has a first output signal (4) and a second output signal (4) output from the motion detection circuit (42).
6) allows interframe interfield interpolation processing circuit (1
1) or inter-field interpolation processing circuit (4
1) select one of the output signals and select the MIX circuit (1
Input is made to the input terminal (16) of 5).

Second output from the motion detection circuit (42)
Output signal 47 of the MIX circuit (15) input terminal (1
It is designed to be input to 7).

The connection relationship of the other parts is the same as that of the conventional example, and therefore the description thereof is omitted here.

The operation principle of the MUSE decoder having the above configuration will be described.

Compared with the conventional example, in the present invention, the dotted line portion (49) and the first output signal (46) of the motion detection circuit (42) in FIG. 1 are added. In the present invention, a quasi-still image region is newly provided in addition to the still image region and the moving image region, and such a region is subjected to interfield field interpolation processing by the interfield field interpolation processing circuit (41). I am supposed to do it.

This quasi-still image area is a moving image area in the 2-frame difference detection described in the conventional example (FIG. 9), but is a still image area in the 1-frame difference detection. This is the area where the corresponding interpolation processing was performed.

Next, a specific operation of the MUSE decoder shown in FIG. 1 will be described.

When the MUSE baseband signal converted into a digital signal is input to the input terminal (14) of FIG. 1, this is branched into four and the interframe interfield interpolation processing circuit (11) It is input to the inter-field interpolation processing circuit (41), the motion detection circuit (42), and the field interpolation processing circuit (13). Of these, interframe interfield interpolation processing circuit (11)
Performs inter-frame inter-field interpolation in which pixels are interpolated over four fields in a still image area to reproduce an image, and the resulting reproduced data is input to an input terminal (44) of a selector circuit (43).

On the other hand, the inter-field field interpolation processing circuit (41) performs inter-field field interpolation processing on the above-mentioned quasi-still image area, and the data reproduced as a result is input to the input terminal (45) of the selector circuit (43). ).

The field interpolation processing circuit (13) performs field interpolation for reproducing an image by interpolating pixels in only one field in the moving image area, and the resulting reproduced data is input to the input terminal 18 of the MIX circuit (15). To enter.

The motion detection circuit (12) also monitors the MUSE baseband signal input from the input terminal (14) and outputs the first output signal (46) for controlling the operation of the selector circuit (43). , And outputs a second output signal (47) for controlling the operation of the MIX circuit (15).

The MIX circuit (15) includes a selector circuit (4
Based on the second output signal 47 of the motion detection circuit (12), the still image path or the semi-still image path input from 3) and the moving image path input from the field interpolation processing circuit (13) are input. The pixels are proportionally mixed and output from the output terminal (19) to the circuit in the subsequent stage.

FIG. 2 shows the motion detection circuit (42) in FIG.
Is shown in detail. In this figure, the conventional example (Fig. 1
The same parts as those in (0) are designated by the same reference numerals and the description thereof will be appropriately omitted. This circuit is provided with a still image / semi-still image determination circuit (51), and first and second absolute value circuits (27), (28)
Therefore, the 1-frame difference detection signal and the 2-frame difference detection signal are input respectively. An output terminal (5) is provided on the output side of the still image / quasi still image determination circuit (51).
2) is provided.

Further, this circuit is provided with a non-linear constant generating circuit (31) similar to that of the conventional example (FIG. 10) so that only the two-frame detection signal from the second absolute value circuit (28) is inputted. It has become.

Other configurations are similar to those of the conventional example.

A motion detection circuit (42) having the above-mentioned configuration
The operation of will be described.

In this motion detection circuit (42), the still image / semi-still image determination circuit (51) is the first and second absolute value circuit (2).
Based on the 1-frame difference detection signal and the 2-frame difference detection signal respectively input from 7) and (28), a still image or a quasi-still image is determined for each pixel, and the determination result is 1
It outputs a binary signal of bits. This signal is given to the selector circuit (43) (FIG. 1) via the output terminal (52) as a selector switching signal.

The selector circuit (43) selects the inter-field field interpolation processing circuit (41) only when it is judged by the motion detection circuit (42) to be a quasi-still image area by the given selector switching signal. In other cases, the inter-frame inter-field interpolation processing circuit (11) is selected.

On the other hand, the nonlinear constant generating circuit (31) has a second
Based on only the two-frame detection signal from the absolute value circuit (28), a non-linear constant similar to the conventional example is generated, and the input terminal (17) of the MIX circuit (15) (FIG. 1) is output through the output terminal (32). ) Give to.

Since the operation from the input terminal (23) to the first and second absolute value circuits (27) and (28) is the same as that of the conventional example, the description is omitted here.

As a result, the image proportionally mixed by the MIX circuit (15) has a shape closer to a still image, and the resolution is increased.

FIG. 3 shows an interpolation processing process by the MUSE decoder of the present invention. As shown in this figure, two-dimensional low-frequency pass processing, that is, field interpolation processing is apparently performed on the data one field before (marked by □ in the figure) and the data of the current field (marked by ◯). Give. The reason why the image is "apparent" is that the image of the previous field and the image of the current field can be considered to be the same when it is determined that the image is a quasi-still image. That is, there is no problem even if the field interpolation is performed.

The difference between this interpolation processing and the processing of the moving image area is that the number of scanning lines, that is, the number of vertical samples is doubled.

FIGS. 4 to 7 show a transmittable area by various interpolation processes, that is, a luminance signal. In these figures, the vertical axis represents the number of vertical scanning lines and the horizontal axis represents the horizontal frequency. Also, each shaded area indicates a transmittable area.

Of these, FIG. 4 is a transmittable area of primitive sampling, FIG. 5 is a transmittable area by interframe interfield interpolation, FIG. 6 is a transmittable area by interfield interfield interpolation, and FIG. 7 is field interpolate. Indicates a transmittable area by. As is apparent from these figures, it is understood that the inter-field interpolating process can reproduce an image having a higher vertical frequency than the field interpolating process.

FIG. 8 shows an embodiment of the inter-field interpolation processing circuit (41) shown in FIG.

This circuit includes six 1-pixel delay circuits (61), which operate in synchronization with a 32.4 MHz clock.
(66) is provided. One of the 16.2 MHz MUSE baseband signals input from the input terminal (67) and branched into three is input to the first one-pixel delay circuit (61). The other branched signal is input to the 562 line delay circuit (68).

The output side of the first one-pixel delay circuit (61) is branched into two, one is input to the second one-pixel delay circuit (62), and the other is input to one of the first selector circuits (69). It is designed to be input to the input terminal.

The output side of the second one-pixel delay circuit (62) is connected to the first adding circuit (71). One of the signals branched from the input terminal (67) and branched into three is input to the adder circuit (71), which is created by the first and second one-pixel delay circuits (61) and (62). It is added to the data two pixels before. The result of this addition is input to the other input terminal of the first selector circuit (69) via the constant multiplication circuit (72).

The output side of the 562 line delay circuit (68) is branched into three branches, and the third one pixel delay circuit (6
3), the second adder circuit (73), and the 1-line delay circuit (74). The second adder circuit (73) is 5
The data before 562 lines output from the 62-line delay circuit (68) and the third and fourth 1-pixel delay circuits (6
3), 562 line plus 2 created by (64)
The data before the pixel is added and input to one input terminal of the second selector circuit (76) via the constant multiplication circuit (75). The data of 562 lines plus one pixel before is input from the third one-pixel delay circuit (63) to the other input terminal of the second selector circuit (76).

The output side of the 1-line delay circuit (74) is branched into two, which are input to the fifth 1-pixel delay circuit (65) and the third addition circuit (77), respectively. The third adder circuit (77) is created by the 563 line previous data output from the 1-line delay circuit (74) and the fifth and sixth 1-pixel delay circuits (65) and (66). The data of 563 lines plus the data two pixels before are added and input to one input terminal of the third selector circuit (79) via the constant multiplication circuit (78). This third selector circuit (79)
The data of 563 lines plus one pixel before is input from the fifth one-pixel delay circuit (65) to the other input terminal.

The first to third selector circuits (69), (7
6) and (79) are the first to third control signals (81) to
Due to (83), either one of the data input to the two input terminals is output. These control signals (81) to (83) are created based on a signal on which the MUSE signal is superimposed, such as the Y sub-sample phase and the C sub-sample phase, and a reset signal such as a frame, field and line. Thus, by switching the selector circuits (69), (76), (79), only the transmitted pixels are selected.

First and third selector circuits (69),
The output side of (79) is connected to a fourth adder circuit (84), and this adder circuit (84) further includes a constant multiplier circuit (8).
It is connected to the 5th addition circuit (86) via 5). In the fifth adder circuit (86), the data from the constant multiplication circuit (85) and the data from the second selector circuit (76) are added, and further, from the output terminal (88) via the constant multiplication circuit 87. Is output.

After all, the inter-field interpolation processing circuit (41) operates at a clock of 32.4 MHz and substitutes a zero value for a pixel that has not been transmitted, thereby equalizing the original filter. Will be performed.

As described above, in the present embodiment, the inter-field inter-field interpolation processing circuit (11) and the inter-field inter-field interpolation processing circuit (41) are appropriately switched by the selector circuit (43), which is similar to the conventional case. MIX circuit can be used.

That is, the selector circuit (43) operates the inter-field field only when the still image / quasi-still image determination circuit (51) (FIG. 2) of the motion detection circuit (12) determines that it is a quasi-still image area. Select the interpolation processing circuit (41),
In other cases, the interframe interfield interpolation processing circuit (11) is selected.

[0075]

As described above, according to the present invention,
Since an area called a quasi-still image area is set upon detection of a moving area, and inter-field inter-field interpolation processing is performed on this area, it is possible to obtain an image with high vertical resolution. Further, since the selector circuit switches between the interpolation processing in the still image area and the quasi still image area, the conventional MIX circuit can be used as it is.

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Claims (1)

[Claims] 1. A MUSE baseband signal converted into a digital signal is determined to be a still image region, a moving image region, or a quasi still image region, and first and second determination result output signals are output. Motion detection circuit, inter-frame inter-field interpolation processing circuit that performs inter-frame inter-field interpolation processing for images that belong to the still image area, and field that inter-field inter-field interpolation processing applies to images that belong to the quasi-still image area An inter-field interpolating processing circuit, a field interpolating processing circuit for performing field interpolating processing on an image belonging to a moving image area, and an inter-frame interpolating processing based on a first determination result output signal output from the motion detecting circuit. Of the output signals of the inter-field interpolation processing circuit and the output signals of the inter-field interpolation processing circuit, A mixing circuit for proportionally mixing the output signal selected by the selection circuit and the output signal of the field interpolation processing circuit based on the selection circuit for selection and the second determination result output signal output from the motion detection circuit. A MUSE decoder including a circuit, and performing interfield interfield interpolation processing on an image area determined to be a quasi still image area by a motion detection circuit.