JPH06105204A - Speed converter for high speed tv camera output signal - Google Patents

Abstract

PURPOSE:To output the output signal of a high speed TV camera from plural output terminal as parallel output. CONSTITUTION:A high speed TV camera 10 picks up an image at a rate of 120 frames per second. An A/D converter 1 samples the output of the TV camera 10 at a high speed clock being four times of a usual TV rate (30 frames/ sec). Four frame memories 2a-2d fetch the output of the A/D converter 1 by using a clock signal whose frequency is 1/4 of the high speed clock. The output from each frame memory becomes the video signal of a usual TV rate in a D/A converter in four D/A converters 3a-3d corresponding to the A/D converter. Thus, an optional process in one high speed operation process of an object for monitor or the like is subjected to display processing or the like in any of the four processing units by giving each output of the four D/A converters to a relevant processing unit in the four processing units 11 operated at the usual TV rate, then an optional process in one operation process is immediately monitored.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a speed converter for a high speed TV camera output signal, and more particularly to a speed converter having a plurality of output terminals.

[0002]

2. Description of the Related Art For example, a processing device which can measure a dimension of a target object such as a positioning mark for mounting an IC on a substrate, a marking character inspection of a product, and a character recognition has been widely used in factories and the like. However, a TV camera used as an input means of a processing device of this type can usually take an image at a rate of 30 frames per second (frame), and even if it has a shutter for the purpose of acquiring a still image of a moving object, Even if the normal shutter speed is 1/1000 second, for example, there are 30 "frame images" per second.

However, for example, in the monitoring and management of the manufacturing process of semiconductor parts, it may be necessary to examine in detail each process from the start to the end of one bonding process. In the case of a moving object that operates at high speed, sufficient motion analysis cannot be performed at a normal TV rate of 30 frames / sec.

Therefore, in recent years, for example, a high-speed TV camera with a shutter capable of picking up images at a rate of 120 frames per second has been developed and is used together with a dedicated processing device. This is because all the captured images are temporarily stored in the memory in the dedicated processing device, and the continuous image at the TV rate (30 frames / second) or the still image from this dedicated processing device, or even the slow motion image is displayed. It can be read as.

[0005]

The above-mentioned high-speed TV camera enables the motion analysis of a moving object that operates at high speed, but it is necessary to make a good / bad judgment instantly in the production line. The method of temporarily storing in the processing device and performing image analysis as post-processing has a problem of lack of responsiveness. Further, in the above-mentioned dedicated processing device, the output is 1
Since it is a channel, it is difficult to confirm any process of a series of operation processes immediately, that is, it cannot be used by incorporating it into a production line.

An object of the present invention is to provide a speed conversion device for a high speed TV camera output signal, which makes it possible to immediately make an appropriate judgment on an object that operates at high speed in surveillance using a high speed TV camera. To provide.

[0007]

To achieve the above object, a high speed TV camera output signal speed conversion apparatus of the present invention has the following configuration. That is, the high speed TV camera output signal speed conversion apparatus according to the present invention has a normal TV rate of N.
An A / D converter that samples an output signal of a double high-speed TV camera with a high-speed clock that is N times as high as a normal TV image processing; and N frame memories that receive the output of the A / D converter in parallel And N frame memories for converting the output of the A / D converter into a signal at a speed of 1 / N of the high-speed clock and outputting the signals, respectively; And N D / A converters for analogizing the output.

[0008]

Next, the high speed T of the present invention constructed as described above.
The operation of the speed conversion device for the V camera output signal will be described. In the present invention, an output signal of a high-speed TV camera N times as high as a normal TV rate is sampled at a high-speed clock N times as high as a normal TV image processing, and the sampled signal is stored in each of N frame memories. It is stored at a speed of 1 / N, and it is converted to analog and output. That is, the output signal of the high-speed TV camera is output from the N output terminals at the normal TV rate.

As a result, if a conventional processor operating at 30 frames / second is connected to each of the N output terminals, N arbitrary number of arbitrary operation steps of the object such as high-speed operation of monitoring can be achieved. Since the processing is displayed on any of the processing devices, it is possible to immediately monitor an arbitrary process of one operation process and the like, and it is possible to perform high-speed measurement processing incorporated in the production line.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a speed converter for a high speed TV camera output signal according to an embodiment of the present invention. This speed conversion device includes an A / D converter 1 and four frame memories 2 (a,
b, c, d) and four D / A converters 3 (a, b, c,
d) is basically provided, and the output signal of the high-speed TV camera 10 is distributed and output from the four output terminals (3a to 3d). Each of the four output terminals has the above-mentioned character recognition and the like. The processing device 11 of is connected.

As described above, the high-speed TV camera 10 is a TV camera capable of picking up an image at a rate of 120 frames per second, for example, and the video signal as the picked-up image signal is given to the A / D converter 1. The A / D converter 1 outputs the output signal of the high-speed TV camera 10 at a normal TV rate (30 frames / frame).
Sampled with a high-speed clock (clock cycle 25 ns) that is 4 times (N = 4) the clock used in 4 seconds.
The write system of each frame memory is configured as shown in FIG. 2, for example.

In FIG. 2, in the write system of each frame memory, a flip-flop (F / F) 21 is provided at the input stage, and four F / Fs (22a-22d) are arranged in parallel at the output stage. .

The F / F 21 takes in the output of the A / D converter 1 with a high-speed clock (FIG. 3 (a)) similar to that of the A / D converter 1, controls the timing, and outputs it.

The four F / Fs (22a to 22d) have write clocks (WCK1 to WCK1 to WCK1) having a clock cycle of 100 ns.
WCK4) is given in a relationship in which the high speed clock is shifted by one clock (FIGS. 3 (b) (c) (d) (e)).

Therefore, although the memories (23a-23d) are, for example, dynamic RAMs (DRAMs), each DR
In the AM, the output of the F / F 21 is thinned out to 1/4, and the DRAM 23a → DRAM 23b → DRAM 23c
→ The data is stored in the order of the DRAM 23d.

Next, the reading system of each frame memory is constructed, for example, as shown in FIG. In FIG. 4, each DR
The AM read clock (RCK1 to RCK4) has a cycle of 4
Although it is 00 ns, the DRAM 23a →
It operates in the order of DRAM 23b → DRAM 23c → DRAM 23d.

The switches (24a to 24d) are switched by the select signal at intervals of 100ns, 24a → 24b → 24c → 2.
Opening and closing operations are performed in the order of 4d to selectively output the read output of the corresponding DRAM. The output of each switch is given to the F / F 25.

The F / F 25 is set to 10 by the latch clock.
The output of each switch is taken in every 0ns, and the output terminal D
Output to the / A converter 3.

As a result, the D / A converter 3 outputs a video signal of a normal TV rate (30 frames / second).

Therefore, as shown in FIG. 1, each of the four output terminals has a processor 1 which operates at a normal TV rate.
If 1 is connected, an arbitrary process of one operation process of the object such as high-speed monitoring is processed and displayed on any of the four processing devices 11, so that the arbitrary process of one operation process is immediately monitored. It becomes possible to perform high-speed measurement processing etc. by incorporating it in the production line.

A DRAM is used as the memory (23a to 23d) in terms of price, but a static RAM is used.
Of course, (SRAM) may be used. Further, the number of output terminals may be determined according to the operation speed of an object to be monitored or the like.

[0022]

As described above, the high speed T of the present invention
According to the speed conversion device for the V camera output signal, the high speed TV
The output signal of the camera is sampled at a high-speed clock N times the normal TV rate, stored in each of N frame memories at a speed of 1 / N of the high-speed clock, and the analog signal is output. Since the output signal of the high-speed TV camera is output from the N output terminals at the normal TV rate, if a processing device that operates at the conventional 30 frames / second is connected to each of the N output terminals, , An arbitrary process of one operation process of an object such as monitoring that operates at high speed is N
Since the processing is displayed on any of the individual processing devices, it is possible to immediately monitor an arbitrary process of one operation process and the like, and it is possible to perform high-speed measurement processing incorporated in the production line.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a speed conversion device for a high speed TV camera output signal according to an embodiment of the present invention.

FIG. 2 is a configuration block diagram of a writing system of each frame memory.

FIG. 3 is a time chart of a write operation.

FIG. 4 is a configuration block diagram of a read system of each frame memory.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 A / D converter 2a-2d Frame memory 3,3a-3d D / A converter 10 High-speed TV camera 11 Processing device 21 Flip-flop (F / F) 22a-22d Flip-flop (F / F) 23a-23d Memory (DRAM) 24a to 24d Switch 25 Flip-flop (F / F)

Claims (1)

[Claims] 1. An A / D converter for sampling an output signal of a high-speed TV camera N times the normal TV rate at a high-speed clock N times the normal TV image processing; N frame memories for receiving outputs in parallel, each of which converts the output of the A / D converter into a signal at a speed of 1 / N of the high-speed clock and outputs the signal. A speed conversion device for high-speed TV camera output signals, comprising: N D / A converters for analogizing outputs of corresponding memories of the N frame memories.