JPH06104957A - Digital signal receiver - Google Patents

Abstract

PURPOSE:To implement demodulation processing and start-stop synchronization reception processing with the same configuration by fetching a timer value corresponding to a rising and a falling edge intervals of a modulation signal with a trigger signal based on a start bit and discriminating bit data from the timer value. CONSTITUTION:A rising or a falling of a received FSK modulation input is detected by an edge detection circuit 1, which outputs a trigger signal and a timer means 2 measures the interval of trigger signals and outputs a relevant timer value TM. A start bit detection means 3 detects a start bit based on the value TM and a trigger signal generating means 4 generated the trigger signal, A frame reception buffer means 4 fetches the signal TM based on the trigger signal to discriminate a level 0/1 of the bit data from the timer value changing after the reception of the trigger signal. Thus, the demodulation processing and start-stop synchronization reception processing are implemented by the same configuration and the operation stability and reliability are enhanced with simple circuit configuration.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention receives a digital signal transmitted including a pulse signal and outputs it as a "0",
The present invention relates to a digital signal receiving apparatus that demodulates to bit data of "1", and more specifically to a digital signal receiving apparatus having a function of detecting a start bit by counting an edge interval (pulse width) of a pulse signal.

[0002]

2. Description of the Related Art Process signals such as temperature and pressure are converted into standardized signals of 4 to 20 mA, for example, and are sent from a transmitter side to a receiving end side via a signal transmission path. There is. Such signal transmission is sent as an analog signal via, for example, a two-wire type transmission line, but communication means such as a handheld terminal is connected to the transmitter side or the receiving side or to the transmission signal line. Then, various digital communications can be performed from there to the transmitter and the receiving end.

FIG. 11 is a block diagram showing an example of a digital signal receiving apparatus conventionally used in this type of system. This signal receiving device inputs a demodulation circuit DM that demodulates 1-bit data (B-DATA) from the received signal, the demodulated 1-bit data and a trigger signal, and starts synchronization in synchronization with the trigger signal. It is composed of an asynchronous reception circuit (UART circuit) UR for performing synchronous reception, and a microprocessor MP for inputting an interrupt signal INT and data DATA obtained from the asynchronous reception circuit UR and performing necessary data processing.

FIG. 12 is a waveform diagram showing the operation of the start / stop synchronization receiving circuit UR. (A) shows a trigger signal Trg generated from the start bit of the received signal, and (b).
Is 1-bit data (B-
DATA) is shown. The start-stop synchronization receiving circuit UR is
Asynchronous reception of 1-bit data (B-DATA) is performed in synchronization with the trigger signal Trg shown in FIG.
The data (DATA) of "1" is demodulated.

[0005]

In the conventional receiver configured as described above, the demodulation circuit D is used for demodulating the modulated input signal.
M performs the start-stop synchronization reception by the start-stop synchronization receiving circuit (UAR).
(T circuit) Its function is separated into two, as is done by the UR. Therefore, there is a problem that the circuit configuration is complicated and the cost is high.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a digital signal receiving apparatus having a simple structure and capable of reliably demodulating data.

[0007]

SUMMARY OF THE INVENTION The present invention which achieves such an object is to receive a digital signal transmitted including a pulse signal and demodulate it into "0" and "1" data. A digital signal receiving apparatus, which is an edge detection circuit for detecting a rising / falling edge of a pulse signal included in the received signal and outputting a trigger signal,
Timer means for measuring the interval of the trigger signal output from the edge detection circuit, start bit detecting means for detecting a start bit based on the timer value measured by the timer means, and start detected by the start bit detecting means Trigger signal generating means for outputting a trigger signal based on a bit, and the timer value measured by the timer means are inputted, and the trigger signal from the trigger signal generating means is inputted and changed after receiving the trigger signal. Digital signal reception, characterized in that it is provided with frame receiving buffer means for judging "0" or "1" of bit data from a timer value, storing one frame, and outputting predetermined bit data together with an interrupt signal. It is a device.

[0008]

The function of the edge detection circuit is to detect edges at the rising edge and the falling edge of the pulse signal included in the received signal,
The detection means restarts the timer means.

As a result, the edge interval (pulse width) is obtained as the timer value by the timer means. The frame reception buffer means obtains a timer value corresponding to the center of the bits by matching the phases with the trigger signal, and determines "0" or "1".

As a result, the demodulation processing of the received signal and the start-stop synchronization processing can be performed with the same configuration.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a configuration block diagram showing an embodiment of the present invention. In the figure, IN is an input terminal to which a digital signal transmitted including a pulse signal is applied, and 1 is an edge for detecting a rising edge and a falling edge of a pulse signal included in a reception signal applied to this input terminal. The detection circuit is composed of, for example, a differentiation circuit, and outputs the trigger signal Trg1 at the timing of the edge of the pulse.

Reference numeral 2 is a timer means for measuring the interval of the trigger signal Trg1 output from the edge detection circuit 1. The trigger signal Trg1 is input to the clear terminal CLR and the clock is counted during the edge interval (pulse width). Timer value (T
M) is output. 3 inputs the timer value (TM) measured by the timer means 2, and from the value (pulse width),
It is a start bit detecting means for detecting a change from "1" to "0", that is, a start bit. When the start bit detecting means 3 detects the start bit, it outputs the enable signal ENA and also outputs the offset data (OFFset) for adjusting the phase so as to trigger the bit center value.

Reference numeral 4 denotes a trigger signal generating means, which inputs the enable signal ENA from the start bit detecting means 3 and offset data (OFFset) and receives the timing corresponding to the bit center position, that is, the enable signal ENA. To offset data (OFFs
et), the trigger signal Trg2 is output at the time. From then on, the trigger signal Trg2 is repeatedly output at 1-bit length intervals.

Numeral 5 is a frame receiving buffer means which inputs the timer value TM measured by the timer means 2 and the trigger signal Trg2 from the trigger signal generating means 4 and changes after receiving the trigger signal Trg2. Bits “0” and “1” are determined from the timer value TM, one frame (1 start, 8 bits, 1 stop) is stored, and when a stop bit is detected, a predetermined bit (eg, 8 bits) data DATA is interrupted. Output together with the signal INT.

Reference numeral 6 denotes a processor circuit (microprocessor), which is an interrupt signal I from the frame receiving buffer 5.
NT is applied to the interrupt terminal and this interrupt signal IN
In synchronization with T, one frame of data DATA output from the frame receiving buffer means 5 is input.

The operation of the thus constructed apparatus will be described below. FIG. 2 is a waveform diagram showing an example of a signal applied to the input terminal IN, and FIG. 3 is a waveform diagram mainly showing a part of FIG. Here, it is assumed that the HART protocol developed by Rosemount Inc. in the United States is adopted.

In these figures, (a) is a bit data string corresponding to the modulation input, and (b) shows the modulation input signal applied to the input terminal IN. The main specifications in the above-mentioned HART protocol are as follows.

Communication method: serial half-duplex, start-stop synchronization, 1 start 8 bits odd parity, 1 stop bit Transmission rate: 1200 baud modulation; FSK 1: 1200 Hz ± 1% 0: 220
The relationship between the 0 Hz ± 1% FSK-modulated modulation signal and the corresponding bit string data is as shown in FIG. 2, and is “1”.
The pulse widths L and S of the FSK modulated signal for the bit data of are as follows.

L = 1 / (1200 × 2) = 416.7 μs S = 1 / (2200 × 2) = 227.3 μs bt (1 bit length) = 833.3 μs X; S ≦ X ≦ L Here, X is the pulse width of the pulse existing at the time of switching from the bit data “1” to “0”.

In FIG. 3, OFFset from the bit center of the bit data “0” to the pulse width signal indicating switching from the bit data “1” to “0” is expressed by the equation (1).

OFFset = L-{(L−X) / (L−S)} · S (1) In demodulation of the modulation input signal, first, the start bit is detected by detecting the pulse width X. After that, OFFset is obtained, and thereafter, it is possible to match the phase with the center position of the bit. Then, the pulse width of the modulated input signal at the median bit value is S
When, the corresponding bit data string is "0", when L,
The corresponding bit data string is "1".

FIG. 4 is an operation waveform diagram showing an example of the operation. The FSK modulation signal having the above-mentioned specifications is applied to the input terminal IN as shown in (a). The edge detection circuit 1 detects edges at the rising edge and the falling edge of the FSK modulated signal, and applies a trigger signal Trg1 as shown in (b) to the timer means 2.

The timer means 2 constantly counts clocks, and the count value is cleared by the trigger signal Trg1 from the edge detection circuit 1 as shown in (c). Therefore, as shown in (d), the timer means 2 outputs the timer value TM corresponding to the edge interval. here,
At the time when the bit data changes from “1” to “0”, the timer value corresponding to the pulse width X is output.

The start bit detecting means 3 receives such a timer value TM output from the timer means 2, and (e)
As shown in (1), the enable signal ENA is output, and OFFset is calculated and output using the above-described equation (1). The trigger signal generating means 4 receives the enable signal ENA and the OFFset value output from the start bit detecting means 3, and after receiving the enable signal ENA, starts the internal timer as shown in (f), and the counter value becomes When the OFFset value is reached, (g)
The trigger signal Trg2 is output as shown in FIG. After that, the trigger signal Trg2 is incremented for each 1-bit length (bt).
Is output.

The frame reception buffer means 5 has the timer value TM output from the timer means 2 immediately after the trigger signal Trg2 from the trigger signal generating means 4 is applied.
As shown in (h), and if the value is S,
Bit data “0” is held, and if L, bit data “1” is held.

FIG. 5 is an operation waveform diagram showing an operation near the stop bit. The frame receiving buffer means 5 is
Frame data (1 start, 8 bits, 1 stop bit) holds each bit data in the same manner, and when a stop bit is detected, an interrupt signal INT is output to the microprocessor 6 as shown in (i), When the completion of receiving one frame is notified, 8-bit data (DATA) is output as shown in (j). Here, the detection of the stop bit is determined from the magnitude of the pulse width, similarly to the detection of the start bit.

As described above, the trigger signal Trg2 for detecting the edge interval (pulse width) by the timer means, obtaining OFFset, and causing the trigger signal generating means 4 to adjust the phase at the timing corresponding to the bit center position. And the frame reception buffer means 5 outputs the trigger signal Tr.
Since the timer value is fetched based on g2 and the bit data is demodulated from the value, the FSK demodulation and the start / stop synchronization receiving function can be performed with the same configuration.

FIG. 6 is a block diagram showing the configuration of another embodiment of the present invention. In this embodiment, the circuit assumes that the modulation signal applied to the input terminal IN is an ASK-modulated signal.

FIG. 7 shows the ASK applied to the input terminal IN.
It is a wave form diagram which shows an example of a modulation signal. Here, a communication protocol using an ASK modulated signal developed by Yokogawa Electric is shown. (A) is a bit data string corresponding to a modulation input, (b) is a modulation applied to an input terminal IN. It is an input signal.

The main specifications in the communication protocol using this ASK modulated signal are as follows. Communication method: serial half-duplex, start-stop synchronization, 1 start 8 bits, no parity, 1 stop bit Transmission rate: 1200 baud modulation; ASK "1": No signal "0": 2400
Each pulse width S and X of the modulated signal that is Hz ± 2% ASK modulated,
The relationship between the corresponding bit string data indicating "0" and "1" is as follows.

S = 1 / (2400 × 2) = 208.3 μ
s (constant) X = determined by the length of no signal (bit 1) bt (1 bit length) = 833.3 μs In FIG. 6, the start bit detection means 3 inputs the timer value TM from the timer means 2. , If the pulse width of S described above continues twice, it is recognized as a start bit and the enable signal ENA is output. The trigger signal generating means 4 adds the timer value TM every time the enable signal ENA is received, and outputs the added value (sum1) indicating the time after the start bit is detected, and the enable signal When the signal ENA is received, a 1-bit length is added in synchronization with the trigger signal Trg2, and a second adder 42 that outputs the added value (sum2),
Addition values sum1 and s of the first and second adders 41 and 42
um2, and a comparator 43 that outputs a trigger signal Trg2 each time sum1 ≧ sum2 holds when sum1 and sum2 change.

The operation of the embodiment thus constructed is as follows. FIG. 8 is a time chart showing an example of the operation, and FIG. 9 shows bit data “1” in FIG.
6 is a time chart showing the time axis in the vicinity of the time point of changing from "0" to "0" in more detail. (A) is the input terminal IN
Is a waveform of a modulation signal applied to the edge detection circuit 1
Detects edges at the rising edge and the falling edge of the ASK modulated signal and applies the trigger signal Trg1 as shown in FIG.

The timer means 2 constantly counts the clock CLK, and the trigger signal Trg from the edge detection circuit 1 is used.
The count value is cleared by 1 as shown in (c). Therefore, the timer means 2 outputs the timer value TM corresponding to the edge interval (pulse width) as shown in (d). The start bit detecting means 3 detects the case where the applied timer value TM is S, as shown in (d), and the case where two consecutive times are detected. The change from "1" to "0", that is, the start bit is recognized, and the enable signal ENA is output as shown in (e).

The second adder 42 of the trigger signal generating means 4
Upon receiving this enable signal ENA, outputs a 1-bit length (bt) as shown in (f), and thereafter, every time the trigger signal Trg2 is input, the 1-bit length is sequentially added, and the addition is performed. The value sum2 is output like 2 bt, 3 bt ... In addition, when the first adder 41 receives the enable signal ENA, the first adder 41 thereafter triggers the trigger signal Trg1.
The timer value TM is added in synchronization with
1 is output as shown in (g).

The comparator 43 includes the first and second adders 4
The addition values sum1 and sum2 output from 1 and 42 are constantly compared, and when the relationship of sum1 ≧ sum2 is established, the trigger signal Trg2 is output to the frame reception buffer means 5 as shown in (h). That is, now
Assuming that sum1 = S + X, sum1 (S
+ X)> sum2 (1 bt), and the trigger signal Trg2 is output. Further, this trigger signal Trg2 causes the second adder 42 to add value sum2 = 2 this time.
bt is output, which is sum1 (S + X)> sum
The relationship is 2 (2 bt), and the trigger signal Trg2 is output again.

The frame receiving buffer means 5 fetches the timer value TM at the timing when the trigger signal Trg2 is input, and when the value is X, holds the bit data as "1" and stores the data. When the timer value TM is S, the bit data is set to "0" and the data is held.

FIG. 10 is an operation waveform diagram showing an operation near the stop bit. When the above-described operation is repeated for bit data (8 bits) and the ninth trigger signal Trg2 corresponding to the stop bit is output, the frame reception buffer means 5 causes one frame (1 start, 8 bits). , 1 stop bit) reception completion, and outputs an interrupt signal INT to the microprocessor 6 as shown in (i) to notify completion of 1 frame reception and also to output 8-bit data (DATA) (j). Output as shown in. In addition, the entire hardware is initialized to prepare for the detection of the next start bit.

According to this embodiment, the start bit is detected from the rising and falling edge intervals of the modulated signal, and the time after the start bit is detected is compared with the addition value of 1 bit length to obtain the bit data. Therefore, the demodulation processing of the modulated input signal and the step synchronization receiving processing can be performed at the same time.

In each embodiment, the edge detection circuit 1,
The timer means 2, the start bit detection circuit 3, the trigger signal generation means 4, and the frame buffer means 5 are all shown as functional blocks different from the microprocessor 6, but some or all of these circuit means are It may be realized by firmware in the microprocessor circuit 6.

[0040]

As described above in detail, according to the present invention, attention is paid to the interval (pulse width) between the rising and falling edges of the FSK or ASK modulated signal, and the timer value TM corresponding to the pulse width. Is taken in by a trigger signal Trg2 generated based on the start bit, and bit data is determined from the timer value TM. The demodulation process of the modulated signal and the start / stop synchronization receiving process can be performed with the same structure. it can. Therefore, not only the circuit configuration is simplified, but also the stability and reliability of operation can be improved.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram showing an example of a signal applied to an input terminal IN.

FIG. 3 is a waveform diagram mainly showing a part of FIG.

FIG. 4 is an operation waveform chart showing an example of the operation of FIG.

FIG. 5 is an operation waveform diagram showing an operation near a stop bit.

FIG. 6 is a configuration block diagram showing another embodiment of the present invention.

FIG. 7 is a waveform diagram showing an example of an ASK modulation signal applied to an input terminal IN.

FIG. 8 is a time chart showing an example of the operation of FIG.

FIG. 9 is a diagram showing bit data in FIG.
It is a time chart which expands the time axis near the time of changing to, and shows it in detail.

FIG. 10 is an operation waveform diagram showing an operation near a stop bit.

FIG. 11 is a configuration block diagram showing an example of a receiving device used in a conventional system.

12 is a waveform diagram showing an operation of the start / stop synchronization receiving circuit UR in FIG.

[Description of Codes] IN input terminal 1 edge detection circuit 2 timer means 3 start bit detection means 4 trigger signal generation means 5 frame reception buffer means 6 microprocessor 41 first arithmetic unit 42 second arithmetic unit 43 comparator

Claims (3)

[Claims] 1. A digital signal receiving apparatus for receiving a digital signal transmitted including a pulse signal and demodulating the digital signal into data of "0" and "1", which is included in the received signal. An edge detection circuit that detects a rising / falling edge of a pulse signal and outputs a trigger signal, a timer unit that measures an interval between trigger signals output from the edge detection circuit, and a timer value measured by the timer unit. A start bit detecting means for detecting a start bit based on the above, a trigger signal generating means for outputting a trigger signal based on the start bit detected by the start bit detecting means, and a timer value measured by the timer means are inputted. At the same time, the trigger signal from the trigger signal generating means is input, and the type changed after receiving the trigger signal. A digital signal receiving apparatus, characterized in that it is provided with frame receiving buffer means for judging "0" or "1" of bit data from a value, storing one frame, and outputting predetermined bit data together with an interrupt signal. . 2. The digital signal receiving apparatus according to claim 1, wherein the trigger signal generating means is configured to receive the start bit detected by the start bit detecting means and output the trigger signal at intervals of 1 bit length. 3. The trigger signal generating means receives the enable signal output from the start bit detecting means, adds the timer value output from the timer means, and outputs an added value (sum1) indicating the time after the start bit is detected. When receiving the enable signal output from the adder of 1 and the start bit detecting means, the 1-bit length is added in synchronization with the trigger signal (Trg2) output from the trigger signal generating means, and the added value (sum2) is output. The second adder going forward, and the respective added values (su from the first adder and the second adder
When the addition value from the first adder is larger than the addition value from the second adder (sum1 ≧ sum)
The digital signal receiving apparatus according to claim 1, wherein the trigger signal (Trg2) is output to (2).