JPH06104695A - Digital roll-off filter - Google Patents

Abstract

PURPOSE:To reduce the circuit scale through the reduction in number of multipliers and to prevent the deterioration in the processing by eliminating n-sets of one side multipliers for a center position and instead applying outputs of the n-set of multipliers on the remaining side to an adder at a position symmetrical for the center position. CONSTITUTION:Each output from multipliers 311-31n is branched into two, one of them is fed respectively to adders 332n-33n+1. Thus, an output of the adder 33n is delayed by a unit delay element 32n+1 and added to an output of the multiplier 31n by an adder 33n+1 and fed to a next unit delay element 32n+2. Similarly an output of a unit delay element 322n-1 and an output of the multiplier 312 are added by an adder 332n-1 and its output is delayed by a unit delay element 322n and added to an output of the multiplier 311 by the adder 332n and output data y(n) are outputted from a terminal 34. Thus, outputs by (2n+1) sets of multipliers of a conventional filter are outputted by using (n+1) sets of multipliers 311-316+1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital roll-off filter, and more particularly to a non-recursive (FIR) digital roll-off filter.

[0002]

2. Description of the Related Art Multilevel QAM used in digital communication equipment
In (quadrature amplitude modulation) and the like, a digital roll-off filter is used.

FIG. 3 and FIG. 4 each show a circuit configuration diagram of an example of a conventional transposed non-recursive digital roll-off filter.

In FIG. 3, the input data X (n) coming into the terminal 10 is supplied to _{2n + 1} multipliers 11 _{1 to} 11 _{2n + 1} , respectively, where the tap coefficients C _{−n to} C _n are multiplied. To be done. The output of the multiplier 11 _-n is delayed by the unit delay element 12 ₁ , is then added to the output of the multiplier 11 ₂ by the adder 13 ₁ , is delayed by the next unit delay element 12 ₂ , and is then added by the next adder 1.
3 ₂ and is added to the output of the multiplier 11 ₃ . Similarly, the output of the adder 13 _{2n is} output from the terminal 14 as output data y (n).

In FIG. 4, the input data X (n) from the terminal 20 is supplied to the selector 22 and is also delayed by each of the cascaded unit delay elements 21 ₁ to 22 _2n and supplied to the selector 22. Further, the tap coefficients of the 2n + 1 or from the terminal 24 ₁ to 24 _n to the selector 23 C _-n -C _n
Is being supplied. The data and the tap coefficient that are selected in synchronization by the selectors 22 and 23 are multiplied by the multiplier 25 and supplied to the adder 26, which is added to the previous addition result delayed by the delay element 27 and added to all taps. The sum is latched by the latch circuit 28 and output data y from the terminal 29.
It is output as (n).

[0006]

When the input data is 8 bits and the tap coefficient is 8 bits, the unit delay element and the adder are each composed of about 200 basic cells of a master slice type semiconductor integrated circuit. On the other hand, the multiplier requires about 1400 basic cells.

The conventional circuit shown in FIG. 3 has a problem in that the number of multipliers increases and the circuit scale increases because the multipliers are required for tap coefficients.

Although the conventional circuit of FIG. 4 requires a small circuit scale, there is a problem that the processing speed of the entire circuit is limited by the operation speed of the multiplier 25 and the processing speed becomes slow.

The present invention has been made in view of the above points,
An object of the present invention is to provide a digital roll-off filter capable of reducing the number of multipliers to reduce the circuit scale and preventing a decrease in processing speed.

[0010]

A digital roll-off filter according to the present invention comprises 2n + 1 multipliers for multiplying input data by a center tap coefficient and n tap coefficients symmetrically arranged on both sides thereof. , 2n adders respectively supplied with 2n multiplier outputs excluding the one-side multiplier farthest from the center, and 2n-1 excluding the one-side multiplier output farthest from the center and the final stage Delay the output of each adder and supply to each adder of the next stage 2
In a digital roll-off filter having n adders and extracting the output of the final stage adder as output data, n multipliers on one side of the center are deleted,
Instead, the remaining n multiplier outputs on one side are each fed to adders located symmetrically about the center.

[0011]

In the present invention, since the tap coefficient values at symmetrical positions with respect to the center are the same, the n multipliers on one side are deleted and the remaining n multiplier outputs are substituted. As a result, n multipliers that require a large number of basic cells can be reduced, the circuit scale can be reduced, and a reduction in processing speed can be prevented.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram of an embodiment of the filter of the present invention. In the figure, 1-bit input data X (n) coming into the terminal 30 is supplied to each of _{n + 1} multipliers 31 _{1 to} 11 _{n + 1} . Each of the multipliers 31 _{1 to} 31 _{n + 1} multiplies the input data X (n) by each of the m-bit tap coefficients C _{−n to} C _O and outputs the result. The output of the multiplier 31 ₁ is delayed by the unit delay element 32 ₁ and then added by the adder 32 _{1
The two} outputs are added, delayed by the next unit delay element 32 ₂ , supplied to the next adder 33 ₂ , and added to the output of the multiplier 31 ₃ . In the same manner the adder 33 _n-1 output multiplier 31 n _{+ 1} in adder 33 _n are delayed by the delay unit 32 _n
It is added to the output.

The outputs of the multipliers 31 _{1 to} 31 _n are branched into two, and _one of them is supplied to each of the adders 33 _{2n to} 33 _{n + 1} . Therefore, the output of the adder 33 _n is delayed by the unit delay element 32 _{n + 1} , is added to the output of the multiplier 31 _n by the adder 33 _{n + 1} , and is supplied to the next unit delay element 32 _{n + 2} . After the similar manner the unit delay element 32 _2n-1 output and the multiplier 31 ₂ outputs an adder 33 _2n-1 output obtained by adding the following delayed by the unit delay element 32 _2n, multiplied by the adder 33 _2n 31 ₁ Output data y is added to the output and output from terminal 34
It is output as (n).

Here, in the roll-off filter, the tap coefficient C _-n supplied to each of the multipliers 11 _{1 to} 11 _{2n + 1 in} FIG.
-C _n each have a relationship of C _-n = C _n around the C _O. That is, the output of each of the multipliers 11 _{1 to} 11 _n is the same as the output of each of the multipliers 11 _{2n + 1 to} 11 _{n + 1} , so that n + 1 multipliers 31 _{1 to} 31 _{n + 1 as} shown in FIG. Then, it is possible to obtain the output of _{2n + 1} multipliers 11 _{1 to} 11 _{2n + 1 in} FIG.

By the way, the number l of bits of the input data X (n) and the number m of bits of each of the tap coefficients C _{-n to} C _O generally have a relation of m> l, and the multipliers 31 _{1 to} 31 _{n +. 1} , the number of bits of the output data of each of the adders 32 _{1 to} 32 _2n is m. However, when m ≦ l, the number of bits of the output data of each of the multipliers 31 _{1 to} 31 _{n + 1} and the adders 32 _{1 to} 32 _2n is l.

As described above, in this embodiment, when the number of multipliers in the conventional circuit of FIG. 3 is k, the number of multipliers is reduced to (k + 1) / 2, and the number of basic cells required to form the entire circuit is large. And the circuit scale becomes smaller. Further, as compared with the conventional circuit of FIG. 1, the processing speed is increased only by the delay due to the increase in the wiring for supplying the outputs of the multipliers 31 _{1 to} 31 _n to the adders 33 _{2n to} 33 _{n + 1} . It can perform high-speed processing almost the same as the circuit of.

FIG. 2 shows a circuit configuration diagram of a modified example of the filter of the present invention. In the figure, the difference from FIG. 1 is that the multipliers 31 ₁ ...
For the tap coefficients C _-n -C _O supplied to 31 n + _1, the tap coefficients C _O of the center and the number of bits m, the number of bits of tap coefficients as the distance from the center m-
i ₁ , m−i ₂ , and m−i ₃ are sequentially decreased.

In the roll-off filter, the value of the tap coefficient at the position distant from the center is smaller than that at the center, so that the tap coefficient at the position distant from the center depends on the required accuracy of the roll-off filter. It is possible to reduce the number of bits, which reduces the number of basic cells that form each of the multipliers 31 _{1 to} 31 _n , thereby reducing the circuit scale. In this case, the multipliers 31 _{1 to} 31
_The number of output bits for each of _n is 1 and m-i ₁ , m-i ₂ , m-
i ₃ is the number of bits on the larger side.

[0019]

As described above, according to the digital roll-off filter of the present invention, the number of multipliers can be reduced, the circuit scale can be reduced, and the reduction in processing speed can be prevented, which is extremely useful in practice.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of a filter of the present invention.

FIG. 2 is a circuit configuration diagram of a modified example of the filter of the present invention.

FIG. 3 is a circuit configuration diagram of a conventional filter.

FIG. 4 is a circuit configuration diagram of a conventional filter.

[Explanation of symbols]

31 _{1 to} 31 _{n + 1} multiplier 32 _{1 to} 32 _2n unit delay element 33 _{1 to} 33 _2n adder

Claims (2)

[Claims] 1. The tap coefficient of the center and n pieces on both sides of the tap coefficient.
Multiply the input data by each tap coefficient symmetrically arranged
2n + 1 multipliers to be added and one side multiplier (31₁)
Except for 2n multiplier outputs, each of which is supplied with 2n additions
Bowl (33₁~ 33_2n) And a multiplier (31₁) Out
2n-1 adders (33₁~ 33
_2n-1) Each output is delayed and the adder (33 ₂~ 33
_2n) 2n adders (33₁~ 33_2n)
And the final stage adder (33_2n) Extract output as output data
In the digital roll-off filter, n multipliers on one side of the center are deleted and replaced.
To the remaining n multipliers (31₁~ 31_n) Output
Each of the adders (33
_{n + 1}~ 33_2n) Is configured to be supplied to
Digital roll-off filter. 2. The digital roll-off filter according to claim 1, wherein the number of bits of the tap coefficients of the n + 1 multipliers decreases with distance from the center.