JPH06104661A - Complementary signal generating circuit - Google Patents

Abstract

PURPOSE:To generate complementary signals whose amplitude is equal to each other from one input signal. CONSTITUTION:The circuit is provided with a current/voltage conversion section 3 outputting an inverted signal Vout1, a voltage/current conversion section 2 outputting a noninverting signal Vout2, and a voltage/current conversion section 1 receiving an input signal Vin, and the conversion section 1 converts a positive change +DELTAv of an input signal into a current change +DELTAi, the conversion section 3 outputs an (I1+DELTAi)RL including the current change +DELTAi as an inverting signal, converts the current change DELTAi into a negative voltage change -DELTAv, outputs the voltage chance -DELTAv to the voltage/current conversion section 2, which converts the voltage change -DELTAv into the current change -DELTAi again, outputs an (I1-DELTAi)RL including the current change -DELTAi as a noninverting signal, converts the current change DELTAi into a negative voltage change -DELTAv, and outputs a noninverting signal (I1-DELTAi)R and an inverting signal (I1+DELTAi)RL when the input signal chances by -DELTAv to output complementary signals whose amplitude is 2DELTAiRL.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to electronic equipment, information equipment,
The present invention relates to a complementary signal generating circuit used for communication equipment and the like, and a differential amplifier or a preamplifier using the complementary signal generating circuit.

[0002]

2. Description of the Related Art FIG. 9 shows an example of a conventional differential amplifier.
It is often used as a complementary signal generating circuit. That is, conventionally
A differential amplifier as shown is mainly used to generate complementary signals. Here, the complementary signal means a normal signal and its inverted signal obtained from one input signal. That is, in the illustrated circuit, the inverted signal V _out1 and its non-inverted signal V _out2 are referred to as complementary signals as output signals with respect to the input signal V _in . In the figure, V _DD is the first power supply, V _SS is the second power supply (ground), Q ₁ and Q ₂ are field effect transistors (FET),
I ₀ is a constant current source.

[0003] In the illustrated circuit, receives the input signal V _in to the terminal, giving the reference voltage V _ref to the terminal, the input signal V _in
The difference between the reference voltage V _ref and the reference voltage V _ref is amplified (or attenuated), and the inverted signal V _out1 is output from the terminal and the normal signal V _out2 is output from the terminal as complementary signals.

[0004]

FIGS. 10A and 10B are explanatory views of the problems of the above circuit. It is known that when the transistors Q ₁ , Q ₂ and Q ₃ are composed of bipolar transistors (BJT), there is no difference between the amplitudes of the inverted signal V _out1 and the non-inverted signal V _{out2 in} the above-mentioned circuit, and it operates without problems. There is. However, Q ₁ , Q ₂ , and Q ₃
If the input signal V _in is higher or lower than the reference voltage V _{ref as in} (A), the amplitude (that is, gain) of the inverted signal V _out1 and the non-inverted signal V _out2 as in (B). )
There was a problem that there was a difference.

This is because the operating states of the transistors Q ₁ and Q ₂ are different, the transistor Q ₁ is grounded at the source, the transistor Q ₂ is grounded at the gate, and the current of Q ₃ depends on V _ds. It is due. That is, when the input signal V _in is higher than the reference voltage V _ref , the current value flowing through the transistor Q ₁ becomes larger than the current value flowing through the transistor Q ₂ , and as a result, a difference occurs between the output voltage of the terminal and the output voltage. is there. Therefore, this voltage difference appears as a difference between the amplitudes of the inverted signal V _out1 and the non-inverted signal V _out2 , and is due to the transistors Q ₁ and Q ₂ not operating symmetrically.

An object of the present invention is to generate complementary signals having the same amplitude from one input signal, and further, to generate this complementary signal does not require a reference voltage.

[0007]

FIG. 1 is a block diagram showing the principle of the present invention. As shown in the figure, the complementary signal generating circuit according to the present invention includes two voltage / current converters 1 and 2 and one current / current converter.
It comprises a voltage converter 3 and a load resistor _RL each connected to the first power supply V _DD . The voltage / current converter 1 is connected to the terminal to receive the input signal V _in , the current / voltage converter 3 is connected to the terminal to output the inverted signal V _out1 , and the voltage / current converter 2 is connected to the terminal. And outputs the forward rotation signal V _out2 . Further, the current / voltage conversion unit 3 is the voltage / current conversion unit 2
It is connected to the.

[0008]

According to the complementary signal generating circuit of the present invention, the current flowing through the voltage / current converter 1 is I ₁ when the voltage of the input signal V _in is 0v. Then, the voltage change + Δv of the input signal V _in input to the terminal is converted into the current change + Δi by the voltage / current converter 1. Current / voltage converter 3
Outputs the voltage (I ₁ + Δi) _RL including the current change + Δi to the terminal and obtains the inverted signal V _out1 . Further, the current / voltage conversion unit 3 converts the change Δi of the current into an inverted voltage change −Δv, and further outputs the voltage change −Δv to the voltage / current conversion unit 2, and the voltage / current conversion unit At step 2, the change in current is converted to Δi again. Voltage / current converter 2
Outputs a voltage (I ₁ -Δi) R _L, including changes -Derutaai current to terminal, obtain an inverted signal V _out2.

On the contrary, when the input signal V _in changes by −Δv, the above is all reversed, and the inverted signal V _out1 becomes the voltage (I ₁
-Δi) _RL , the forward rotation signal V _out2 is the voltage (I ₁ + Δi)
Become _RL . Therefore, it is possible amplitude outputs complementary signals 2ΔiR _L (see FIG. 5). In this case, as a condition, it is necessary that the input signal V _in is an AC signal that changes Δv toward the + side and Δv toward the − side around 0v. The case where the input signal V _in includes a DC component will be described later.

[0010]

FIG. 2 shows an embodiment of the complementary signal generating circuit of the present invention.
It is a circuit diagram. As shown in FIG.
Transistor Q₁As a current / voltage conversion unit 3.
Register Q₂As a voltage / current converter 1
Q₃Apply respectively. As shown,
Star Q₁~ Q₃Is composed of a FET. Also, Transis
Q₂Of the gate G of the transistor Q₃To the source S of
Transistor Q ₃Of the gate G of the transistor Q₂of
The sources S are connected to each other. And to
Langista Q₁~ Q₃Are FETs that have almost the same characteristics
And the gate-source voltage of each transistor
Pressure V_gsCurrent I (= I₁= I₂)
It

Here, as a condition, the input signal V _in is 0 v
It is necessary that the AC signal be such that Δv changes to the + side and Δv changes to the − side with respect to the center. The case where the input signal V _in includes a DC component will be described later. Now, the input signal V _in is + Δ
v when changed, the transistors Q ₁ and Q ₂ are current (I ₁ + Δi) flows, V _gs2 of V _gs1 the transistor Q ₂ of the transistor Q ₁ is changed by equal [Delta] V _gs.
At this time, if the source voltage of the transistor Q ₂ is V ₁ and the source voltage of the transistor Q ₃ is V ₂ , then V ₂ −V
_{Since 1} = ΔV _gs , the change of V _gs3 of the transistor Q ₃ becomes −ΔV _gs , and the current I ₂ changes by −Δi. On the other hand, when the input signal V _in changes by −Δv, the sign is simply inverted from the above description. It should be noted that V _DD is the first power supply (that is, the B power supply) and V _SS is the second power supply (for example, the ground potential). Further, R _L1 and R _L2 are respective load resistances.

Therefore, the output voltages V _out1 and V _out2 are as follows. (When the input signal V _in changes by + Δv) V _out1 = V _DD − (I + Δi) R _L1 V _out2 = V _DD − (I−Δi) R _L2 (when the input signal V _in changes by −Δv) V _out1 = V _DD −R _L1 (I−Δi) V _out2 = V _DD −R _L2 (I + Δi)

Incidentally, the diode D₁~ D_FourIs for voltage adjustment
Element. As shown, transistor Q₂Is V₂
The gate is grounded through. On the other hand, transistor Q₁
Is source grounded. Therefore, the transistor Q₂When
Q₃In order to accurately apply the gate potential of the diode D
₁~ D₃And D_FourIs provided. 3 (A) and (B)
FIG. 4 is an explanatory diagram of FET characteristics. Understand the essence of the invention
The characteristics shown in this figure are especially important for the purpose. (A) is V_ds─I
_DRelationship, (B) is V_gs─I_DRelationship. here,
Between gate and source, which is an important point of the circuit of the present invention
Voltage V_gsAnd drain current I_DThe relationship between
To do. In FET, drain-source voltage V_dsSaturated area
The operation in the range is V_dsCurrent I _DIs almost constant
Can be seen as V_ds─I_DOf the good linearity of
The linearity of the FET can be secured by using it.
it can. A circuit is constructed by taking advantage of this feature.

When V _gs = 0 in the saturation region where the V _{ds of the} FET is sufficiently large, the state a in which the current I flows is obtained. There are two methods for transitioning from the state a to the state b (state c), one of which changes V _gs by ΔV _gs (−ΔV _gs ) and the other of which changes the current I by Δi (−Δi). . That is, Δi (−Δi) for changes in ΔV _gs (−ΔV _gs )
Change and ΔV _gs (-
ΔV _gs ) will change.

Therefore, in the circuit example shown in FIG. 2, the change amount of the current generated in the transistor Q ₁ is converted into V _gs in the transistor Q ₂ and the reverse sign, + → − (or − →
+) A manner, by the V _gs of the transistor Q _3, transistor Q ₁ of the current change of the transistor Q ₃
It can be corrected in the opposite direction. 4A and 4B are waveform diagrams when the input signal V _in is changed by ± Δv. In (A), the state a changes when V _in does not change (corresponding to a in FIG. 3), the state b changes + Δv (corresponding to b in FIG. 3), and the state c changes −Δv (FIG. 3). Corresponds to c). (B), the output voltage (complementary signals) V _out1 and V _{ou t2} is the amplitude as indicated by a dotted line are the same.

The input signal V is shown in FIGS._inIs +
FIG. 9 is a waveform diagram when Δv is changed to the side. In this case, the output
Voltage (complementary signal) V_out1And V_out2Is as shown by the dotted line
In addition, the amplitude is almost unchanged, and the waveform becomes symmetrical. this is
V mentioned above_out1And V_out2It is clear from the formula. Figure 6
It is a circuit diagram of another embodiment of the present invention. This circuit is shown in Figure 1
A DC compensation circuit is added. In the above description, the article
The input signal V_inIs on the + side around 0v
The AC signal was changed by Δv toward the v and − sides. In this example
Force signal V_inIs the case that the DC component is included in the
A flow compensation circuit DC is added. That is, the resistance R₃And con
Densa C₁The central value detection circuit CL composed of
Issue V _inTransistor Q to receive_FourConnect to the gate of
To do. Therefore, the central value detection circuit CL is_inin
The core value can be detected, and this detected value is
Q_FourSupply to the gate of the
It is carried out.

According to this circuit, the output waveform shown in FIG. 4B can be obtained in the case of the input signal shown in FIG. 5 (only the change of + Δv). 7 (A) and (B)
FIG. 7 is a waveform diagram of input and output signals of the circuit of FIG. Thus, this circuit by direct current compensation, using the center value of the input waveform, the inverted signal as shown in FIG. 5 V _out1
And the central value of the _normal rotation signal V _out2 are matched. The diodes D _{1 to} D ₁₀ are gate voltage adjusting elements as described above.

FIG. 8 is a circuit diagram of still another embodiment of the present invention. By applying the complementary signal generation circuit to a transimpedance type preamplifier, this circuit can be used as a complementary signal generation circuit while maintaining the linear amplification characteristics of the transimpedance type preamplifier.
Since the conventional transimpedance type preamplifier circuit cannot generate a complementary signal as shown in FIG. 11, it is necessary to connect a differential amplifier of the one-sided reference voltage _{Vref to} the _subsequent stage. Using the output V _pre of the preamplifier input to the terminal of the transistor Q ₄ of this differential amplifier as an input signal, the magnitude comparison with the reference voltage V _ref input to the transistor Q ₅ is performed to obtain complementary signals from the terminals and There is.

However, the transistor Q ₆ has a bipolar
When a transistor is used, there is no problem, but when an FET is used, there is a problem that the output signal amplitude of the differential amplifier is output as different amplitudes for the normal rotation signal and the inverted signal. That is, similar to the problem of FIG. 9 described above, there is a difference in amplitude between the normal signal and the inverted signal when the output V _{pre of} the preamplifier is higher than or lower than the reference voltage V _ref .

The circuit of FIG. 8 is a preamplifier that solves this problem.
FIG. That is, in the complementary signal generating circuit
Force signal V_inTransistor Q₁If you type in
As is clear and clear, transistor Q₂And Q₃Shake
Output signal V with the same width_Q2And V _Q3And these are tran
Dista Q_FourAnd Q₆Entered in. Therefore, Transis
Q_FourAnd Q₆If the characteristics of are the same, OUT1 and OUT
The characteristic of 2 is the output signal V _Q2And V_Q3Increased with the same characteristics
The width can be output.

[0021]

As described above, according to the present invention,
A complementary signal having the same amplitude can be generated from one input signal, and a reference voltage is not required for generating the complementary signal.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a circuit diagram of an embodiment of the present invention.

FIG. 3 is an explanatory diagram of FET characteristics.

FIG. 4 is an output waveform diagram (No. 1) according to the present invention.

FIG. 5 is an output waveform diagram (No. 2) according to the present invention.

FIG. 6 is a circuit diagram of another embodiment of the present invention.

FIG. 7 is an output waveform diagram (No. 3) according to the present invention.

FIG. 8 is a circuit diagram of still another embodiment of the present invention.

FIG. 9 is an example of a conventional differential amplifier.

FIG. 10 is an explanatory diagram of a problem of the circuit in FIG.

FIG. 11 is another example of a conventional circuit.

[Explanation of symbols]

1 ... Voltage / current converter 1 2 ... Voltage / current converter 2 3 ... Current / voltage converter Q _{1 to} Q ₆ ... FET V _DD ... First power supply V _SS ... Second power supply V _in ... Input signal V _out1 … Inverted signal V _out2 … Normal signal

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Isao Tsuyama 3-28-1, Joto, Oyama-shi, Tochigi Prefecture Fujitsu Digital Technology Limited (72) Inventor Akihiko Ishikawa 3-28-1, Joto, Oyama-shi, Tochigi Prefecture Within Fujitsu Digital Technology Limited (72) Inventor Yoshihisa Kondo 3-28-1, Joto, Oyama City, Tochigi Prefecture Within Fujitsu Digital Technology Limited

Claims (5)

[Claims] 1. A complementary signal generating circuit for generating a complementary signal composed of a non-inverted signal and its inverted signal with respect to one input signal, through a load resistor ( _RL ) to a first power source (V _DD ). And a current / voltage converter (3) that outputs an inverted signal (V _out1 ) and is connected to the first power source via a load resistor ( _RL ).
A voltage / current converter (2) connected to the current / voltage converter and a second power supply (V _SS ) and outputting a _normal rotation signal (V _out2 ), the second power supply and the current / voltage It is connected to the converter, and a voltage / current converter receiving an input signal (V _in) (1), wherein the input signal (V _in) is Δv in the + direction around the 0 v,
When the AC signal changes Δv to the − side, the + side change + Δv of the voltage of the input signal (V _in ) is converted into a current change + Δi by the voltage / current conversion unit (1), and the current / The voltage converter (3) outputs the voltage (I ₁ + Δi) _RL including the current change + Δi as an inversion signal (V _out1 ), and the current change Δi is a negative voltage change −
The voltage / current conversion unit (2) converts the voltage change into Δv and outputs the voltage change−Δv to the voltage / current conversion unit (2).
To the voltage (I ₁ −
Δi) _RL is output as a normal signal (V _out2 ), and conversely, when the input signal (V _in ) changes by −Δv, all of the conversion units described above operate in the opposite manner to the inverted signal (V _in ). the V _out1) as the voltage (I ₁ -Δi) R _L, and outputs a voltage (I ₁ + Δi) R _L as the normal signal (V _out2), from these, so that the amplitude outputs complementary signals 2DerutaiR _L Complementary signal generation circuit. 2. The voltage / current converter (1) is a field effect transistor FET (Q ₁ ), the current / voltage converter (3) is FET (Q ₂ ), and the voltage / current converter (2).
Are composed of FETs (Q ₃ ) respectively, and FETs (Q ₂ )
The gate G of the FET to the source S of the FET (Q ₃ ) and FE
Gate G of T (Q ₃ ) to source S of FET (Q ₂ )
The FETs (Q _{1 to} Q ₃ ) connected to each other are FETs having substantially the same characteristics, and the current I (= I ₁ = I) at which the gate-source voltage V _{gs of} each FET becomes 0 v.
₂ ) The complementary signal generating circuit according to claim 1, wherein 3. A DC compensating circuit (DC), wherein when the input signal (V _in ) includes a DC component, the center value of the input signal is detected and the center value is used as the input signal. The complementary signal generation circuit described in 1. 4. A resistor (R ₃ ) for receiving an input signal and a capacitor (C) for blocking direct current are provided in an input stage of the direct current compensation circuit.
4. The complementary signal generating circuit according to claim 3, further comprising a center value detecting circuit (CL) constituted by ₁ ). 5. The complementary signal generating circuit according to claim 1, further comprising a transimpedance type preamplifier having transistors (Q ₄ and Q ₆ ) for receiving a complementary signal which is an output of the preceding stage.