JPH06104409A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a base cell in a matrix shape with improved integration and reliability on a substrate in a gate array made up of a CMOS semiconductor device. CONSTITUTION:P-type and n-type source/drain regions 2 and 5 are formed on a substrate, and p-channel and n-channel MOS transistors are formed at each cross part with a polysilicon 3 so that a base cell is constituted. Moreover, n-type and p-type high-density impurity regions 1 and 4 are formed in a surrounding part thereof, and a part thereof elongated lengthwise is put in parallel with power lines 7a and 7b. The power lines 7a and 7b are connected to the high-density impurity regions 1 and 4, and the power-supply current is shunted so that a power line thicker than a signal line becomes not necessary, and integration in the device can be improved.

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a CMOS (complementary MO
S) The present invention relates to a structure of basic cells arranged in a matrix on a substrate in a gate array using a semiconductor. 2. Description of the Related Art Conventionally, as shown in FIG. 8, a device of this type has a structure in which 2 P-type source / drain regions and 5 N-type source / drain regions are crossed by 3 polysilicon regions. The basic cells are arranged in a matrix on the semiconductor substrate. In this case, 10 is an N-type channel stopper region, 11 is a P-type channel stopper region, 16
Is a P-well. Reference numerals 7, 7a, 7b are first-layer metal wirings, and 6 is metal wirings, polysilicon and P.
And N-type source / drain regions are connected to each other. In the metal wiring of FIG. 8, 7a is a plus side power source line and 7b is a minus side power source line. The central P-type transistors are connected in series and the N-type transistors are connected in parallel by metal wiring. FIG. 4 is a transistor circuit diagram equivalent to FIG. As can be seen from this figure, FIG.
Wiring is performed so as to form an R gate. In FIG. 8, polysilicon 3 running laterally on the upper and lower sides of the basic cell is a signal line for passing a signal across the inside of the cell. This signal line is used, for example, when the terminal 501 from the cell A and the terminal 502 from the cell B shown in FIG. The conventional technique has the following problems because the above-described basic cell structure is general. When an electric signal passes in the lateral direction of FIG. 8, the resistance of polysilicon and the resistance of polysilicon and P
Type or N-type source / drain capacitance has the drawback of increasing the propagation delay time of an electric signal. Therefore, even when the basic cells are arranged in a matrix, the circuit scale is restricted if the semiconductor device requires a high operation speed. It is not appropriate to make the power supply line the same thickness as a general signal line from the viewpoint of current capacity of metal wiring. If the substrate contact is made to the power supply line in units of basic cells, the area of the cells increases and the degree of integration is reduced. As shown in FIG. 8, the input terminal is used by dropping it to the power supply line (this is generally the case when one terminal of, for example, a 10-input NAND gate circuit is dropped to a positive power supply and used as a 9-input NAND gate. By doing this, it is possible to reduce the number of types of logical function blocks created by wiring on the basic cell, and to facilitate library management of the functional block), if the logical function is wired on the basic cell. It is difficult to handle the block (2-input NOR gate) as a black box as shown in FIG. 6, and it becomes impossible to process the input terminal outside the black box. In other words, the wiring on the basic cell could not be made into a black box. The contact of the power source to the substrate or well around the source / drain of the basic cell is not sufficient, and the potential of the substrate or well may fluctuate due to the operation of the transistor. SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and a MOS forming a basic cell is formed.
An attempt is made to realize higher integration, higher reliability, and higher speed by providing an opposite conductivity type high impurity concentration region parallel to the power supply line adjacent to the transistor (FET) pair and shunting the power supply current. It is a thing. According to the present invention, in a semiconductor device having basic cells formed in a row in one direction on a first conductivity type semiconductor substrate, the basic cells are: A first transistor having a source / drain region of a second conductivity type formed in a region of the first conductivity type in the semiconductor substrate; and a first transistor formed in a region of the second conductivity type in the semiconductor substrate. A second transistor having a source / drain region of one conductivity type is adjacently arranged in a direction substantially orthogonal to the one direction, and the source / drain region of the second conductivity type of the first transistor is disposed on the second transistor. A first power supply line is arranged so as to pass in one direction, and a second power supply line is arranged so as to pass over the source / drain region of the first conductivity type of the second transistor in the one direction. , The first transition A shunt of a power supply current having a power supply potential applied to the first power supply line extending in the one direction in the first conductivity type region adjacent to the second conductivity type source / drain region. A first-conductivity-type impurity region that acts so as to extend in the one direction in the second-conductivity-type region adjacent to the first-conductivity-type source / drain region of the second transistor. A second conductivity type impurity region is formed which acts so as to shunt a power supply current having a power supply potential applied to the formed second power supply line. According to the present invention, the opposite conductivity type high impurity concentration region parallel to the power supply line is provided adjacent to the pair of MOS transistors (FET) forming the basic cell, and the power supply current is shunted. Thus, it is not necessary to reduce the load on the power supply line and widen the width of the power supply line. FIG. 7 is a plan view of a basic cell of the present invention,
2 is a P-type source / drain region, 5 is an N-type source / drain region
The drain region 3 is polysilicon. The intersections of the source / drain regions 2 and 5 and the polysilicon 3 are P-channel and N-channel MOS, respectively.
Forming a transistor. Reference numeral 1 denotes an N-type high impurity concentration region, 4 denotes a P-type high impurity concentration region, which are P-type source / drain regions 2 and N of the basic cell, respectively.
The source / drain region 5 of the mold is surrounded from three directions. Reference numeral 10 is an N type, 11 is a P type channel stopper region, and 16 is a P well. FIG. 1 shows an embodiment in which wiring is provided on top of FIG. 7, and the equivalent circuit is a 2-input NOR circuit as shown in FIG.
Wiring is performed so as to form a gate.
Reference numerals 7, 7a and 7b are first-layer metal wirings, and 9 is a second-layer metal wiring. Reference numeral 6 is a contact that connects the first-layer metal wiring to the P-type and N-type source / drain and the high impurity concentration region, and 8 is a through hole that connects the first-layer metal wiring and the second-layer metal wiring. Is. A two-input NOR gate is configured by the two-layer metal wiring, and the input terminal A1 is connected to the positive power supply line VDD and the input terminal A is connected to the positive power supply line VDD.
2 is connected to the minus power supply line VSS, but is a high impurity concentration region 1 surrounding the first-layer metal wiring 7 and the basic cell.
Alternatively, it is connected to the power supply line via 4. Therefore, since the high impurity concentration regions 1 and 4 are connected to the power supply potential, it is possible to stabilize the potential fluctuation of each substrate and the well, prevent malfunction of the transistor, and stabilize the operation. The portions of the high-impurity regions 1 and 4 shown in the vertical direction are arranged in parallel with the power supply line and are connected to the power supply line, thereby shunting the power supply current. Basically, the input cells of A1 and A2 can be arbitrarily selected from two power supply lines VDD and VSS because the basic cell is symmetrical. FIG. 2 is a sectional view of the P-channel transistor of FIG. 1 viewed in the direction of the power supply line VDD, and FIG. 3 is a sectional view of FIG.
FIG. 5 is a cross-sectional view of the N-channel transistor of FIG. 6 when viewed in the power supply line VSS direction. Reference numerals 1 to 11 and 16 in the figure
Means the same as in FIG. Reference numeral 12 is an oxide film, 13 is a gate oxide film, and 14 and 15 are insulating films for insulating metal wiring. In the second-layer metal wiring 9 shown in FIG. 1, the metal wiring running horizontally above and below the basic cell corresponds to the polysilicon wiring running horizontally described in the basic cell of FIG. is there. Further, in the embodiment of FIG. 1, all the electric signals running in the lateral direction use the second layer metal wiring. Due to such a structure, even when an electric signal passes laterally as in the conventional basic cell shown in FIG. 8, polysilicon passes through the P-type and N-type source / drain regions. It is possible to reduce the delay of the signal, which is disadvantageous in terms of circuit characteristics due to the resistance and capacitance generated when the signal is applied. Regarding the power supply line, in the embodiment shown in FIG.
Since the plus side has the N-type high impurity concentration region 1 and the minus side has the P-type high impurity concentration region 4 in parallel with the first-layer metal wiring, the power supply current is bypassed using this region. . Since it did in this way, the metal wiring of the 1st layer for power supplies may be the same as a general signal line like before,
It need not be larger than the signal line. Therefore,
The degree of integration can be further improved. Furthermore, since the power supply line of the first layer can be connected to the high-concentration impurity regions 1 and 4 below the metal wiring of the second layer, which extends above and below the basic cell in the lateral direction, in other words, By doing so, since it is possible to connect the power supply line to the substrate in units of basic cells, it is possible to stabilize the substrate potential of the MOS transistors in each basic cell and to take measures against latch-up peculiar to CMOS, which makes the IC more reliable. Can be converted. Next, the processing of the input terminal will be described.
The basic cell of FIG. 1 has a structure in which a logic circuit formed on the basic cell can be made into a black box as shown in FIG. When the actual pattern shown in FIG. 1 is symbolized, it can be seen that the processing of the input terminal is performed outside the black box. By considering the outer region as a wiring region, the wiring work of the entire IC can be replaced with the wiring work between the black boxes. As is apparent from the above description, according to the present invention, the first transistor having the second conductivity type source / drain region and the first conductivity type source / drain region are provided. In a semiconductor device in which basic cells each including a second transistor are formed in a row, an impurity region having a conductivity type opposite to that of each source / drain region and having the same conductivity type as a substrate or a well is used as a power supply line. Since they are arranged in parallel and the power supply current is shunted, the power supply line may be the same as a general signal line as in the conventional case, and need not be larger than the signal line. Therefore, there is an advantage that the degree of integration can be further improved, and high reliability, high speed, and large scale can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view showing wiring on a basic cell of an embodiment of a semiconductor device of the present invention. FIG. 2 is a sectional view taken along the power supply line VDD in FIG. 3 is a cross-sectional view taken along the power supply line VSS in FIG. FIG. 4 is an equivalent circuit diagram showing a method of connecting the constituent elements of FIGS. 1 and 8. FIG. 5 is an explanatory diagram of a case where a wiring passes in a cell in a lateral direction. FIG. 6 is an explanatory diagram showing the plan view of FIG. 1 as a symbol diagram. FIG. 7 is a plan view of an example of a basic cell of a semiconductor device of the present invention. FIG. 8 is a plan view of a conventional semiconductor device. [Explanation of symbols] 1,4 high impurity concentration region 2,5 source / drain region 3 polysilicon 6 contacts 7, 7a, 7b first layer metal wiring 8 through hole 9 second layer metal wiring 10, 11 channel stopper 12 oxide film 13 gate oxide films 14 and 15 insulating film 16 well

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Claims (1)

What is claimed is: 1. A semiconductor device having a basic cell formed in a row in one direction on a semiconductor substrate of a first conductivity type, wherein the basic cell is of a first conductivity type in the semiconductor substrate. A first transistor having a source / drain region of the second conductivity type formed in the region, and a source / drain region of the first conductivity type formed in the region of the second conductivity type in the semiconductor substrate. A second transistor is disposed adjacent to the second transistor in a direction substantially orthogonal to the one direction, and the first transistor is configured to pass over the second conductivity type source / drain region of the first transistor in the one direction. A power source line is disposed, and a second power source line is disposed so as to pass over the source / drain region of the first conductivity type of the second transistor in the one direction; Conductive source A first conductivity type that acts so as to shunt a power supply current of a power supply potential applied to the first power supply line that is formed to extend in the one direction in the first conductivity type region adjacent to the drain region. An impurity region is formed, and the second power supply line extending in the one direction is formed in the second conductivity type region adjacent to the first conductivity type source / drain region of the second transistor. A semiconductor device characterized by forming a second conductivity type impurity region which acts so as to divide a power supply current having an applied power supply potential.