JPH06103785A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To shorten delay time of a selecting circuit and to increase operating speed of a memory system by supplying a current to a emitter or a collector of either of a pair of transistors in accordance with a selecting signal and adding a selecting function. CONSTITUTION:In the case of data of a memory cell MC1 being 0 and transistors Q2 and Q4 being turned on, when a non-selecting signal /SEL is made a H state and a transistor Q7 is turned on, transistors Q5 and Q3 are turned on, and output signals O and /O both are made a L state. Further, in the case of data of the MCI being 0 and transistors Q1 and Q3 being turned on, when /SEL is made a H state and the transistor Q7 is turned on, transistors Q6 and Q4 are turned on, and signals O and /O are made a L state. Therefore, when emitters of output transistors Q9 and Q10 are respectively connected to emitters of transistors Q11 and Q12 of a sense circuit as wired OR, only output signals of a selected sense circuit are outputted to 0 and /0 terminals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a memory circuit technology suitable for speeding up a memory system.

[0002]

2. Description of the Related Art It is desirable that a memory has a high read speed and a large storage capacity. However, for economical and technical reasons, generally, a high-speed one has a small capacity and a large-capacity one has a low capacity. For this reason, in the current memory system for middle- and large-sized computers, a hierarchical storage system is adopted in which a high-speed small-capacity memory (cache memory) is the peak and a low-speed large-capacity memory (main memory) is the base.
In this hierarchical storage system, the information required by a certain program is deviated from the specific information, that is, when a certain program is executed, the data that the central processing unit (CPU) calls is a certain limited memory area. It utilizes that there is a high probability that it exists inside. That is, if the data of the frequently used area in the main memory is transferred to the cache memory, the read speed apparently becomes close to the read speed of the cache memory and the storage capacity becomes the same as the storage capacity of the main memory.

In the following, the principle of this hierarchical storage system will be explained with a simple example. FIG. 2 is a diagram showing a two-level memory system. In the following, the storage capacity of the main memory as shown in FIG. 2 is 32 Kbytes (= 2 15 bytes, which will be referred to as 2 ^ 15 bytes hereinafter), and the storage capacity of the cache memory is 512 bytes (= 2 ^ 9). 2) memory system of two layers. The storage capacity of the main memory is 32 Kbytes (= 2 ^ 15 bytes), so when a program needs 1 byte of data, C
The PU will access the data with a 15-bit address. Below, this 15-bit address is the CP
Called U address. Here, the 15-bit CPU address is divided into two. That is, the lower 9 bits are used as an index address and the remaining upper 6 bits are used as a tag address. Obviously, accessing the main memory requires both the index address and the tag address. On the other hand, the number of bits of the index address (9 bits) matches the number of bits of the address required to access the cache memory (2 ^ 9 bytes). Generally, when the storage capacity of the main memory is 2 ^ n bytes and the storage capacity of the cache memory is 2 ^ k bytes, n
The bit CPU address is divided into a k-bit index address and an nk-bit tag address. Then, an n-bit address is used to access the main memory, and a k-bit index address is used to access the cache memory.

FIG. 3 shows the configuration of the main memory and the cache memory and the configuration of the table memory for storing the address correspondence between the main memory and the cache memory. When transferring new data from main memory to cache memory,
The CPU memory accesses the main memory to read the data, the index address accesses the cache memory to write the data, and at the same time, the index address accesses the table memory to write the tag address. When the CPU calls the data, the cache memory is accessed by the index address to read the data, and at the same time, the table memory is accessed by the index address to read the tag address. This tag address is compared with the tag area of the CPU address, and if the two tag addresses match, it means a hit, and the data read from the cache memory becomes the desired data. If the two tag addresses do not match, it means that a mistake has occurred and the data will be called from the main memory. Next, this data is written in the cache, a new tag address is written in the table memory, and the cache is updated. In this method, if the data of different tag addresses with the same index address is accessed alternately, the hit rate decreases. However, memory areas separated in this way (in this example, the address Hamming distance is 51
It becomes 2. ) The probability of alternately accessing is small. Hereinafter, a specific example of the hierarchical storage method described above will be shown with reference to FIG. Now, at address 123 of the cache memory, at address 0123 of the main memory (index address = 12
Data B of (3, tag address = 00) is stored, and the tag address 00 is stored at address 123 of the table memory corresponding to this. Here, the CPU is CP
When the data at the U address 00123 is requested, the cache memory is accessed by the index address 123 and the data B is read, and at the same time, the table memory is accessed by the index address 123 and the tag address 00
Read out. Since this tag address 00 matches the tag area 00 of the CPU address (hit), the data B read from the cache memory becomes the desired data.
Next, when the CPU requests the data at the CPU address 01123, the cache memory is accessed by the index address 123 and the data B is read, and at the same time, the table memory is accessed by the index address 123 and the tag address 00 is read. Since the tag address 00 and the tag area 01 of the CPU address do not match (miss), the data E is called from the main memory. Next, this data E is written in the address 123 of the cache, a new tag address 01 is written in the table memory, and the cache is updated.

As described above, the drawback of the method of FIG. 3 is that a plurality of data having the same index address but different tag addresses cannot be stored in the cache memory at the same time. Therefore, in order to solve this drawback,
A method in which a plurality of data having the same index address can be simultaneously stored in the cache memory is also adopted. Figure 4
Is provided with two sets each of a cache memory and a table memory (first and second cache memories and first and second table memories), and two pieces of data having different tag addresses with the same index address can be simultaneously stored in the cache memory. An example of doing so is shown. In this way, the more data with the same index address to be stored in the cache memory, the higher the hit rate, but the required storage capacity of the cache memory also increases, so an optimal design is required for each memory system. become.

Next, FIG. 5 shows a conventional example in which the cache memory and the table memory of FIG. 4 are constituted by a semiconductor memory.
In the figure, CMA1 and CMA2 are first and second cache memory cell arrays, and TMA1 and TMA2 are first and second table memory cell arrays. Further, IA and TA are an index address and a tag address, respectively,
DECs 1, 2, 3, 4 are decoders, S1, 2, 3, 4 are sense circuits, CMP1, 2 are compare circuits, and SEL is a select circuit. Also, DATA1 and 2 are the first and second
Data output of the cache memory of HIT1, 2 is DA
This is a signal indicating whether TA1 or 2 has hit or missed. Further, DATA outputs the hit data when either DATA 1 or 2 hits, and outputs either one of the data when both DATA miss.
HIT is a signal indicating whether the data hit the DATA or missed the data. Now, when the CPU inputs the index address IA to the memory to call data, the IA is decoded by the decoders DEC1 and DEC3, and the cells in the cache memory cell arrays CMA1 and CMA2 are selected. The stored data of the selected cell is the sense circuits S1, 3
Are detected and output as DATA1 and DATA2. In parallel with this, the IA is decoded by the decoders DEC2, 4 to select the cells in the table memory cell array TMA1, 2. The tag address stored in the selected cell is detected by the sense circuits S2 and S4. Here, the compare circuits CMP1 and 2 are provided with the tag address detected by the sense circuits S2 and 4 and the tag address TA input from the CPU.
Are compared, and the comparison result is output as HIT1 and 2 signals. Based on the HIT1 and 2 signals, the select circuit SEL outputs the hit data as DATA when one of DATA1 and DATA2 hits, and outputs a signal indicating the hit to HIT. Further, when both are missed, either one of the data is output as DATA and a signal indicating the miss is output to HIT.

FIG. 6 is a diagram showing an example of a conventional select circuit. In addition to the select circuit SEL, the memory cell MC and the sense circuit S are also shown in the figure. This sense circuit is the most frequently used circuit in ultra high speed memory,
An extremely high speed operation is realized by including the grounded base transistors Q3 and Q4. When the non-select signal / SEL goes high, the select circuit SEL forces the output signal O to go low, no matter what the output data of the sense circuit S is. That is, / SEL is H
When it reaches the level, the transistor Q8 turns on.
In both cases, 1 and Q3 are on, and Q2 and Q4 are on, the output signal O becomes L level.

As described above, the conventional semiconductor memory shown in FIG. 5 uses the select circuit SEL shown in FIG.
It realizes the functions of cache memory and table memory shown in. However, in this conventional example, no consideration was given to the speedup of the memory system.

[0009]

In recent years, the demand for higher performance of memories has become extremely strong, and the speeding up of memory systems has become an extremely important issue. Therefore, the inventors of the present invention have examined the cause of impeding the speeding up of the memory system in the conventional example shown in FIG. As a result, they have found that the delay time of the gates forming the select circuit SEL impedes the speedup of the memory system.

An object of the present invention is to reduce the delay time of the select circuit and speed up the memory system.

[0011]

SUMMARY OF THE INVENTION In a semiconductor memory, an object is to include a base grounded transistor pair in which an emitter is connected to a common sense line, a constant voltage is applied to a base, and information is output from a collector. This is accomplished by providing the sense circuit with means for supplying current to either the emitter or collector of either of the transistor pairs in response to a select signal.

[0012]

In a high-speed sense circuit including a pair of grounded base transistors, a means for supplying a current to either one of the emitter or collector of the transistor pair in response to a select signal is provided to add a select function. Since the select circuit that was needed separately becomes unnecessary, only the delay time of the gate that configures the select circuit,
The memory system can be speeded up.

[0013]

1 is a diagram showing a first embodiment of the present invention. In this figure, a grounded base transistor Q is shown according to the present invention.
The select function is added to the high-speed sense circuit including 3 and Q4. This circuit is a non-select signal / SEL
Goes to the H level, the output signals O and / O are forced to the L level regardless of the data in the selected memory cell. Here, the switch SW is connected to the selected memory cell M.
When the data of C1 is "1" and the transistors Q2 and Q4 are on, it is connected to the left terminal as shown in the figure, the data of MC1 is "0", and the transistors Q1 and Q3 are on. In this case, it is configured to be connected to the right terminal, which is the opposite of the figure. In this way, when the data of MC1 is "0" and the transistors Q2 and Q4 are on, / SEL becomes H level and when the transistor Q7 is turned on, Q5 and Q3 are turned on, and eventually the output signal Both O and / O become L level. When the data of MC1 is "0" and the transistors Q1 and Q3 are on, / SEL becomes H level and the transistor Q
When 7 turns on, Q6 and Q4 turn on, and eventually the output signals O and / O both go low. Therefore, when the emitters of the output transistors Q9 and Q10 are further wirelessly connected to the emitters of the output transistors Q11 and Q12 of another sense circuit, respectively, they are selected (select signal SEL = H level, that is, non-select signal / SEL =).
Only the output signal of the sense circuit (to which the L level has been input) is output to O and / O. In this example, since the select function is added to the high-speed sense circuit including the grounded base transistor, the memory system can be speeded up by the amount of the select circuit that has been conventionally required.

FIG. 7 is a diagram showing a second embodiment of the present invention. In the figure, the select function is added to the high-speed sense circuit including the grounded base transistors Q3 and Q4 according to the present invention. This circuit is a non-select signal / SE
When L becomes H level, the output signals O and / O are forced to L level regardless of the data of the selected memory cell. Here, as in the case of FIG. 1, when the data of the selected memory cell MC1 is “1” and the transistors Q2 and Q4 are on, the switch SW is connected to the left terminal as shown in FIG. When the data of "0" is "0" and the transistors Q1 and Q3 are turned on, it is configured to be connected to the right terminal contrary to the figure. Therefore, when the data of MC1 is "1" and the transistors Q2 and Q4 are on, when / SEL goes high and the transistor Q7 turns on, the switch SW is connected to the left terminal and the output signal O, Both / O are at the L level. Also, when the data of MC1 is "0", the transistor Q
When 1 and Q3 are on, / SEL goes to H level and the transistor Q7 turns on, the switch SW is connected to the right terminal, and as a result, the output signals O and / O are both L level.
Become a level. Therefore, the output transistors Q9 and Q10
Of the output transistors Q11 and Q12 of the other sense circuits are selected by wire-OR, respectively, and are selected (select signal SEL = H level,
That is, only the output signal of the sense circuit (where the non-select signal / SEL = L level is input) is output to O and / O. In this example, since the select function is added to the high-speed sense circuit including the grounded base transistor, the memory system can be speeded up by the amount of the select circuit that has been conventionally required.

FIG. 8 is a diagram showing a third embodiment of the present invention. In the figure, the select function is added to the high-speed sense circuit including the grounded base transistors Q3 and Q4 according to the present invention. This circuit is a non-select signal / SE
When L becomes H level, the output signals O and / O are forced to L level regardless of the data of the selected memory cell. That is, when the data of the selected memory cell MC1 is "1" and the transistors Q2 and Q4 are on, / SEL becomes H level and the transistor Q7 is turned on, Q5 and Q3 are turned on, and eventually, Both the output signals O and / O become L level. Further, when the data of the selected memory cell MC1 is "0" and the transistors Q1 and Q3 are turned on, when / SEL becomes H level and the transistor Q7 is turned on, Q6 and Q4 are turned on, and eventually, Both the output signals O and / O become L level. Therefore, when the emitters of the output transistors Q9 and Q10 are further wirelessly connected to the emitters of the output transistors Q11 and Q12 of the other sense circuit, respectively, the selected signal (select signal SEL = H level, that is, non-select signal / SEL = L level is input). Only the output signal of the sense circuit) is output to O and / O. In this example, since the select function is added to the high-speed sense circuit including the grounded base transistor, the memory system can be speeded up by the amount of the select circuit that has been conventionally required. The diodes D3 and D4 shown in this example are added to prevent saturation of Q5 or Q6.

FIG. 9 is a diagram showing a fourth embodiment of the present invention. In the figure, the select function is added to the high-speed sense circuit including the grounded base transistors Q3 and Q4 according to the present invention. This circuit is a non-select signal / SE
When L becomes H level, the output signals O and / O are forced to L level regardless of the data of the selected memory cell. That is, when the data of the selected memory cell MC1 is "1" and the transistors Q2 and Q4 are on, / SEL goes to H level and the transistor Q7 turns on, so that Q5 turns on and, eventually, the output signal. Both O and / O become L level. Also, the selected memory cell MC
When the data of 1 is "0" and the transistors Q1 and Q3 are turned on, / SEL becomes H level and when the transistor Q7 is turned on, Q6 is turned on and, eventually, both output signals O and / O are L level. Become a level. Therefore, when the emitters of the output transistors Q9 and Q10 are further wired with the emitters of the output transistors Q11 and Q12 of the other sense circuit, respectively, the selected signal (select signal S
EL = H level, that is, non-select signal / SEL = L
Only the output signal of the sense circuit (when the level is input) is O,
Will be output to / O. In this example, since the select function is added to the high-speed sense circuit including the grounded base transistor, the memory system can be speeded up by the amount of the select circuit that has been conventionally required.

FIG. 10 is a diagram showing a fifth embodiment of the present invention. In the figure, the select function is added to the high-speed sense circuit including the grounded base transistors Q3 and Q4 according to the present invention. This circuit is a non-select signal / S
When EL goes to H level, the output signals O and / O are forced to L level no matter what the data in the selected memory cell is. That is, when the data of the selected memory cell MC1 is "1" and the transistors Q2 and Q4 are on, / SEL becomes H level and the transistor Q7 is turned on.
Is turned on, the diode D5 is turned on, and eventually the output signals O and / O both become L level. Further, when the data of the selected memory cell MC1 is "0", the transistor Q1
When / SEL is at H level and the transistor Q7 is on when Q3 and Q3 are on, the diode D6 is on and eventually the output signals O and / O both become L level. Therefore, the emitters of the output transistors Q9 and Q10 are connected to the output transistors Q11 and Q of another sense circuit.
When wirelessly connected to each of the 12 emitters, only the output signal of the selected sense circuit (the select signal SEL = H level, that is, the non-select signal / SEL = L level is input) is output to O and / O. Become. In this example, since the select function is added to the high-speed sense circuit including the grounded base transistor, the memory system can be speeded up by the amount of the select circuit that has been conventionally required.

Although the speeding up of reading of the memory system has been described above, the same argument holds for writing. That is, when a select function is added to the conventional write signal input circuit or write circuit, the write select circuit, which is conventionally required separately from the write signal input circuit or write circuit, is not required, and the writing speed of the memory system is increased. can do. This will be described below with reference to specific examples. Figure 11
FIG. 9 is a diagram showing an example of a conventional write signal input circuit.
In this circuit, write signal / WE is input, waveform shaping,
If necessary, level conversion is performed and the write control signal WC is output.

FIG. 12 is a diagram showing a sixth embodiment of the present invention. In this figure, a select function is added to the write signal input circuit according to the present invention. This circuit forcibly sets the write control signal WC to the H level when the non-select signal / SEL goes to the H level, regardless of the level of the write signal / WE. That is, when / SEL goes high, no matter what the level of the write signal / WE is, one of the transistors Q1 or Q4 is always turned on and the write control signal WC goes low.

In this example, since the select function is added to the write signal input circuit, the write select circuit, which is required separately from the write signal input circuit or the write circuit in the past, is not required, and the writing of the memory system can be performed. It can speed up.

FIG. 13 is a diagram showing an example of a conventional write circuit. In this circuit, when the write signal / WE is set to L level, the data "1" or the data "1" is stored in the memory cell (MC1 or MC2) selected by the bit line selection signal Y1 or Y2 in response to the data input signal D1 or / DI. "0" is written.

FIG. 14 is a diagram showing a seventh embodiment of the present invention. In this figure, a select function is added to the write circuit according to the present invention. In this circuit, non-select signal / S
When EL goes to H level, writing is not performed regardless of the level of write signal / WE. That is, / S
When EL becomes H level, the transistors Q1 and Q2 are always turned on regardless of the levels of the write signal / WE and the data input signals D1 and / DI, and the write operation is not performed. In this example, since the select function is added to the write circuit, the write select circuit, which has been required separately from the write signal input circuit or the write circuit in the past, is not necessary, and the writing speed of the memory system can be increased. it can.

If the sense circuit with select function or the write signal input circuit with write function or write circuit described above is used, the word configuration of the memory can be easily changed. This will be described below with reference to specific examples. 15 to 17 are views showing an eighth embodiment of the present invention. In FIG. 15, MEM1 to MEM4
Are memory of 2 ^ n words x 1 bit structure, A (1) to A (n) are address signals, and DI1 to DI
4 and DO1 to DO4 are data input and data output of MEM1 to MEM4, respectively. Further, SS is a sense circuit with a select function, WS is a write signal input circuit with a select function or a write circuit, and / SEL1
~ / SEL4 is a non-select signal. In FIG. 15, since the non-selection signals / SEL1 to / SEL4 are all at the L level, MEM1 to MEM4 are always selected.
Therefore, the total of MEM1 to MEM4 is 2 ^ n words x
It is a 4-bit memory.

Here, consider a case where the wiring connection of the memory of FIG. 15 is changed as shown in FIG. In Figure 16, / SEL
1- / SEL4 to (n + 1) th address signal A
A signal obtained by decoding (n + 1) is input, and DI1 and D
I2, DI3 and DI4, DO1 and DO2, DO3 and D
O4 is commonly connected. Therefore, MEM1 to ME
M4 is a memory having a structure of 2 ^ (n + 1) words × 2 bits as a whole.

Further, consider the case where the wiring connection of the memory of FIG. 15 is changed as shown in FIG. In Figure 17, / SEL
The signals obtained by decoding the (n + 1) th and (n + 2) th address signals A (n + 1) and A (n + 2) are input to 1- / SEL4, and DI1, DI2, DI3, DI4, DO1, DO2, DO3, and DO4. Are commonly connected. Therefore, the total of MEM1 to MEM4 is 2 ^ (n +
2) The memory has a word × 1 bit configuration.

As described above, when the sense circuit with select function or the write signal input circuit or write circuit with select function is used, the word configuration of the memory can be easily changed only by changing the wiring connection. it can. FIG. 18 is a diagram showing a ninth embodiment of the present invention. In FIG. 18, S is a sense circuit without a select function, or a sense circuit with a select function but a non-select signal (not shown in the figure) is in the select state at L level. WS is a write signal input circuit with a select function or a write circuit, and / SEL
1 to / SEL4 are non-selection signals for writing. In FIG. 18, the (n + 1) th and (n + 2) th write address signals A (n +) are added to / SEL1 to / SEL4.
1), A (n + 2) decoded signal is input, and D
I1 to DI4 are commonly connected. Therefore, MEM
1 to MEM4 as a whole, 2 ^ (n +
2) 2 ^ for reading with a word x 1 bit configuration
The memory has a structure of n words × 4 bits. That is, when a sense circuit with a select function or a write signal input circuit with a select function or a write circuit is used, it is possible to easily change the word configuration at the time of reading and writing.

FIG. 19 is a diagram showing a tenth embodiment of the present invention. In FIG. 19, W is a write signal input circuit or write circuit that does not have a select function or has a select function but is in a select state when a non-select signal (not shown in the figure) is L level. Also, S
S is a sense circuit with a select function, / SEL1 ~
/ SEL4 is a read non-select signal. FIG. 19
Then, in / SEL1 to / SEL4, (n + 1) th and (nth)
+2) th read address signal A (n + 1), A
A signal obtained by decoding (n + 2) is input, and DO1 to D
O4 is commonly connected. Therefore, MEM1 to ME
The M4 is a memory of 2 ^ (n + 2) words x 1 bit configuration for reading and 2 ^ n words x 4 bit configuration for writing. That is, when a sense circuit with a select function or a write signal input circuit with a select function or a write circuit is used, it is possible to easily change the word configuration at the time of reading and writing.

In the above, the sense circuit with a select function or the write signal input circuit with a select function or the write circuit has been described, but the same argument holds for the compare circuit. That is, when the compare function is added to the conventional sense circuit, the read operation of the memory system can be speeded up because the compare circuit which is conventionally required separately from the sense circuit is unnecessary. This will be described below with reference to specific examples. FIG. 20 is a diagram showing an example of a conventional compare circuit. It should be noted that in this figure, in addition to the compare circuit CMP, the memory cell MC and the sense circuit S are also shown. This sense circuit is the most commonly used circuit in ultra-high speed memory
An extremely high-speed operation is realized by including 3 and Q4. The compare circuit CMP outputs the output data (tag address in the above example) of the sense circuit S and the comparison data D,
/ D (tag address input from the CPU in the above example) is compared, and as a result, if they match, an L level signal is output, and if they do not match, an H level is output as a / HIT signal. That is, when the data of the selected memory cell MC1 is "1" and the transistors Q2 and Q4 are on, the comparison data is "1" (D = H level, / D = L).
Level), transistors Q10 and Q8 turn on,
The HIT signal becomes L level, and the comparison data is "0" (D
= L level, / D = H level), Q9 and Q5 are turned on, and the / HIT signal becomes H level. Further, when the data of the selected memory cell MC1 is “0”, the transistor Q
When 1 and Q3 are on, the comparison data is "1"
When (D = H level, / D = L level), the transistors Q10 and Q7 are turned on, the / HIT signal becomes H level, and the comparison data is "0" (D = L level, / D = H level). At this time, Q9 and Q6 are turned on, and the / HIT signal becomes L level. However, in this conventional example, no consideration was given to the speedup of the memory system. That is, as a result of examining the conventional example shown in FIG. 20, the present inventors have found that the delay time of the gates forming the compare circuit CMP impedes the speedup of the memory system.

Therefore, the present inventors examined the circuit shown in FIG. 21 prior to the present invention in order to reduce the delay time of the compare circuit. That is, FIG. 21 is a diagram showing another example of the compare circuit. In this circuit, Q101 and Q102 to which a compare signal is input are added to the bases of the differential amplifiers Q1 to Q4 that detect the voltage difference of the bit lines, and a series gate is provided to add a compare function to this part. There is. In this way, the read operation of the memory system can be speeded up by the fact that a compare circuit, which is conventionally required separately, is unnecessary. But,
When a series gate is used like this circuit, Q10
Since the number of vertically stacked stages of bipolar transistors increases by 1 and Q102, it is difficult to reduce the power supply voltage. Therefore, another object of the present invention is to propose a circuit that can reduce the delay time of the compare circuit and further reduce the power supply voltage.

FIG. 22 is a diagram showing an eleventh embodiment of the present invention. In the figure, the compare function is added to the high-speed sense circuit including the grounded base transistors Q3 and Q4 according to the present invention. The present circuit compares the data of the selected memory cell with the comparison data D and / D, and as a result, when they match, it outputs an L level signal, and when they do not match, it outputs an H level as a / HIT signal. That is, when the data of the selected memory cell MC1 is "1",
When the transistors Q2 and Q4 are on, when the comparison data is "1" (D = H level, / D = L level), the transistors Q5 and Q3 are turned on, and Q7 and Q4 are turned on.
Since the emitter of 8 is wired or, the / HIT signal becomes L level, and when the comparison data is "0" (D = L level, / D = H level), Q6 is turned on and Q3 is not turned on. The HIT signal becomes H level. In addition, when the data of the selected memory cell MC1 is "0" and the transistors Q1 and Q3 are turned on, when the comparison data is "1" (D = H level, / D = L level), the transistor Since Q5 turns on and Q4 does not turn on, / HI
The T signal becomes H level, and the comparison data is “0” (D = L
Level, / D = H level), Q6 and Q4 turn on,
The / HIT signal becomes L level. In this example, since the compare function is added to the high-speed sense circuit including the grounded base transistor, the memory circuit can be speeded up by the amount of the compare circuit which has been conventionally required. Furthermore, since no series gate is used, the power supply voltage can be reduced. As shown in this example, when the emitters of Q7 and Q8 are further wirelessly connected to the emitters of Q9 and Q10 which output the comparison result of another sense circuit, only when both comparison results are the same,
The HIT signal can be set to L level. The diodes D1 and D2 shown in this example are added to prevent saturation of Q3 or Q4 when Q1 and Q5 or Q2 and Q6 are simultaneously turned on.

FIG. 23 is a diagram showing a twelfth embodiment of the present invention. In the figure, the compare function is added to the high-speed sense circuit including the grounded base transistors Q3 and Q4 according to the present invention. The present circuit compares the data of the selected memory cell with the comparison data D and / D, and as a result, when they match, it outputs an L level signal, and when they do not match, it outputs an H level as a / HIT signal. That is, when the data of the selected memory cell MC1 is "1",
When the transistors Q2 and Q4 are turned on, when the comparison data is "1" (D = H level, / D = L level), the transistor Q5 is turned on, and the emitters of Q7 and Q8 are further wired. So / HIT signal is L
And the comparison data becomes “0” (D = L level, /
When D = H level), since Q6 is turned on, the / HIT signal becomes H level. Also, the selected memory cell MC
When the data of 1 is "0" and the transistors Q1 and Q3 are on, the transistor Q5 is on when the comparison data is "1" (D = H level, / D = L level). When the HIT signal becomes H level and the comparison data is "0" (D = L level, / D = H level), Q6
Is turned on, the / HIT signal becomes L level. In this example, since the compare function is added to the high-speed sense circuit including the grounded base transistor, the memory circuit can be speeded up by the amount of the compare circuit which has been conventionally required. Furthermore, since no series gate is used, the power supply voltage can be reduced. As shown in this example, when the emitters of Q7 and Q8 are further wirelessly ORed with the emitters of Q9 and Q10 which output the comparison result of another sense circuit, the / HIT signal is output only when the comparison results of both are the same. Can be set to L level. The diodes D1 and D2 shown in this example are
Q when 1 and Q5 or Q2 and Q6 are turned on at the same time
3 or Q4 is added to prevent saturation.

[0032]

As described above, when the sense circuit with a select function or the write signal input circuit with a select function or the write circuit according to the present invention is used, the select circuit which has been conventionally required becomes unnecessary. It is possible to speed up the memory system by the delay time of the gates constituting the memory. Also, the word configuration of the memory can be easily changed. Further, when the sense circuit with the compare function of the present invention is used, the compare circuit which has been conventionally required is not required, so that the speed of the memory system can be increased by the delay time of the gate which constitutes the compare circuit. Further, the power supply voltage can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a two-level memory system.

FIG. 3 is a diagram showing configurations of a main memory, a cache memory, and a table memory.

FIG. 4 is a diagram showing another configuration of a main memory, a cache memory, and a table memory.

FIG. 5 is a diagram showing a conventional example in which a cache memory and a table memory are configured by a semiconductor memory.

FIG. 6 is a diagram showing an example of a conventional select circuit.

FIG. 7 is a diagram showing a second embodiment of the present invention.

FIG. 8 is a diagram showing a third embodiment of the present invention.

FIG. 9 is a diagram showing a fourth embodiment of the present invention.

FIG. 10 is a diagram showing a fifth embodiment of the present invention.

FIG. 11 is a diagram showing an example of a conventional write signal input circuit.

FIG. 12 is a diagram showing a sixth embodiment of the present invention.

FIG. 13 is a diagram showing an example of a conventional write circuit.

FIG. 14 is a diagram showing a seventh embodiment of the present invention.

FIG. 15 is a diagram showing an eighth embodiment of the present invention.

FIG. 16 is a diagram showing an eighth embodiment of the present invention.

FIG. 17 is a diagram showing an eighth embodiment of the present invention.

FIG. 18 is a diagram showing a ninth embodiment of the present invention.

FIG. 19 is a diagram showing a tenth embodiment of the present invention.

FIG. 20 is a diagram showing an example of a conventional compare circuit.

FIG. 21 is a diagram showing another example of the compare circuit.

FIG. 22 is a diagram showing an eleventh embodiment of the present invention.

FIG. 23 is a diagram showing a twelfth embodiment of the present invention.

[Explanation of symbols]

CMA ... Cache memory cell array, TMA ... Table memory cell array, IA ... Index address, T
A ... Tag address, DEC ... Decoder, S ... Sense circuit, CMP ... Compare circuit, SEL ... Select circuit, D
ATA: data output, HIT: signal indicating hit or miss.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuo Kanaya 1-280 Higashi Koikekubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Yoji Ide 1-280 Higashi Koikeku, Kokubunji, Tokyo Hitachi Ltd. Central Research Laboratory (72) Inventor Kenichi Ohata, 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd. (72) Inventor Takeshi Kusu, 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd. (72) Inventor Hishita Keiichi 2326 Imai, Ome, Tokyo Metropolitan area Hitachi Device Development Center (72) Inventor Yasuhiro Fujimura 2326 Imai, Ome city Tokyo Metropolitan area Hitachi Device Development Center, Inc. (72) Inventor Akihisa Uchida Imai Tokyo Metropolitan City Address 2326 Company Hitachi Seisakusho device within the development center

Claims (7)

[Claims] 1. A sense circuit comprising a grounded-base transistor pair in which an emitter is connected to a common sense line, a constant voltage is applied to a base, and a collector outputs information. 2. A semiconductor memory comprising means for supplying a current to either one of the emitter or collector. 2. A means for supplying a current to either the emitter or the collector of a transistor pair in response to the select signal is connected to a current switch which switches in response to the select signal and an output terminal of the current switch, 2. The semiconductor memory according to claim 1, wherein the semiconductor memory includes a switching element that supplies a current to either the emitter or the collector of one of the transistor pairs according to the read data of the memory cell. 3. A plurality of said sense circuits are included, and their outputs are wide-ORed.
Alternatively, the semiconductor memory described in 2. 4. A semiconductor memory comprising a write signal input circuit or a write circuit having a select function. 5. A semiconductor memory including a sense circuit having a select function, a write signal input circuit having a select function, or a write circuit, wherein a signal obtained by decoding an address signal is used as a select signal. 6. A sense circuit configured to include a base-grounded transistor pair in which an emitter is connected to a common sense line, a constant voltage is applied to a base, and a collector outputs information to the sense circuit, in accordance with a compare signal. A semiconductor memory characterized in that a means for supplying a current to either one of the emitters or collectors is provided, and an OR logic is adopted by the collector output of the transistor pair. 7. Means for supplying current to either one of the emitter or collector of the transistor pair in response to the compare signal, the output being connected to the respective emitter or collector of the transistor pair and in response to the compare signal. 7. The semiconductor memory according to claim 6, comprising a current switch for switching.