JPH06103753A - Ferroelectric memory - Google Patents

Ferroelectric memory

Info

Publication number
JPH06103753A
JPH06103753A JP4246908A JP24690892A JPH06103753A JP H06103753 A JPH06103753 A JP H06103753A JP 4246908 A JP4246908 A JP 4246908A JP 24690892 A JP24690892 A JP 24690892A JP H06103753 A JPH06103753 A JP H06103753A
Authority
JP
Japan
Prior art keywords
voltage
ferroelectric
memory
thin film
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4246908A
Other languages
Japanese (ja)
Inventor
Takeshi Ito
毅 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Olympus Corp
Original Assignee
Olympus Optical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olympus Optical Co Ltd filed Critical Olympus Optical Co Ltd
Priority to JP4246908A priority Critical patent/JPH06103753A/en
Publication of JPH06103753A publication Critical patent/JPH06103753A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide the ferroelectric memory which can be actually produced as a device by specifying the current and voltage characteristics of a nonlinear resistor thin film forming a unit memory cell. CONSTITUTION:A thin film 16 having such current and voltage characteristics that the voltage at the time of passing 1 microampere current attains about 1 volt to 6 volts is used in the unit memory cell formed by laminating the ferroelectric thin film 14 and the nonlinear resistor thin film 16 and the ferroelectric memory constituted of striped electrodes 13, 17. As a result, the device which has no crosstalk between the memory cells and obviates the destruction of the memory state of the non-selected memory cells is attained. The ferroelectric memory which can be actually produced as the device, is thus obtd.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、画像ファイル、音声フ
ァイル等に適用可能な大容量固体不揮発性メモリに係
り、特に非選択セルの記憶状態を破壊しないで書き込み
読み出し可能な強誘電体メモリに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a large-capacity solid-state non-volatile memory applicable to image files, audio files, etc., and more particularly to a ferroelectric memory capable of writing and reading without destroying the memory state of non-selected cells. .

【0002】[0002]

【従来の技術】従来、図1に示すようなヒステリシス特
性を有する強誘電体材料の分極特性を利用した強誘電体
メモリが知られている。
2. Description of the Related Art Conventionally, there is known a ferroelectric memory utilizing the polarization characteristic of a ferroelectric material having a hysteresis characteristic as shown in FIG.

【0003】このヒステリシス特性によれば、強誘電体
材料に電圧Vを印加して、一度分極させると、電圧を
“0”に戻しても、図示A点またはC点で示される残留
分極値Prの状態を保持する。
According to this hysteresis characteristic, when a voltage V is applied to the ferroelectric material to polarize it once, even if the voltage is returned to "0", the remanent polarization value Pr shown at the point A or the point C is shown. Hold the state of.

【0004】従って、A点、又はC点で示される残留分
極値の各々にデジタル信号の“1”、“0”を対応させ
ることにより、メモリとして機能させることができる。
Therefore, by associating each of the remanent polarization values shown at the points A or C with the digital signals "1" and "0", it is possible to function as a memory.

【0005】このような特性を利用して、情報の記録を
行う場合は、抗電圧Vcを超える充分な大きさの電圧V
s(飽和電圧)を印加することによって、“0”が記録
され、また、抗電圧−Vcを超える充分な大きさの電圧
−Vs(飽和電圧)を印加し、“1”の状態を記録す
る。
When information is recorded using such characteristics, a voltage V of a sufficient magnitude exceeding the coercive voltage Vc is obtained.
By applying s (saturation voltage), “0” is recorded, and a sufficiently large voltage −Vs (saturation voltage) exceeding the coercive voltage −Vc is applied to record the state of “1”. .

【0006】この“1”の状態が記録されている場合
に、正の読み出しパルスVsを印加すると、分極状態が
点Aから点Cに転移する。この時、両分極差2Prに相
当する電荷が放出される。
When the positive read pulse Vs is applied when the state of "1" is recorded, the polarization state changes from the point A to the point C. At this time, charges corresponding to both polarization differences 2Pr are discharged.

【0007】一方、“0”の状態にあるときはC→B→
Cと分極状態が変化するので両分極差はゼロである。
On the other hand, in the state of "0", C → B →
Since the polarization state changes with C, both polarization differences are zero.

【0008】従って、正の電圧印加によって発生する電
荷量を検出することにより、記憶状態が“1”か“0”
かを読み出すことができる。
Therefore, the storage state is "1" or "0" by detecting the amount of charge generated by applying a positive voltage.
Can be read.

【0009】図2は前述した分極を利用した従来構造の
メモリ装置の具体的な構成を示す図である。
FIG. 2 is a diagram showing a specific structure of a memory device having a conventional structure using the above-mentioned polarization.

【0010】図2(a)は単純マトリックス構造、同図
(b)はアクティブマトリックス構造である。
FIG. 2A shows a simple matrix structure, and FIG. 2B shows an active matrix structure.

【0011】このメモリは、支持体となる基板1の面上
に互いに交差した一対のストライプ状の下部電極2、上
部電極3が配置され、この両電極2、3間に強誘電体薄
膜4が設けられて、上下ストライプ電極2、3の交差点
にメモリセルが構成される。
In this memory, a pair of stripe-shaped lower electrodes 2 and upper electrodes 3 which intersect each other are arranged on the surface of a substrate 1 serving as a support, and a ferroelectric thin film 4 is provided between the electrodes 2 and 3. A memory cell is provided at the intersection of the upper and lower stripe electrodes 2 and 3.

【0012】このようなメモリはストライプ電極2、3
に書き込み、または読み出し電圧を印加させるもので、
液晶表示装置にならって単純マトリックス方式と称され
ている。
Such a memory has stripe electrodes 2, 3
To write or read voltage to,
It is called a simple matrix system after the liquid crystal display device.

【0013】図2(c)はアクティブマトリックス構造
のメモリ装置の等価回路を示す。
FIG. 2C shows an equivalent circuit of a memory device having an active matrix structure.

【0014】図3に前記単純マトリックス構造が3×3
のマトリックスの場合を示す。
In FIG. 3, the simple matrix structure is 3 × 3.
The case of the matrix is shown.

【0015】図3(a)はセル配置図、同図(b)は等
価回路図である。
FIG. 3A is a cell layout diagram, and FIG. 3B is an equivalent circuit diagram.

【0016】今、図3(a)に示すA2端子にV/2、
B3端子に−V/2の電圧を各々印加すると、セルC3
2に電圧Vがかかる。
Now, V / 2 is applied to the A2 terminal shown in FIG.
When a voltage of -V / 2 is applied to the B3 terminal, the cell C3
The voltage V is applied to 2.

【0017】前記セルC32の記憶状態を読み出そうと
する時、C22、C21、C12、C33には2/5
V、C31、C11、C13、C23には1/5Vの電
圧が各々かかる。
When the storage state of the cell C32 is to be read out, 2/5 of C22, C21, C12 and C33 are stored.
A voltage of 1 / 5V is applied to each of V, C31, C11, C13, and C23.

【0018】なお、単純マトリックス構造がn×nの場
合、+1/2V、−1/2Vの電圧がかかるストライプ
ラインに関わる非選択セルには(n−1)/(2n−
1)・Vが、それ以外の非選択セルには1/(2n−
1)・Vの電圧が印加される。
When the simple matrix structure is n × n, (n-1) / (2n-) is applied to the non-selected cells related to the stripe lines to which the voltages of +1/2 V and -1/2 V are applied.
1) .V is 1 / (2n−) for the other non-selected cells.
1) The voltage of V is applied.

【0019】このような電圧の印加により、強誘電体メ
モリセルの分極が反転しないように、即ち、抗電圧以下
になるように印加電圧を設定したとしても、図1の点線
に示すように電圧除去後、分極状態はA→B′→A′と
減極することになる。
By applying such a voltage, even if the applied voltage is set so that the polarization of the ferroelectric memory cell is not reversed, that is, the applied voltage is equal to or lower than the coercive voltage, the voltage is as shown by the dotted line in FIG. After the removal, the polarization state is depolarized as A → B ′ → A ′.

【0020】この現象は強誘電体の極めて原理的なもの
であり、従って、図2(a)に示した様な従来の単純マ
トリックス構造強誘電体メモリでは非選択セルの分極状
態の減極、即ち記憶状態の破壊を避けることは不可能で
あった。
This phenomenon is extremely fundamental to the ferroelectric substance. Therefore, in the conventional simple matrix structure ferroelectric memory as shown in FIG. 2A, the polarization state of the non-selected cell is depolarized, That is, it was impossible to avoid destruction of the memory state.

【0021】[0021]

【発明が解決しようとする課題】そこで、本出願人らは
強誘電体薄膜と非線形抵抗体を有する抵抗体薄膜とを層
状構造に形成した単位メモリセルが、該メモリセルの
上、下で互いに直交するように形成されたX、Yストラ
イプ電極の各交点に配置され構成された単純マトリック
ス構造の強誘電体メモリを提案した(出願No.特願平
3−239696)。
Therefore, the present applicants propose that unit memory cells in which a ferroelectric thin film and a resistor thin film having a non-linear resistor are formed in a layered structure are arranged above and below each other. A ferroelectric memory having a simple matrix structure arranged and arranged at each intersection of X and Y stripe electrodes formed so as to be orthogonal to each other was proposed (Application No. Japanese Patent Application No. 3-239696).

【0022】これにおいて、前記単位メモリセルが、上
部ストライプ電極/非線形抵抗体/第二電極/PZT/
下部ストライプ電極/シリコン酸化膜/半導体基板の積
層構造からなる強誘電体メモリが提案されている。
In this case, the unit memory cell includes an upper stripe electrode / non-linear resistor / second electrode / PZT /
A ferroelectric memory having a laminated structure of a lower stripe electrode / silicon oxide film / semiconductor substrate has been proposed.

【0023】しかし、前記提案には基本構成については
述べられているが、非線形抵抗体の電流電圧特性につい
ては、具体的にはなっていなかった。
However, although the above-mentioned proposal describes the basic structure, the current-voltage characteristic of the non-linear resistor is not concrete.

【0024】すなわち、強誘電体薄膜と非線形電流電圧
特性を有する抵抗体薄膜とを層状構造になるように形成
された単位メモリセルが該メモリセルの上、下で互いに
直交するように形成されたX、Yストライプ電極の各交
点に配置され構成された単純マトリックス構造の強誘電
体メモリにおいて、前記単位メモリセルが、上部ストラ
イプ電極/非線形抵抗体/第二電極/PZT/下部スト
ライプ電極/シリコン酸化膜/半導体積層基板構造から
なることを特徴とする強誘電体メモリにおいて、前記非
線形抵抗体の特性が不明確であり、実際にデバイスを製
造することが出来なかった。
That is, a unit memory cell having a ferroelectric thin film and a resistor thin film having a non-linear current-voltage characteristic formed in a layered structure is formed above and below the memory cell so as to be orthogonal to each other. In a ferroelectric memory having a simple matrix structure arranged at each intersection of X and Y stripe electrodes, the unit memory cell includes an upper stripe electrode / non-linear resistor / second electrode / PZT / lower stripe electrode / silicon oxide. In a ferroelectric memory characterized by having a film / semiconductor laminated substrate structure, the characteristics of the non-linear resistor were unclear, and a device could not be actually manufactured.

【0025】そこで、本発明は上記強誘電体メモリに対
して、有効な非線形抵抗体の電流電圧特性を具体的にす
ることにより、実際にデバイスとして製造することが可
能な強誘電体メモリを提供することを目的とする。
Therefore, the present invention provides a ferroelectric memory which can be actually manufactured as a device by making the effective non-linear resistance current-voltage characteristics concrete for the above ferroelectric memory. The purpose is to do.

【0026】[0026]

【課題を解決するための手段及び作用】すなわち、本発
明では、電流電圧特性が明確な非線形抵抗体を積層した
単純マトリックス構造の強誘電体メモリを構成すること
により、メモリセル間のクロストークが無く、書き込み
/読み出し動作によって、非選択メモリセルの記憶状態
が破壊されないデバイスを実現する。
That is, in the present invention, crosstalk between memory cells is prevented by forming a ferroelectric memory having a simple matrix structure in which nonlinear resistors having clear current-voltage characteristics are laminated. In addition, a device in which the storage state of the non-selected memory cell is not destroyed by the write / read operation is realized.

【0027】先ず、本発明の強誘電体メモリ装置の概略
を説明する。
First, the outline of the ferroelectric memory device of the present invention will be described.

【0028】図4に非線形抵抗体薄膜の電流電圧特性を
示し、強誘電体薄膜に積層する非線形抵抗体の基本特性
とメモリセル特性との関係について述べる。
FIG. 4 shows the current-voltage characteristics of the nonlinear resistor thin film, and the relationship between the basic characteristics of the nonlinear resistor laminated on the ferroelectric thin film and the memory cell characteristics will be described.

【0029】この非線形抵抗体薄膜の電流電圧特性は正
負対称となるように構成される。
The current-voltage characteristics of this non-linear resistor thin film are configured so as to have positive / negative symmetry.

【0030】この非線形抵抗体は、例えば、層状構造が
中心対称な奇数のZnO−Bi2 3 の繰り返し構造、
もしくは多結晶質等で構成できる。
This non-linear resistor has, for example, an odd-numbered ZnO-Bi 2 O 3 repeating structure whose layered structure is centrally symmetric,
Alternatively, it can be composed of a polycrystalline material or the like.

【0031】そして、図5には前記非線形抵抗体の等価
回路の例として、直並列回路を示す。
Then, FIG. 5 shows a series-parallel circuit as an example of an equivalent circuit of the nonlinear resistor.

【0032】ここで、Rgは多結晶グレインの内部抵抗
であり、通常数オームである。Rb、Cbは粒界層の直
流抵抗成分、静電容量成分であり、それぞれ数百オー
ム、約500pF程度である。
Here, Rg is the internal resistance of the polycrystalline grain, which is usually several ohms. Rb and Cb are the direct current resistance component and the electrostatic capacitance component of the grain boundary layer, which are several hundred ohms and about 500 pF, respectively.

【0033】また、Ri、Ciはグレインと粒界の界面
直流抵抗成分、静電容量成分であり、それぞれ107
108 オーム、約100pF程度の値を持つ。
Further, Ri and Ci are the direct current resistance component and the capacitance component at the interface between the grain and the grain boundary, and each is 10 7 to
It has a value of about 10 8 ohms and about 100 pF.

【0034】この構成では、しきい値電圧Vth以下に
なると等価直流抵抗は非常に大きくなる。
In this structure, the equivalent DC resistance becomes extremely large when the voltage becomes lower than the threshold voltage Vth.

【0035】従って、合成インピーダンスは非線形抵抗
体の等価容量Cnlで決定される。
Therefore, the combined impedance is determined by the equivalent capacitance Cnl of the nonlinear resistor.

【0036】ここで、しきい値電圧とは非線形抵抗体が
off状態(高抵抗状態)からon状態(低抵抗状態)
にスイッチングするときの電圧のことである。
Here, the threshold voltage means that the nonlinear resistor is in the off state (high resistance state) to the on state (low resistance state).
It is the voltage when switching to.

【0037】次に、前記非線形抵抗体と強誘電体薄膜と
を積層した場合のメモリ動作について説明する。
Next, the memory operation when the nonlinear resistor and the ferroelectric thin film are laminated will be described.

【0038】この場合、印加電圧Vexを前記非線形抵
抗体と電気容量Cfeを持つ強誘電体薄膜とで分圧し、
強誘電体側にはCnl/(Cnl+Cfe)・Vexが
印加され、非線形抵抗体側にはCfe/(Cnl+Cf
e)・Vexが印加される。
In this case, the applied voltage Vex is divided by the non-linear resistor and the ferroelectric thin film having the electric capacitance Cfe,
Cnl / (Cnl + Cfe) · Vex is applied to the ferroelectric side, and Cfe / (Cnl + Cf) is applied to the non-linear resistor side.
e) -Vex is applied.

【0039】従って、Cnl+Cfeの値が小さいほ
ど、強誘電体側に加わる電圧は小さくなり、非破壊読み
出しが効果的に行えるようになる。
Therefore, the smaller the value of Cnl + Cfe, the smaller the voltage applied to the ferroelectric side, and the more effective non-destructive reading can be performed.

【0040】一方、外部電圧が増加し、非線形抵抗体側
に加わる電圧Cfe/(Cnl+Cfe)・Vexがし
きい値電圧Vthを超えると急激に非線形抵抗体の抵抗
が低下し、それと同時に強誘電体側に加わる電圧Zfe
/(Zfe+Znl)・Vexが大きくなり、前記強誘
電体の抗電圧Vc以上になった時、分極反転する。
On the other hand, when the external voltage increases and the voltage Cfe / (Cnl + Cfe) · Vex applied to the side of the non-linear resistor exceeds the threshold voltage Vth, the resistance of the non-linear resistor decreases rapidly, and at the same time, the resistance of the non-linear resistor increases. Applied voltage Zfe
When / (Zfe + Znl) · Vex becomes large and exceeds the coercive voltage Vc of the ferroelectric substance, the polarization is inverted.

【0041】従って、非選択セルの強誘電体に電圧が印
加されなくするためには、非線形抵抗体のオフ状態にお
いて、その電気容量が小さいほど良い。
Therefore, in order to prevent the voltage from being applied to the ferroelectric substance of the non-selected cell, it is better that the electric capacitance is smaller in the OFF state of the nonlinear resistor.

【0042】[0042]

【実施例】先ず、本発明の強誘電体メモリ装置の構造に
ついて説明する。
First, the structure of a ferroelectric memory device of the present invention will be described.

【0043】図9は本発明の強誘電体メモリ装置の単位
メモリセルである。
FIG. 9 shows a unit memory cell of the ferroelectric memory device of the present invention.

【0044】この単位メモリセルの構造は、上部より上
部ストライプ電極17/非線形抵抗体層16/第2電極
15/強誘電体層14/下部ストライプ電極13/シリ
コン基板表面酸化層12/シリコン基板11となってい
る。
The structure of this unit memory cell is such that, from the top, the upper stripe electrode 17 / nonlinear resistor layer 16 / second electrode 15 / ferroelectric layer 14 / lower stripe electrode 13 / silicon substrate surface oxide layer 12 / silicon substrate 11 are arranged. Has become.

【0045】次に、どのような電流電圧特性を有する非
線形抵抗体が最適かを説明する。
Next, what kind of current-voltage characteristics the non-linear resistor has is optimum will be described.

【0046】図6は幾種かの非線形抵抗体を強誘電体単
一セルに直列に接続した場合のヒステリシス曲線の例で
あり、図示内側及び外側の曲線はそれぞれ2.5Vと5
Vの印加電圧単位での測定結果である。すなわち、測定
に際しては、印加電圧を2.5Vと5Vとで行ったもの
で、これは非選択セルにかかる最大の電圧は、選択セル
にかかる電圧の1/2となるためである。
FIG. 6 is an example of a hysteresis curve when several types of non-linear resistors are connected in series to a ferroelectric single cell. The inner and outer curves in the figure are 2.5 V and 5 respectively.
It is a measurement result in the unit of applied voltage of V. That is, the measurement was performed with applied voltages of 2.5 V and 5 V, because the maximum voltage applied to the non-selected cells is ½ of the voltage applied to the selected cells.

【0047】図6(a)は非線形抵抗体を有しない場合
のヒステリシス曲線である。
FIG. 6A is a hysteresis curve in the case of not having a non-linear resistor.

【0048】図のように2.5Vの電圧でもその分極状
態が大きく変化している。
As shown in the figure, the polarization state changes greatly even at a voltage of 2.5V.

【0049】即ち、これは書き込み/読み出し動作によ
って、記憶状態が破壊されていることを示している。
That is, this indicates that the memory state is destroyed by the write / read operation.

【0050】図6(b)は0.9Vのしきい値電圧(V
th)を有する非線形抵抗体を接続した場合のヒステリ
シス曲線である。
FIG. 6B shows a threshold voltage (V of 0.9V).
is a hysteresis curve in the case of connecting a non-linear resistor having th).

【0051】これは非線形抵抗体のVthが小さすぎる
場合であり、2.5Vの印加電圧でもその分極状態が大
きく変化している。
This is the case where the Vth of the non-linear resistor is too small, and the polarization state of the non-linear resistor changes greatly even with an applied voltage of 2.5V.

【0052】図6(c)は2.76VのVthを有する
非線形抵抗体を接続した場合である。
FIG. 6C shows a case where a non-linear resistor having a Vth of 2.76 V is connected.

【0053】これは、非線形抵抗体のVthが適正な値
の場合であり、印加電圧5Vのときは十分な分極を示し
ているが、印加電圧2.5Vのときはほとんど分極状態
を変化させてない。
This is a case where the Vth of the non-linear resistor has an appropriate value and shows sufficient polarization when the applied voltage is 5 V, but when the applied voltage is 2.5 V, the polarization state is almost changed. Absent.

【0054】図6(d)は6.2VのVthを有する非
線形抵抗体を接続した場合のヒステリシス曲線である。
FIG. 6D is a hysteresis curve when a non-linear resistor having a Vth of 6.2 V is connected.

【0055】この場合はVthが大きすぎる場合で、印
加電圧5Vの場合でもその分極状態をほとんど変化させ
てない。
In this case, Vth is too large, and the polarization state is hardly changed even when the applied voltage is 5V.

【0056】上記測定は図7に示す測定回路を用いて行
った。
The above measurement was performed using the measurement circuit shown in FIG.

【0057】上記測定結果をグラフに表したものを図8
に示す。
A graphical representation of the above measurement results is shown in FIG.
Shown in.

【0058】横軸は測定に用いた非線形抵抗体としての
ダイオードの1μAでのしきい値電圧Vthであり、縦
軸は分極2Prの、印加電圧2.5Vと5Vでの測定値
の比であり、単位は%である。
The horizontal axis represents the threshold voltage Vth at 1 μA of the diode as the non-linear resistor used for the measurement, and the vertical axis represents the ratio of the measured values of the polarization 2Pr at the applied voltages of 2.5V and 5V. , The unit is%.

【0059】この図に於て、縦軸の数値が小さいものほ
ど5Vの印加電圧に比べて2.5Vの印加電圧でその分
極を変化させていないことになり、従って、より非破壊
読み出し的であると言える。この図より、1μAの電流
を導通するのに要する電圧が約1〜6Vのしきい値電圧
Vthを有する非線形抵抗体が最も有効であることが分
かる。
In this figure, the smaller the value on the vertical axis is, the more the polarization is not changed by the applied voltage of 2.5 V as compared with the applied voltage of 5 V. Therefore, it is more non-destructive read-out. It can be said that there is. From this figure, it can be seen that the nonlinear resistor having the threshold voltage Vth of about 1 to 6 V required to conduct the current of 1 μA is most effective.

【0060】[0060]

【発明の効果】以上詳述したように本発明によれば、電
圧電流特性が具体化された非線形抵抗体薄膜を用いるこ
とにより、非選択セルの内容を破壊することなく書き込
み/読み出し可能な強誘電体メモリデバイスとして実際
に実現可能な強誘電体メモリを提供することができる。
As described above in detail, according to the present invention, by using the non-linear resistor thin film in which the voltage-current characteristic is embodied, the write / read operation can be performed without destroying the contents of the non-selected cells. It is possible to provide a ferroelectric memory that can be actually realized as a dielectric memory device.

【図面の簡単な説明】[Brief description of drawings]

【図1】強誘電体材料の分極(ヒステリシス)特性を示
す図
FIG. 1 is a diagram showing polarization (hysteresis) characteristics of a ferroelectric material.

【図2】従来の強誘電体のメモリ構造と等価回路とを示
す図
FIG. 2 is a diagram showing a conventional ferroelectric memory structure and an equivalent circuit.

【図3】3×3単純マトリックス構造のセル配置図と等
価回路を示す図
FIG. 3 is a diagram showing a cell layout diagram of a 3 × 3 simple matrix structure and an equivalent circuit.

【図4】本発明に用いる非線形抵抗体薄膜の電流電圧特
性を示す図
FIG. 4 is a diagram showing current-voltage characteristics of a nonlinear resistor thin film used in the present invention.

【図5】図4の非線形抵抗体の等価回路として直並列回
路を示す図
5 is a diagram showing a serial-parallel circuit as an equivalent circuit of the non-linear resistor of FIG.

【図6】強誘電体単一セルに直列に接続する非線形抵抗
体の種別を変えたときのヒステリシス測定結果を示す図
FIG. 6 is a diagram showing hysteresis measurement results when the type of a nonlinear resistor connected in series to a ferroelectric single cell is changed.

【図7】図6に用いる測定回路を示す図7 is a diagram showing a measurement circuit used in FIG.

【図8】図6の測定結果を表したグラフを示す図8 is a diagram showing a graph showing the measurement results of FIG.

【図9】本発明による強誘電体メモリの単位メモリセル
を示す図
FIG. 9 is a diagram showing a unit memory cell of a ferroelectric memory according to the present invention.

【符号の説明】[Explanation of symbols]

11 シリコン基板 12 シリコン基板表面酸化膜 13 下部ストライプ電極 14 強誘電体層 15 第2電極 16 非線形抵抗体層 17 上部ストライプ電極 11 Silicon Substrate 12 Silicon Substrate Surface Oxide Film 13 Lower Stripe Electrode 14 Ferroelectric Layer 15 Second Electrode 16 Nonlinear Resistor Layer 17 Upper Stripe Electrode

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 強誘電体薄膜と非線形電流電圧特性を有
する抵抗体薄膜とを層状構造に形成した単位メモリセル
が該メモリセルの上、下で互いに直交するように形成さ
れたX、Yストライプ電極の各交点に配置されることに
より、構成された単純マトリックス構造の強誘電体メモ
リにおいて、 前記非線形電流電圧特性を有する抵抗体薄膜が、1マイ
クロアンペアの電流を流したときの電圧が約1ボルトか
ら6ボルトとなる様な電流電圧特性を有することを特徴
とした強誘電体メモリ。
1. An X, Y stripe in which unit memory cells in which a ferroelectric thin film and a resistor thin film having a non-linear current-voltage characteristic are formed in a layered structure are formed so as to be orthogonal to each other above and below the memory cell. In the ferroelectric memory having the simple matrix structure configured by being arranged at each intersection of the electrodes, the resistance thin film having the non-linear current-voltage characteristic has a voltage of about 1 when a current of 1 microamperes flows. A ferroelectric memory characterized by having a current-voltage characteristic such that the voltage changes from 6 V to 6 V.
JP4246908A 1992-09-16 1992-09-16 Ferroelectric memory Pending JPH06103753A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4246908A JPH06103753A (en) 1992-09-16 1992-09-16 Ferroelectric memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4246908A JPH06103753A (en) 1992-09-16 1992-09-16 Ferroelectric memory

Publications (1)

Publication Number Publication Date
JPH06103753A true JPH06103753A (en) 1994-04-15

Family

ID=17155542

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4246908A Pending JPH06103753A (en) 1992-09-16 1992-09-16 Ferroelectric memory

Country Status (1)

Country Link
JP (1) JPH06103753A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100430656B1 (en) * 2000-07-27 2004-05-10 미쓰비시덴키 가부시키가이샤 Nonvolatile semiconductor memory device
US7190339B2 (en) 2003-01-17 2007-03-13 Seiko Epson Corporation Ferroelectric memory device and display drive IC

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100430656B1 (en) * 2000-07-27 2004-05-10 미쓰비시덴키 가부시키가이샤 Nonvolatile semiconductor memory device
US7190339B2 (en) 2003-01-17 2007-03-13 Seiko Epson Corporation Ferroelectric memory device and display drive IC

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