JPH06103164A - Access control method/device for interleave memory circuit - Google Patents

Abstract

PURPOSE:To attain the transfer of data with high efficiency and to improve the access efficiency by preventing such a case where a shorter access cycle time is affected by a longer access cycle time. CONSTITUTION:A cycle time comparator 4 compares the cycle time obtained by a 1st cycle time measuring means 2 with the cycle time obtained by a 2nd cycle time measuring means 3. Thus a port of a short cycle time is identified. The outrun control means 5 and 6 stop the progress of addresses of the ports having the long cycle times and advance the progress of addresses of the ports having the short cycle times when the progresses are set in the same direction between the ports of the long and short cycle times and when the progress of the bank address of the port of the short cycle time catches up to the progress of the bank address of the port of the long cycle time. The progress of address at the port of the short cycle time is advanced. Then the stop of progress is canceled for the address of the port of the long cycle time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for controlling access to an interleaved memory circuit, and more particularly to an address of a port having a short access cycle time when a plurality of ports access the interleaved memory circuit at the same time. The present invention relates to a method and apparatus for controlling access to an interleaved memory circuit, which controls so that the progress of a memory overtakes the progress of an address of a port having a long cycle time.

[0002]

2. Description of the Related Art FIG. 4 shows the configuration of a conventional interleaved memory circuit. The interleaved memory circuit includes a memory circuit 7 in bank # 0, a memory circuit 8 in bank # 1,
The memory circuit 9 of bank # 2 and the memory circuit 10 of bank # 3 are divided into four banks, each of which has (..., 08, 1
2, 16,…), (…, 09, 13, 17,…), (…, 10, 1
Addresses of 4, 18, ...), (..., 11, 15, 19, ...) are assigned.

Control unit M of each memory circuit 7, 8, 9, 10
CC has two ports, and system bus SB
It is possible to access from both the side and the local bus LB side at the same time.

When two ports of the memory circuit of the same bank are accessed at the same time, the control section MMC accepts the later-arriving access after finishing the processing of the first-arriving access.

[0005]

FIG. 5 shows address progression in the interleaved memory circuit shown in FIG. The access from the system bus SB side has a short cycle time and the address progresses quickly. On the other hand, the cycle time of access from the local bus LB side is long and the progress of the address is slow.

As shown in FIG. 5, the address on the system bus SB side becomes "12" at time t2, and the local bus L
Catch up with the address "12" on the B side, but the local bus L
Since the B side is the first-come-first-served basis, the access from the system bus SB side is not accepted and the system enters the waiting state. Then, after the processing for the address "12" on the local bus LB side is completed, at time t3, the address "12" on the system bus SB side is generated.
The process for is started.

When the processing for the address "12" on the side of the system bus SB is completed and an attempt is made to access the address "13", the processing for the address "13" on the side of the local bus LB is performed first. Processing for the address "13" on the SB side cannot be accepted. Then, the address "1" on the local bus LB side
After the processing for "3" is completed, processing for address "13" on the system bus SB side is performed at time t5.

In this way, the progress of the address at the port with the shorter cycle time is the same as the progress of the address at the port with the longer cycle time, and the progress of the address at the port with the shorter cycle time is the same. Has caught up with the progress of the address at the port having the longer cycle time, the progress of the address having the shorter cycle time is hindered by the progress of the address having the longer cycle time, resulting in a problem that the access efficiency is lowered. In the description of FIG. 5, an example in which the address on the system bus SB side matches the address on the local bus LB side has been described, but even if the addresses do not match, the above problem occurs when the bank address catches up. .

SUMMARY OF THE INVENTION An object of the present invention is to provide an access control method and apparatus capable of solving the above-mentioned problem of lowered access efficiency.

[0010]

According to a first aspect of the present invention, when a plurality of ports of an interleaved memory circuit are accessed at the same time, the progress of the address at the port with a short cycle time and the address at the port with a long cycle time are performed. When the progress of the bank address in the port with the short cycle time catches up with the progress of the bank address in the port with the long cycle time, the progress of the address in the port with the long cycle time is stopped. Advance the address progress on the port with a short cycle time, then
Provided is an access control method for an interleaved memory circuit, which is characterized in that the progress stop of an address in a port having a long cycle time is released.

According to a second aspect of the present invention, a first cycle time measuring means for measuring a first cycle time for accessing a first port of an interleaved memory circuit and a second port of the interleaved memory circuit are provided. Second cycle time measuring means for measuring a second cycle time to be accessed, and cycle time comparison for comparing the first cycle time and the second cycle time to identify a port having a short cycle time and a port having a long cycle time. Means and
The progress of an address on a port with a short cycle time is the same as the progress of an address on a port with a long cycle time, and the progress of a bank address on a port with a short cycle time is the progress of a bank address on a port with a long cycle time. When catching up, the overtaking control means for stopping the progress of the address of the port with the long cycle time to advance the progress of the address of the port with the short cycle time, and then canceling the stop of the progress of the address of the port with the long cycle time. And an access control device for an interleaved memory circuit.

In the above structure, the bank address means an address portion designating a bank of the interleaved memory circuit.

[0013]

According to the method and apparatus for controlling access to the interleaved memory circuit of the present invention, when the progress of the bank address at the port with the shorter cycle time catches up with the progress of the bank address at the port with the longer cycle time. , The progress of the address on the port with the shorter cycle time is forced to stop, and the progress of the address on the port with the shorter cycle time is overtaken. No longer obstructing the progress of addresses on the long side port,
Access efficiency is improved.

[0014]

The present invention will be described in more detail with reference to the embodiments shown in the drawings. The present invention is not limited to this. FIG. 1 is a block diagram of an interleaved memory circuit including an access control device 1 according to an embodiment of the present invention. System bus SB, local bus LB,
Memory circuit 7 of bank # 0, memory 8 of bank # 1, memory circuit 9 of bank # 2, memory circuit 10 of bank # 3
Are components similar to the conventional components.

On the local bus LB, for example, CT or MR
In an image diagnostic apparatus such as I, an observation apparatus such as a CT scanner or a magnet assembly is connected, and an image reconstruction calculation apparatus is connected to the system bus SB. Then, the data acquired by the observation device is transferred to the local bus LB.
The data is stored in the interleaved memory circuit via, and the image reconstruction arithmetic unit takes out the data stored in the interleaved memory circuit via the system bus SB to perform the image reconstruction arithmetic operation.

The access control device 1 includes a first cycle time measuring circuit 2 and a second cycle time measuring circuit 3.
And a cycle time comparison circuit 4, an interleave monitoring circuit 5, and an interleave arbitration circuit 6.

The first cycle time measuring circuit 2 monitors the control signal of the system bus SB and measures the time interval of access to the memory circuits 7 to 10 with a timer.

The second cycle time measuring circuit monitors the control signal of the local bus LB, and the memory circuit 7
The time interval of access to 10 is measured by a timer.

The cycle time comparing circuit 4 compares the cycle time obtained by the first cycle time measuring circuit 2 with the cycle time obtained by the second cycle time measuring circuit 3, and the system bus SB side or the local bus. It is determined which of the LB side has the shorter cycle time.

The interleave monitoring circuit 5 monitors the address on the system bus SB side and the address on the local bus LB side, and determines whether or not the address progresses in the same direction. Also, the bank-designated portions of the addresses are compared to determine whether the bank addresses match.

The interleave arbitration circuit 6 uses the control signal on the system bus SB side, the control signal on the local bus LB side, the output signal from the cycle time comparison circuit 4, and the output signal from the interleave monitoring circuit 5. , Outputs a wait command to the memory circuits 7 to 10, and cancels the wait command.

Next, the operation of the access control device 1 will be described with reference to FIG. First, the interleave arbitration circuit 6
Examines the control signal to determine whether or not there is simultaneous access from the system bus SB side and the local bus LB side (S1).

If there is no access from both, the wait command to the memory circuits 7 to 10 is canceled (S2). In this state, the operation of the memory circuits 7 to 10 is the same as the conventional operation. If there is access from both sides, it is judged from the output signal of the interleave monitoring circuit 5 whether or not the advancing directions of the addresses are the same direction (S3).

If the addresses are not in the same direction, the process proceeds to step S2. If the addresses proceed in the same direction, it is determined from the output signal of the cycle time comparison circuit 4 whether or not the cycle time on the system bus SB side is short (S4). If the cycle time on the system bus SB side is short, the process proceeds to step S5. If the cycle time on the local bus LB side is short, the process proceeds to step S8.

In step S5, it is determined from the output signal of the interleave monitoring circuit 5 whether or not the bank address on the system bus SB side matches the bank address on the local bus LB side. If they match, a wait command for access on the local bus LB side is output to the memory circuit (S6). If they do not match, the wait command for access on the local bus LB side is canceled (S7).

On the other hand, in step S8, the system bus S
It is determined whether the bank address on the B side and the bank address on the local bus LB side match. If they match, a wait command for access on the system bus SB side is output to the memory circuit (S9). If they do not match, the wait command for access on the system bus SB side is canceled (S10). The above steps S1 to S10 are repeated.

FIG. 3 is a conceptual diagram for explaining the result of control by the access control device 1. At time t1, the system bus SB side accesses the address “08” and the local bus LB side accesses the access “11”. The address "08" is assigned to the memory circuit 7 of bank # 0, for example, and the address "11" is assigned to bank # 0, for example.
No. 3 memory circuit 10 is allocated, and simultaneous access is possible. The cycle time of access on the system bus SB side is shorter than the cycle time of access on the local bus LB side, and at time t2, the address on the system bus SB side becomes "12" and catches up with the address "12" on the local bus LB side. At this time, the address "1
The control unit MMC of the memory circuit 7 of the bank # 0 to which "2" is allocated performs processing on the side of the local bus LB that has been accessed first by the first-come-first-served basis.
B side access is not accepted.

On the other hand, in the access control device 1, the process proceeds to steps S1, S3, S4 and S5 in FIG.
Since the bank address on the B side and the bank address on the local bus LB side match, the process proceeds to step S6, and a wait command is issued to the memory circuit 7 for the local bus LB side. As a result, the control unit MMC of the memory circuit 7
Holds the output of the completion signal to the local bus LB side after the processing for the address "12" on the local bus LB side is completed. Therefore, the address on the local bus LB side remains the address "12" even after the processing is completed. On the other hand, since the process for the address "12" on the local bus LB side is actually completed, the process for the address "12" on the system bus SB side is performed at time t4.

Next, in the memory circuit 7, when the processing for the address "12" on the system bus SB side is completed, the control section MMC outputs a completion signal to the system bus SB side. Therefore, the system bus SB side advances the address to "13" to access the memory circuit 8 of bank # 1.

On the other hand, in the access control circuit 1, the process proceeds to steps S1, S3, S4 and S5, but the bank address on the system bus SB side becomes "# 1" and the local bus LB
Since the bank address on the side remains "# 0", the process proceeds to step S7, and the wait command for the local bus LB side output to the memory circuit 7 is canceled. As a result, the control unit MMC of the memory circuit 7 outputs the pending completion signal to the local bus LB side. Therefore, at time t5, the address on the local bus LB side is also "1".
3 ”.

In the memory circuit 8, however, the address "13" on the system bus SB side is processed first, so that the address "13" on the local bus LB side is processed.
The processing for is delayed. That is, the system bus S
The B side has passed the local bus LB side.

When the process for the address "13" on the system bus SB side is completed in the memory circuit 8, the address on the system bus SB side advances to "14". That is, the memory circuit 9 of bank # 2 is accessed. On the other hand, in the memory circuit 8, the process for the address "13" on the local bus LB side is performed.

As described above, the access on the short cycle time side overtakes the access on the long cycle time side, so that the former is prevented from being hindered by the latter and the access efficiency is prevented from decreasing, and both are highly efficient. You can access it at.

[0034]

According to the method and apparatus for controlling access to an interleaved memory circuit of the present invention, when there are a plurality of ports for accessing the interleaved memory circuit,
One with a shorter access cycle time is no longer capped by one with a longer access cycle time,
It enables highly efficient data transfer.

[Brief description of drawings]

FIG. 1 is a block diagram of an interleaved memory circuit including an embodiment of an access control device of the present invention.

FIG. 2 is a flowchart showing the operation of the access control device shown in FIG.

FIG. 3 is an explanatory diagram of passing of address progress.

FIG. 4 is a block diagram of an example of a conventional interleaved memory circuit.

FIG. 5 is an explanatory diagram of conventional address progression.

[Explanation of symbols]

 1 Access Control Device 2 First Cycle Time Measuring Circuit 3 Second Cycle Time Measuring Circuit 4 Cycle Time Comparison Circuit 5 Interleave Monitoring Circuit 6 Interleave Arbitration Circuit 7 Memory Circuit 8 Memory Circuit 9 Memory Circuit 10 Memory Circuit MCC Memory Control Circuit SB System bus LB Local bus

Claims (2)

[Claims] 1. When a plurality of ports of an interleaved memory circuit are accessed at the same time, the progress of an address at a port with a short cycle time and the progress of an address at a port with a long cycle time are in the same direction and have a short cycle time. When the progress of the bank address in the port catches up with the progress of the bank address in the port with a long cycle time, the progress of the address in the port with a long cycle time is stopped and the progress of the address in the port with a short cycle time is advanced,
Thereafter, a method of controlling access to an interleaved memory circuit is characterized in that the progress stop of an address at a port having a long cycle time is released. 2. A first cycle for measuring a first cycle time of accessing a first port of an interleaved memory circuit.
Cycle time measuring means, second cycle time measuring means for measuring a second cycle time for accessing the second port of the interleaved memory circuit, and the first
Cycle time comparing means for identifying a port with a short cycle time and a port with a long cycle time by comparing the cycle time of the second cycle time with the second cycle time; When the progress of the bank address in the port with the same cycle and the short cycle time catches up with the progress of the bank address in the port with the long cycle time, the progress of the address in the port with the long cycle time is stopped. An access control device for an interleaved memory circuit, comprising: an overtaking control unit for advancing the progress of an address in a port having a short cycle time and then canceling the stop of the progress of an address in a port having a long cycle time.