JPH06102739A - High voltage outputting device - Google Patents

Abstract

PURPOSE:To attain the reduction of a device cost and the miniaturization of the device, to perform a switching of the high voltage and to output an extremely high voltage by connecting plural high pressure-proof circuits in series. CONSTITUTION:Plural photo MOS and FET relays 10a-10d and 11a-11d provided with outputs MOS and FET 13 provided with a prescribed pressure-proof are connected in series, and a control signal is outputted to an LED 12 in the photo MOS and FET relays 10a-10d, or 11a-11d through an inverter 16, or 17 so as to perform the ON/OFF control of the outputs MOS and FET 13, and a circuit for outputting a high voltage + HV, or HV to be supplied to a high voltage supply terminal 1, or 2 from an output terminal OUT is formed, and then, the high voltage outputting device provided with the high pressure-proof is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high voltage output device,
In particular, it relates to a high voltage output device capable of supplying an extremely high voltage.

[0002]

2. Description of the Related Art A high voltage output device is used, for example, as a bias power source for a recording electrode of an electrostatic recording device or for supplying a high voltage to a charger or a cleaner of an electrophotographic printer.

FIG. 6 shows a circuit diagram of a conventional high voltage output device as described above. In the figure, when a positive (hereinafter referred to as +) Vcc (high signal) is applied to one input INH and the other input INL is set to 0V (low signal), the output of the buffer 1 becomes a high level (Vcc). The output of the buffer 2 becomes low level. Since the other end of the light emitting diode 3'in the photocoupler 3 to which the output of the buffer 1 is supplied is connected to the power supply terminal of the voltage VCC, the light emitting diode 3'does not emit light and the output transistor of the photocoupler 3 3 "is turned off. Therefore, power MOS FET4
Is applied to the output voltage of the DC-DC converter 5 having its input and output insulated between its gate (G) and source (S),
The power MOSFET 4 turns on. On the other hand, buffer 2
Since the output of is at the low level as described above, the light emitting diode 6'in the photocoupler 6 emits light and the photocoupler 6
The output transistor 6 "of the power MOS.FET 7 turns on. Therefore, the voltage between the gate (G) and the source (S) of the power MOS.FET 7 becomes 0 V, and the power MOS.FET 7 turns off. From the above, a high signal is input to the input INH. When applying and applying a low signal to the input INL, only the power MOS • FET 4 is turned on, and the voltage + HV is output to the output (OUT) of the high voltage output circuit via the resistor R1.

On the other hand, contrary to the above, when a low signal is applied to the input INH and a high signal is applied to the input INL, the output of the buffer 1 is 0V and the output of the buffer 2 is + Vcc.
Therefore, contrary to the above, the output transistor 6 ″ of the photocoupler 6 is turned off and only the power MOS • FET 7 is turned on. Therefore, at this time, the output (OU) of the high voltage output circuit is reached.
The voltage minus HV is output to T) via the resistor R2.

Therefore, as described above, the conventional high-voltage output circuit applies a high signal or a low signal to the input INH and the input INL, so that the power MOS of a single structure is formed.
・ High voltage + HV supplied to FET4, or high voltage minus H supplied to power MOS / FET7 of single configuration
V has been switched and supplied from the output OUT to a device requiring a high voltage.

[0006]

However, although the conventional high voltage output device uses the DC-DC converters 5 and 8, the DC-DC converter is expensive and causes an increase in the cost of the device, and also has a shape. Larger circuit size.

Further, when the high voltage is supplied from the high voltage output circuit to a device requiring an extremely high voltage, the conventional high voltage output circuit uses a single power MOS / FET 4, 7. It is not possible to switch from very high voltage. That is, the withstand voltage of the MOS • FET has a limit, and it has been impossible to drive a large voltage.

[0008]

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, the present invention reduces the cost of the device and downsizes it, and by connecting a plurality of high-voltage switching elements in series, high-voltage switching is performed and an extremely high voltage is output. It is an object of the present invention to provide a high voltage output device that enables the above.

[0009]

According to the present invention, the above object includes a light emitting element which operates according to an input signal, a light receiving element which operates by receiving light from the light emitting element, and a switching means which is driven based on the operation of the light receiving element. A photo relay configured as one,
A plurality of first and second opening / closing means in which the photorelays are connected in series by connecting a plurality of the switching means in series and a terminal of the switching means of the first and second opening / closing means And a resistance element of
A first high voltage is connected to one of the other sides of the terminals, a second high voltage is connected to the other of the other sides of the terminals, and a first high voltage is connected to one end of the light emitting element of the first opening / closing means. By inputting a second input signal to the one end of the light emitting element of the second opening / closing means, the first high voltage or the second high voltage is input to the first and second inputs. This is achieved by providing a high voltage output device characterized by outputting from the middle of the plurality of resistance elements according to a signal.

[0010]

EXAMPLES Examples of the present invention will be described below with reference to the drawings. 1 is a circuit diagram of a high voltage output device for explaining a first embodiment of the present invention. The high-voltage output circuit of this embodiment is a circuit in which two switching circuits 10 and 11 as first and second switching means having the same characteristics are connected in series, and each of the switching circuits 10 and 11 is 4 Individual photo M
OS / FET relays 10a to 10d and 11a to 11
It is configured by connecting d in series. Further, a high voltage supply terminal is provided at one end of each of the photo-MOS / FET relays 10a to 10d connected in series, and + HV is applied as the first high voltage. In addition, the resistor R
7 is connected. Similarly, the photo M connected in series
A high voltage supply terminal is provided at one end of each of the OS-FET relays 11a to 11d to apply a second high voltage minus HV, and a resistor R8 is connected to the other end terminal. The output terminal 0UT of the high-voltage output circuit of this embodiment has the resistance R7.
And R8, and the high voltage + HV or minus HV supplied to this connection point is output.

On the other hand, the circuit configurations of the above-mentioned photo MOS / FET relays 10a to 10d and 11a to 11d are all the same, and a light emitting diode (hereinafter referred to as LE) as a light emitting element is used.
12), an output MOS / FET 13 as a light receiving element and a switching means, a diode 14, and a Zener diode 15. Output M above
The OS-FET 13 is a so-called normally-off type FET, and when the LED 12 is off, the output MOS-FET 1
3 is off. The diode 14 is an output MOS
It is a diode for preventing counter electromotive force for bypassing a surge current when the FET 13 is turned off. Further, the Zener diode 15 has a Zener voltage slightly higher than the withstand voltage of the output MOS / FET 13 described above,
This is for protection when a bad voltage is applied to T13.

On the other hand, the anode (A) of the LED 12 in the above-mentioned photo-MOS / FET relays 10a and 10b is connected to the resistor R3, and the cathode (K) of this LED 12 is connected to the inverter 16. Therefore, the resistor R3-the LED 12 in the photo MOS-FET relay 10a-the LED 12 in the photo MOS-FET relay 10b-the inverter 16 constitutes a series circuit, and when a high signal is output from the input INH to the inverter 16, a current flows through the LED 12. The LED 12 emits light. In addition, the same applies to the LED 12 in the photo-MOS / FET relays 10c and 10d.
Since the anode (A) of the LED 12 is connected to the resistor R4 and the cathode (K) is connected to the inverter 16,
Resistor R4-LE in photo-MOS / FET relay 10c
D12-LED in photo MOS / FET relay 10d
12-Inverter 16 constitutes a series circuit, and when a high signal is output to inverter 16, LED 12 emits light. Therefore, from the inverter 16 to the photo MOS
-When a high signal is output as the first input signal to the LED 12 in the FET relays 10a to 10d, all the LEDs 12 emit light and the corresponding output MOS-FET 13 is turned on.

On the other hand, the circuit configuration of the switching circuit 11 is also the same as that of the switching circuit 10 described above, and the LED 12 in the photo-MOS / FET relays 11a and 11b is connected to the resistor R5, and the photo-MOS / FET relays 11c and 11d are connected. LED1
2 is connected to the resistor R6, and each resistor R5 (or R6) -L
ED12-inverter 17 constitutes a series circuit, and input I
By outputting a high signal from the NL to the inverter 17, the LE in the photo-MOS / FET relays 11a to 11d is output.
The second input signal is supplied to D12, the LED 12 emits light, and the corresponding output MOS • FET 13 is turned on.

Next, the circuit operation of the high voltage output circuit having the above configuration will be described with reference to the flow chart shown in FIG. First, during the period B shown in the figure, a low signal (hereinafter referred to as L signal) is supplied from the input INH and a high signal (hereinafter referred to as H signal) is supplied from the input INL. Therefore, during this period, the output of the inverter 16 becomes the H level and the output of the inverter 17 becomes the L level, so that the four L's in the photo-MOS / FET relays 10a to 10d are L.
The ED12 is turned off, and the photo-MOS / FET relay 11a
The four LEDs 12 within 11d emit light. Therefore, the four in the photo-MOS / FET relays 11a to 11d
Only the four output MOS-FETs 13 are turned on, and the high voltage minus HV applied to the high voltage supply terminal is the four output M.
Output terminal 0U via OS-FET 13 and resistor R8
Appears in T. Therefore, in the above-described period B, the high voltage minus HV is output from the output terminal 0UT of the high voltage output circuit.

On the other hand, the period C is a case where the H signal is supplied from the input INH and the L signal is supplied from the input INL. Therefore, during this period, the output of the inverter 16 becomes L level and the output of the inverter 17 becomes H level, and contrary to the above case, the photo-MOS / FET relay 10a.
The four LEDs 12 within 10d emit light, and only the corresponding output MOS • FET 13 is turned on. Therefore, the high voltage + HV applied to the high voltage supply terminal is four output MOS
Appears at the output terminal 0UT via the FET 13 and the resistor R7. Therefore, in the above-described period C, the high voltage + HV is output from the output terminal 0UT of the high voltage output circuit.

Therefore, during the periods B and C alternately set as described above, the signals shown in FIG. 2 are input INH,
And INL, a high voltage of minus HV and + HV can be alternately supplied from the output terminal 0UT to a recording electrode of an electrostatic recording device or the like as a bias voltage. Moreover, the high voltage output from the high-voltage switching circuit of this embodiment is the photo-MOS / FET relay 10
Since a to 10d and 11a to 11 are connected in multiple stages in series, an extremely high voltage can be supplied. For example, the breakdown voltage of the Zener diode 15 is 800 V, for example.
Then, if a high voltage + 2KV is applied to the high voltage supply terminal and a high voltage -1KV is applied to the high voltage supply terminal, the withstand voltage of each switching circuit 10 and 11 is four output MOSFETs.
Since it is a total of 13 (a voltage value slightly lower than 3.2 KV, which is a voltage obtained by multiplying the withstand voltage of the Zener diode 15 by four), a high voltage of +2 KV and -1 KV can be output from the output terminal OUT with a sufficient withstand voltage.

Next, a second embodiment of the present invention will be described.
FIG. 3 is a circuit diagram of the high voltage output circuit of the second embodiment.
This embodiment is a multilevel high voltage output circuit capable of outputting four kinds of high voltage, and two high voltage output circuits having the same structure as the circuit of the first embodiment are symmetrically arranged. Is. That is, the circuit on the left side shown in the figure is the same as the high voltage output circuit of the first embodiment described above, and the circuit on the right side is arranged symmetrically with the circuit on the left side. However, the values of the high voltages HV1 to HV4 applied to the high voltage supply terminals are different from each other. For example, the high voltage HV1 has the largest + voltage value (eg, +1 KV), and the high voltage HV2 has the next largest + voltage. Value (eg + 500V), high voltage HV3
Is a high voltage value of − (for example, −500V), and a high voltage H
V4 is the largest negative voltage value (eg -2KV)
Shall be For the sake of explanation, in FIG. 3, the same circuit elements as those in FIG. 1 are designated by the same reference numerals. Further, the switching circuit provided between the high voltage supply terminal and the resistor R13 is set to 19, and the switching circuit 19 is configured to form four photo-MOS / FEs connected in series.
Let T relays be 19a to 19d. Similarly, the switching circuit provided between the high voltage supply terminal and the resistor R14 has 20 switching circuits, and four photo-MOSs constituting the switching circuit 20.
・ Use FET relays 20a to 20d. Further, the resistances of the right side circuits corresponding to the resistances R3 to R6 of the left side circuits are R9 to R6.
R12, photo-MOS / FET relays 19a-1
It is connected to the corresponding LED 12 in 9d, 20a-20d.

FIG. 4 is a time chart for explaining the circuit operation of the above high voltage output circuit. First, the period D is the input I
In this case, the H signal is supplied only to N1 and the L signal is supplied to the other inputs IN2 to IN4. Therefore, in this period D, only the output of the inverter 16 becomes L level, the outputs of the other inverters 17, 21 and 22 become H level, and the four L in the photo-MOS / FET relays 10a to 10d.
Only the ED12 emits light, and the corresponding four output MOS · F
Only ET13 turns on. Therefore, at this time, the high voltage H
V1 appears at the output terminal 0UT through the four output MOS-FETs 13 in the photo MOS-FET relays 10a to 10d and the resistor R7. That is, in the above-mentioned period D, the high voltage HV1 is output from the output terminal 0UT of the high voltage output circuit.
Is output.

Similarly, in the period E, only the input IN2 is H level.
Since the signal is supplied, only the output of the inverter 17 becomes the L level, and the photo-MOS / FET relays 11a to 11d
Only the four LEDs 12 among them emit light, and only the corresponding four output MOS • FETs 13 are turned on. Therefore, during this period E, the high voltage HV2 is output from the output terminal 0UT of the high voltage output circuit. In the period F, the input IN3
H signal is supplied only to the
Set to level, only the corresponding 4 output MOS-FETs 13 are turned on, and the output terminal 0UT of the high voltage switching circuit
Outputs a high voltage HV3. Further, in the period I, the H signal is supplied only to the input IN4, only the output of the inverter 22 is set to the L level, and the corresponding four output MOS / FE
Only T13 is turned on, and high voltage HV4 is output from output terminal 0UT.
Is output.

As described above, by outputting four kinds of high voltages from the output terminal 0UT to the image forming section of the electrostatic recording device, the high voltage is used as the bias voltage when printing the recording electrodes and the bias voltage when not printing. In addition, it can be used as a cleaning voltage when collecting toner.

Further, also in the case of the present embodiment, the high voltage output from the high voltage output circuit has a structure in which the photo-MOS / FET relays are connected in series in multiple stages, and a large high voltage output is possible.

Next, a third embodiment of the present invention will be described.
FIG. 5 is a circuit diagram of a high voltage output circuit showing a third embodiment. The present embodiment is based on the circuit of the second embodiment described above, and the parts different from the circuit of FIG. 3 are the photo-MOS / FET relays 10a to 10d, 11a to 11 respectively.
This is a configuration of the output MOS • FET 13, which is the output of d, 19a to 19d, and 20a to 20d, the diode 14, and the zener diode 15. That is, output MOS · F
The ET 13 is composed of a pair of FETs 13a and 13b. For example, the FET 13a is driven when the high voltage supply terminal side has a high potential, and the FET 13b is driven when the high voltage supply terminal side has a low potential. Moreover, the diode 14 is also composed of two diodes 1.
4a and 14b, which is capable of absorbing the surge current when the FET is off, whichever FET 13a or 13b is driven. Furthermore, the Zener diode 15 is also 1
5a and 15b, a high withstand voltage is ensured regardless of whether the high voltage supply terminal has a high potential or a low potential.
It is configured to protect 13a or 13b.

Therefore, according to the high voltage output circuit of the present embodiment, it is possible to operate even if the positive / negative relationship between the high voltage supply terminals and is not predetermined. In the above three embodiments, the case where the low signals are simultaneously output to the inputs INH and INL or the inputs IN1 to IN4 has not been described, but in this case, the output terminal O of the circuit is used.
The UT is in a floating state. Similarly, input I
If a high signal is simultaneously output to NH and INL or inputs IN1 to IN4, the resistors R7 and R8 or the resistor R
The divided voltages of 7, R8, R13, and R14 are used, but such a use is not normally performed.

Further, in this embodiment, each photoMOS.F is
Although the LEDs 12 arranged in the ET relays 10a to 10d and the like use normally-off type LEDs, they may be configured by using normally-on type LEDs.

Further, in this embodiment, each switching circuit 10, 1
Although 1, 19, and 20 are configured by connecting four stages of photo-MOS / FET relays in series, other stages of photo-MOS / FET relays are connected in series according to the required high voltage. Is also good.

[0026]

As described in detail above, according to the present invention, a small number of photo-MOS / FET relays are connected in series to form a high-voltage switching circuit, which can output a high voltage. Miniaturization is possible.

Further, since it is a high voltage output circuit in which a plurality of photo-MOS / FET relays are connected in series, a high withstand voltage output is possible. Further, even if the positive / negative relationship of the high voltage supply terminal is not predetermined, the high voltage output device of the present invention can output a high voltage by performing the switching process, and thus the high voltage output device of the present invention is convenient for the user and can be used for a wide range of purposes. .

[Brief description of drawings]

FIG. 1 is a circuit diagram of a high voltage output device according to a first embodiment.

FIG. 2 is a time chart illustrating the circuit operation of the high voltage output device according to the first embodiment.

FIG. 3 is a circuit diagram of a high voltage output device according to a second embodiment.

FIG. 4 is a time chart for explaining the circuit operation of the high voltage output device according to the second embodiment.

FIG. 5 is a circuit diagram of a high voltage output circuit according to a third embodiment.

FIG. 6 is a circuit diagram of a conventional high voltage output circuit.

[Explanation of symbols]

 10, 11, 19, 20 Switching circuit 12 LED 13 Output MOS / FET 14 Diode 15 Zener diode 16, 17, 21, 22 Inverter ~ High voltage supply terminal R3 ~ R14 Resistance

Claims (1)

[Claims] 1. A light emitting element which operates according to an input signal,
A photorelay in which a light receiving element that operates by receiving the light of the light emitting element and a switching means that is driven based on the operation of the light receiving element are integrally formed, and the photorelay by connecting a plurality of the switching means in series And a plurality of resistance elements connecting terminals of the switching means of the first and second opening / closing means, and one of the other side of the terminals. To a second high voltage on the other side of the terminal, a first input signal is applied to one end of the light emitting element of the first opening / closing means, By inputting a second input signal to one end of the light emitting element of the opening / closing means, the first high voltage or the second high voltage is applied to the plurality of resistance elements according to the first and second input signals. Special output from the middle of High voltage output device to be considered.