JPH06102321A - Failure simulation method for logic circuit - Google Patents

Abstract

PURPOSE:To judge the effectiveness of a test pattern made for a functional test for a logic circuit in a short time by retrieving the content stored in a logic operation storage table sequentially from an output terminal and outputting the same to a logic storage table to collate and detect a failure. CONSTITUTION:A 0 1 change is displayed as (a), and 1 0 change is displayed as (b). Even if at the time t1, an input terminal 10 causes a change (a), a logic gate 14 is fixed to 0 level by an input terminal 11, and logic gates 15, 16 are respectively fixed to 0 level by all of input terminals 12, 13 and a logic gate 4. Whereas, output terminals 17, 18 are respectively fixed to 0 level. At this time, when failure detecting retrieval for the logic gate is performed from the output terminals 17, 18 side, the output terminal 17 enters 0 level as the logic gate 15 is 0 level to detect a failure that the logic gate 15 is fixed to 1. Further, a failure that the logic gate 14 and input terminals 11, 12 are fixed to 1 level can be detected at the time t1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure simulation method for logic circuits.

[0002]

2. Description of the Related Art A fault simulation method using a single stuck-at fault model will be described as an example of a conventional fault simulation method. What is a single stuck-at fault model?
This is a failure model in which one point on a logic circuit is fixed at 0 level or 1 level, and only one failure occurs simultaneously on one logic circuit.

A logic simulation is performed using a logic circuit in which this fault is defined, and it is determined that the fault can be detected if there is a difference from the result of the logic simulation using a logic circuit in which no fault is defined.

When the logical simulation results are the same, it is judged that the failure cannot be detected by this test pattern. This fault definition and logic simulation are sequentially repeated for all logic gate input terminals on the logic circuit to diagnose the effectiveness of fault detection by the test pattern.

In the logic circuit shown in FIG. 1, if a fault in which only the input terminal and the output of each logic gate are fixed to 0 level or 1 level is sequentially defined and the logic simulation is repeated, the fault definition is at least 14 times. By repeating the logic simulation 15 times, one failure simulation is performed, and the effectiveness of the failure detection by the test pattern can be diagnosed.

[0006]

In the conventional fault simulation using the single stuck-at fault model, the fault definition and the logic simulation are performed assuming that only one fault occurs at the same time. The terminals have to be repeatedly and sequentially performed, which results in an enormous number of logic simulation executions, and it takes a long time to obtain the results.

An object of the present invention is to provide a failure simulation method for a logic circuit, which determines the validity of a test pattern created for functional test of the logic circuit in a short time.

[0008]

In order to achieve the above-mentioned object, a fault simulation method for a logic circuit according to the present invention is a fault simulation method for diagnosing the effectiveness of a test pattern created for a functional test of a logic circuit. ,
The state of the logic gate operated by the test pattern and the immediately preceding logic gate name necessary for maintaining the state are stored in the logic operation storage table, and the failure state of the logic gate is stored in the failure storage table. Every time, the contents stored in the logical operation storage table are searched in order from the output terminal, and are output to the logical storage table and collated to detect a failure.

Further, in the logical operation storage table, the logical gate name immediately before the logical gate is in the state of operating according to the test pattern is added and stored.

[0010]

The effectiveness of the test pattern created for the functional test of the logic circuit is diagnosed by executing the logic simulation once and searching the logic operation storage table.

[0011]

The present invention will be described below with reference to the drawings.

Input terminals 10 and 1 of the logic circuit shown in FIG.
1, 12 and 13 have the test patterns P1, P2 and P of FIG.
This logic circuit is operated by the inputs of 3 and P4, and the patterns P5 and P6 of the logic simulation result shown in FIG. 2 are obtained from the output terminals 17 and 18 thereof.

FIG. 3 is a logic operation storage table used in the failure simulation of the present invention. 10 to 13 in the uppermost row of the table are input terminals of the logic circuit of FIG. 1, 14 and 15 and 16 are logic gates. Reference numerals 17 and 18 denote output terminals, and columns t1 to t9 indicate time. Also, a is 0 →
The change b to 1 and the change b to 1 → 0.

The character following the: indicates the state of the logic gate operated by the test pattern, and the character preceding the: means the name of the logic gate immediately before reaching the state of the logic gate.
It is a logic gate name with (). The logic gate name with () is the name of the logic gate immediately before it is necessary to maintain the state when the state of the logic gate changes.

And and 〆 are used when there is a plurality of immediately preceding logic gates, and · is influenced by the states of the immediately preceding logic gates acting at the same time, and if one of the logic gates changes, the Indicates that the state of the logic gate changes, and the state of the logic gate is determined by the state of at least one logic gate, and the state of the logic gate is changed unless all the states of the logic gate stored immediately before are changed. Indicates that is not changed.

Here, the = and the following 0 or 1 shown in parentheses are the states of the logic gate immediately before necessary to maintain the state of the logic gate. It is filled in for simplicity and is not required in the logical operation storage table.

Next, a failure detection method will be described using the logical operation storage table shown in FIG. First, all inputs are 0
It is assumed to be in a level state. At time t1, the input terminal 10 changes from 0 to 1. In addition, 0 →
A change of 1 is indicated as a, and a change of 1 → 0 is indicated as b.

Even if the input terminal 10 changes a at the time t1, the logic gate 14 is set to 0 by the input terminal 11.
The logic gates 15 and 16 are fixed to the level and the input terminal 1
0 by each of 2 and 13 and the logic gate 14
The output terminals 17 and 18 are fixed to the 0 level, respectively.

At this time, when the failure detection and retrieval of the logic gate is performed from the output terminals 17 and 18, the output terminal 17 is at 0 level because the logic gate 15 is at 0 level, and the logic gate 15 is at 1 level. It is possible to detect a fault that is fixed to.

Next, in the logic gate 15, the input terminal 12 and the logic gate 14 are simultaneously at 0 level, and further, the input terminal 11 of the logic gate 14 is at 0 level.
Therefore, the logic gate 14 and the input terminals 11 and 12 are 1
A level-fixed fault can also be detected at time t1.

Similar to the above-mentioned time t1, even at times t2 to t9, the contents of the detected faults are output in order from the output terminal and output to the fault table. This failure table is shown in FIG.

The failure table of FIG. 4 shows that if a failure occurs in which the output of the input terminal 13 is fixed at 0, the test pattern shown in FIG. 2 cannot detect it. When this is confirmed by the logical operation storage table of FIG. 3,
The input terminal 13 can be confirmed via the output terminal 18 and the logic gate 16, and among them, the state in which the input terminal 13 is at 1 level is at times t2 and t7. At the times t2 and t7, the logic gates 14 and the input terminal 13 have brought the logic gate 16 into the state.

Here, since the state of the logic gate 16 is determined by at least one state of the logic gate 14 and the input terminal 13 as described in 〆, even if the other side fails, it is detected. It is not possible. However, since it is possible for the logic gate 14 to detect the occurrence of a failure by the output terminal 17 and the logic gate 15, it can be seen that only the 0 failure at the input terminal 13 cannot be detected.

In the above description, the logical operation memory is performed using the symbols shown in FIG. 3, but the invention is not limited to this.
It is obvious that the stored contents including the same logical operation contents can be used in the same manner and achieve the object of the present invention.

[0025]

As described above, according to the fault simulation method of the present invention, the validity of the test pattern created for the functional test of the logic circuit is verified by executing the logic simulation once and searching the logic operation storage table. A fault simulation to diagnose can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of a logic circuit.

FIG. 2 is a diagram showing a test pattern.

FIG. 3 is a diagram showing a logical operation storage table used in the failure simulation of the present invention.

FIG. 4 is a diagram showing a failure storage table.

[Explanation of symbols]

 10, 11, 12, 13 Input terminals 14, 15, 16 Logic gates 17, 18 Output terminals t1, t2 to t9 Time

Claims (2)

[Claims] 1. A failure simulation method for diagnosing the effectiveness of a test pattern created for a functional test of a logic circuit, comprising: a state of a logic gate operated by the test pattern; and a state immediately before it is necessary to maintain the state. And the logic gate name of the logic operation memory table, and the failure state of the logic gate is stored in the failure memory table, and the contents stored in the logic operation memory table are searched in order from the output terminal. A failure simulation method for a logic circuit, which is characterized in that the failure is detected by outputting the result to a storage table and comparing it. 2. The failure of the logic circuit according to claim 1, wherein the logic operation storage table is added with a logic gate name immediately before the logic gate reaches a state in which it operates according to a test pattern and is stored. Simulation method.