JPH06101727B2 - Receiver circuit - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a system for performing remote monitoring of power distribution equipment by a communication terminal, for example, a multi-drop system, and in particular, a receiving circuit for an FM signal returned in response to a polling call signal. Regarding

[Technical background of the invention]

In general, the multi-drop system uses, as shown in FIG. 3, a coupler 11 connected to the central unit 10 and a distribution line connecting a distribution device (not shown) such as a switch as a transmission line. A plurality of terminals 13 for controlling each distribution device are connected to the transmission line 12.

In this multi-drop method, since the terminal device 13 moves as the transmission line 12 changes, it is unclear which transmission line is connected to which terminal device. In addition, since the length of the transmission line 12 is not constant, it cannot be terminated with an appropriate impedance, so that the signal level is lowered depending on the connection location of the terminal device 13 due to the standing wave phenomenon. To avoid these
The same information is transmitted by using two carrier frequencies of the FS modulation system, and when the signal level of one channel drops, the other channel compensates.

That is, when the terminal device 13 which is present in the central unit 10 is called for polling, as shown in FIG. 4, the calling signal generating circuit 15, the FS modulating circuit 16 and the transmitting circuit 18 including the amplifier 17 of the central unit 10 are used to terminate the terminal. A calling signal to which the address number of the device 13 is added is simultaneously transmitted to each transmission line 12 via the coupler 11. Then, when the terminal device 13 that matches the address number of the calling signal receives the calling signal, the terminal device 13 transmits a return signal to which its own address number is added. This return signal is received by the receiving circuit 20 of the central unit 10 via the coupler 11. The return signal received by the receiving circuit 20 is demodulated by the demodulation circuits 23, 24 via the bandpass filters 21, 22 for each channel.
And is demodulated into digital signals by the demodulation circuits 23 and 24. The signals that have passed through the bandpass filters 21 and 22 are input to the carrier detection circuits 25 and 26. This carrier detection circuit 2
Reference numerals 5 and 26 enable the demodulation signal of the channel having a certain level of input or more to open the gate circuit 27 and output the demodulation signal to the channel selection circuit 28 in order to discriminate between the noise and the return signal. In this channel selection circuit 28, the demodulation signal of the channel in which the carrier detection output is generated is output to the code verification circuit.However, when the carrier detection output is generated in a plurality of channels, one channel is output based on the preset priority order. The demodulated signal of is selected and output to the code verification circuit 29. The code verification circuit 29 carries out a parity test of the code of the input demodulated signal, a verification of continuous transmission verification and an address verification, and uses the signal regarded as correct as valid information.

[Problems of background technology]

However, in such a receiving circuit, only one signal selected according to the priority from the signals of a plurality of channels in which the carrier detection circuit outputs a certain level or more is subjected to the sign verification, and thus the selected channel is selected. If the signal in (1) has a high noise level and the SN ratio deteriorates and contains many errors, it is regarded as an invalid signal in the sign test even if the signals in other channels are correct. Also, if the output of the band-pass filters 21 and 22 becomes lower than the carrier detection level due to the decrease of the reception level, the signal output of one channel is correct and the signal output of the other channel becomes erroneous and becomes higher than the detection level. In the carrier detection circuit, a correct demodulation signal below the detection level is regarded as an invalid signal, and a demodulation signal in which an error above the detection level has occurred is regarded as a valid signal, which causes a problem of deterioration of reception performance. .

[Object of the Invention]

The present invention has been made in view of the above problems, and if there is at least one channel having a correct demodulated signal in a demodulated signal, a correct effective signal can be obtained even if the reception level is lowered. The purpose is to provide a circuit.

[Outline of Invention]

The present invention provides a demodulation circuit that demodulates a return signal through a bandpass filter, a gate circuit that passes the demodulation signal, a timer circuit that opens the gate circuit for a certain period of time after a calling signal is transmitted, and an output signal that passes through the gate. A sign verification circuit for sign verification and a coincidence judgment circuit for judging the address number of the output signal for which the sign verification is performed and the called terminal address number are provided, and each channel is forcibly forced for the time managed by the timer after the call signal is transmitted. The above-mentioned object is achieved by incorporating the demodulated signal of 1 into the code verification circuit and the coincidence determination circuit, performing the code verification and determining the address number, and detecting the correct signal.

Example of Invention

An embodiment of the present invention will be described in detail with reference to the drawings of FIGS.

FIG. 1 is a functional block diagram of an embodiment of the present invention, and portions having the same functions as those in FIG. 3 are designated by the same reference numerals for convenience of explanation.

The return signal for the polling call signal is received by the receiving circuit 30 from the transmission line 12 via the coupler 11. The return signal received by the receiving circuit 30 is demodulated into digital signals by the demodulating circuits 23, 24 via the bandpass filters 21, 22 for each channel and output to the gate circuit 27. This gate circuit 27
A timer circuit 31 is connected to this circuit, the gate is opened for a certain period of time after the calling signal is transmitted, and a demodulation signal is output to the code verification circuit 29.

That is, as shown in the timing chart of FIG. 2, after the polling call signal A is received, the return signal B having a constant time length reaches the receiving circuit 30 from the terminal device 13. Therefore, when the gate circuit 27 is opened by the timer circuit 31 for a time T which is equal to or longer than the information bit length b of the return signal B after a lapse of a certain time t after the polling call signal A is transmitted, only the effective information bits except the noise C are released. Can be extracted.

The demodulated outputs obtained in this manner are respectively used in the sign verification circuit 29.
Then, the parity test and continuous transmission matching are performed, and only the signal that has passed the test is output to the coincidence determination circuit 32 as a correct signal. The match determination circuit 32 determines whether the address number of the input signal and the called terminal address number match, and if they match, the signal is treated as valid information.
If there are multiple signals that have passed the test, it is determined whether the contents of the signals match, and if they do not match, the signal is invalidated. Therefore, if the returned signal is demodulated without error in one channel, an effective signal can be obtained even if there is a channel with a lowered reception level and a high noise level.

Although the above-described embodiment shows the case where the distribution line as the transmission line has two lines, the same receiving circuit can be used even if the number of lines increases. Further, this receiving circuit can be applied not only to the distribution line but also to transmission of a line with a lot of reception level fluctuations and a lot of noise and poor quality, for example, a wireless line.

〔The invention's effect〕

As described above, according to the present invention, the demodulated signal of each channel is forcibly taken into the code verification circuit and the coincidence determination circuit for the time managed by the timer after the calling signal is transmitted, and the code verification and the address number determination are performed. Even if the level of the return signal is reduced or the demodulation output of a specific channel is erroneous due to the deterioration of the SN ratio, a correct effective signal can be obtained as long as there is at least one channel with no erroneous demodulation output. Therefore, it is possible to remarkably reduce the reception loss of the return signal and improve the reception performance.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a functional block diagram of a receiver circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing the same timing chart, and FIG.
FIG. 4 is a power distribution system diagram by the multi-drop method, and FIG. 4 is a functional block diagram showing a transmission / reception circuit of a conventional example. 10 …… Central device, 11 …… Coupler, 12 …… Transmission line, 13 ……
Terminal, 18 ... Transmitting circuit, 20,30 ... Receiving circuit, 21,22 ...
Bandpass filter, 23,24 Demodulator, 25,26 Carrier detection circuit, 27 Gate circuit, 28 Channel selection circuit, 29 Sign verification circuit, 31 Timer circuit, 32 circuit Match determination circuit.

Claims (1)

[Claims] 1. A receiving circuit for receiving a return signal from a terminal device for a polling call signal for each channel, a demodulation circuit for demodulating the return signal via a bandpass filter, and a gate circuit for passing the demodulated signal. A timer circuit that opens the gate circuit for a certain period of time after a call signal is transmitted, a sign verification circuit that verifies the sign of the output signal that has passed through the gate, and a judgment of the address number of the sign-verified output signal and the called terminal address number. A receiving circuit characterized by being provided with a coincidence determining circuit.