JPH061008A - Printer controller - Google Patents

Abstract

PURPOSE:To increase the speed of formation of a bit map image data by provid ing a font cache means for storing the bit map image data formed by a printer controller as a binary data, converting the same into a multi-valued data and outputting. CONSTITUTION:Whether characters to be formed are stored in a font cache or not is checked by character codes and the like stored in respective cache control labels by a CPU (S1). When the data is in the font cache (S2), the cache data corresponding to the characters is read, and converted into the multi-valued data and stored in a page memory (S3...S9). The formed multi-valued bit map data is stored in the page memory by the CPU, and sometimes the operation for pixels in the page memory is also carried out (S6). At that time, the pixel data is loaded from the page memory and bit operated, and then stored in the page memory of the address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printer controller that generates bitmap image data according to print data output from a host device and performs print control on a printer engine.

[0002]

2. Description of the Related Art A printer controller in a laser printer or the like has, as a storage means, a code ROM storing an operation program of a CPU and a font ROM storing a bit map font or an outline font for a text character, a work area of the CPU and a CPU.
It has a RAM including a bitmap data area for pages. Generally, R in the printer controller
AM is a page memory area that stores bitmap image data for one page, a font cache area that stores this bitmap image data when an outline font of text characters is expanded into bitmap image data, and a postscript ( PDL assigned to process page description language (PDL) such as Post Script
The work area and other auxiliary areas.

This RAM area is, for example, A4 paper, 300
A printer controller compatible with dpi, binary (monochrome) requires a capacity of about 2 Mbytes. In this case, a page memory area of 1 Mbyte, a font cache area of about 100 Kbytes to 200 Kbytes, and a PDL work area of about 500 Kbytes are allocated.

On the other hand, with the development of electrophotographic technology and laser driving unit / scanning unit in printer engines, not only high resolution of binary printers but also bitmap image data is converted into multi-valued data (1 pixel is 2 bits). Printers that are capable of expressing gradation (grayscale) have been commercialized. In such a printer, since the bitmap image data is generally stored in the RAM as 4 bits or 8 bits,
This increases the capacity of the RAM. For example, A4 paper, 300 dp
A printer controller compatible with i, 256 gradations requires 8 Mbytes as a page memory area.

[0005]

However, in this type of printer controller, the text characters may also have gradation, and generally the bitmap image data of the characters stored in the font cache area is also stored as multi-valued data. Therefore, in order to correspond to the number of characters that can be stored in the font cache area of the binary printer, the capacity of this font cache area needs to be 1 Mbytes or more.

Further, in the bitmap image formation of a text character, it is necessary to generate a character outline from outline font data and to fill the generated character outline, and thus a RAM access operation is frequently performed. In this processing, the number of times of memory access is extremely large in the case of multi-valued data than in the case of binary data, and it takes a long time to generate the bitmap image data.

The present invention provides a printer controller which eliminates the above-mentioned conventional drawbacks, reduces the RAM capacity required for the font cache area, and speeds up the generation of bitmap image data as multi-valued data. .

[0008]

In order to solve this problem, a printer controller of the present invention is a printer controller for generating bitmap image data having gradation from code data, and is generated by the printer controller. A font cache means for storing the bitmap image data as binary data, and a binary cache stored in the font cache means when the bitmap image data corresponding to the code data is already stored in the font cache means. A font cache control means for converting the data into multi-valued data and outputting the multi-valued data. Here, the font cache control means 2
In the conversion from the value data to the multi-valued data, the value of the multi-valued data is replaced with 00 when the value of the binary data is 0, and the predetermined gradation value is replaced when the value is 1.

[0009]

With this structure, when the bitmap image data is generated from the code data, the bitmap image data stored in the font cache means is read, converted into multi-valued data having gradation and output. By providing such a processing function, it is possible to reduce the RAM capacity required for the font cache area and to speed up the generation of bitmap image data as multi-valued data.

[0010]

The present invention will be described below with reference to the illustrated embodiments.

FIG. 1 is a block diagram showing the arrangement of a printer controller in a laser printer or the like. The host device 109, the operation panel 110, and the printer engine 111, which are external devices of the printer controller of the present example, are shown by dotted lines, but the configuration of FIG. 1 is an example thereof, and the configuration of the printer controller of the present invention is not shown. It is not limited to the range indicated by the solid line 1 and may include the above external device or may lack a part of the configuration of FIG.

In the figure, reference numeral 101 is a CPU for controlling the operation of the printer controller. 102 is a CPU
The memory / I / O control unit receives the address and the bus control signal output from 101 and controls the timing of the memory devices 103 to 105 and the I / F control units 106 to 108. Reference numeral 103 is a code ROM that stores the operation program of the CPU 101, 104 is a font ROM that stores a bitmap font or outline font for text characters, and 105 is a CPU
The RAM includes a work area 101, a bitmap data area for one page, and the like. Further, 106 is data communication with the host device 109 (Centronics or RS-2
A host I / F control unit for controlling the I / F of the 32C or the like), a panel I / F control unit 107 for performing display control of printer status on the operation panel 110 and a switch input control, and a reference numeral 108 for the printer engine 111. A printer I / F control unit that controls output of bitmap image data and communication control of commands / status. Data input / output from the CPU 101 to each of the memory devices 103 to 105 and each of the I / F control units 106 to 108 is performed through a data bus.

The operation sequence in the figure is described below. The CPU 101 inputs print data output from the host device 109 from the host I / F control unit 106, generates bitmap image data from the print data, and stores it in the RAM.
Expand into 105. If the print data includes text characters, the font data corresponding to the text character code is read from the font ROM 104 to generate bitmap image data. When the CPU 101 completes the generation of the bitmap image data for one page,
A request to start printing is issued to the printer engine 111, and then printing is started by a vertical synchronization signal output from the printer engine. In this case, the RAM 105
Bitmap image data in the printer I
To the printer engine 111.
The bit map image data is output in synchronization with the horizontal sync signal from the.

FIG. 2 shows the RAM configuration of the printer controller of this embodiment.

The RAM in the printer controller of this embodiment has a page memory area 105a for storing one page of bitmap image data and a bitmap image data when an outline font of a text character is expanded into the bitmap image data. Font cache area 105b for storing the
It is composed of a PDL work area 105c allocated for processing a page description language (PDL) such as Script) and other auxiliary area 105d. In the PDL work area 105c or other auxiliary area 105d, there is a gradation value data area 105e for storing the gradation value referred to when converting the cache data in the font cache area 105b into multi-valued data.

FIG. 3 is a font cache area 105 in the RAM 105 of the printer controller of this embodiment.
It shows the configuration of b.

In the figure, the font cache area 1
Reference numeral 05b denotes a cache data area for storing bitmap image data of text characters (cache data 0, 1, 2, ...) And a portion for managing information of each cache data in this area (cache management tables 0, 1). , 2, ...) and a cache management area having a cache entry indicating the number of stored text character entries.

FIG. 4 shows details of the cache management table in FIG.

Each cache management table includes a character code, a typeface name and size as text character information, and the number of horizontal pixels is X dots, the number of vertical pixels is Y dots and cache data as cache data information. Contains the territory address of. Further, as attribute information of the cache data, a default bit D (Default) indicating whether or not the cache data is generated in advance when the power is turned on, and the font cache area area is filled with the generated cache data. In this case, a replaceable bit R (Replaceable) indicating whether or not it can be replaced with new bitmap image data and a hit level bit field (Hit Level) indicating how many times the cache data is referred to are included. Of these attribute information, the replaceable bit R is "1" and the hit level value is smaller, and the cache area of the new bitmap image data is replaced in order.

FIG. 5 is a flow chart showing the process of generating bitmap image data of text characters in the multi-valued printer controller of this embodiment.

The CPU 101 checks whether or not the character to be generated exists in the font cache area 105b (FIG. 2) based on the character code, typeface name and size stored in the cache management table (step S1). . If there is data in the font cache area 105b (step S2), the cache data matching the corresponding character is read, converted into multi-valued data and stored in the page memory 105a (steps S3 to S9). .

In this case, the start address of the area where the cache data is stored from the cache management table that matches the corresponding character is the address counter C _ADR ,
The total number of pixels N dots is calculated from the number of horizontal pixels X dots and the number of vertical pixels Y dots, and the number of pixels ΔN of cache data read by one bus transfer is set (step S3). After that, the cache data is loaded (step S4), and binary data (1 bit) is set for each pixel.
To multi-valued data (8 bits) are converted (step S5). At this time, if this pixel value is "0", "0"
If it is "0" and "1", the gradation value data area 105e
Is converted into multi-valued data as a “gradation value”.

Next, the CPU 101 stores the generated multi-valued bitmap data in the page memory area 105a. However, not only the storage but also the operation on the pixel in the page memory area 105a to be stored may be involved. (Step S6). At this time, the page memory area 105a
After loading pixel data from inside and performing bit operations (logical product, logical sum, exclusive OR, addition, subtraction, etc.),
The data is stored in the page memory area 105a having the same address.
The CPU 101 performs steps S5 and S6 for ΔN pixels (step S7), then updates the address of the cache data (step S8), and completes the processing for N dots of the total number of pixels of the character to be bitmapped. The above steps S4 to S8 are repeatedly executed (step S
9).

On the other hand, when the cache data of the character to be bitmapped does not exist in the font cache area 105b, the CPU 101 causes the font ROM 104 to operate.
Outline font data corresponding to the character to be bit-mapped is read out, bit map data is generated and stored in the page memory area (step S1).
0). Next, the font cache area of the generated bitmap image data is stored (step S11).
Details of this are shown in FIG.

In this case, it is checked whether the generated bitmap image data of the character should be stored (cached) in the font cache area (step S12), and if it is the character to be cached, the following steps S13 to S17 are executed. If it is not a character to be cached, this process ends.

When this character is cached, it is checked whether or not there is a sufficient area in the font cache area (step S13). If the area allocated to the font cache area is occupied by the previously generated character cache data and there is not enough area for new storage, the CPU 101 stores in each cache management table. The cache management table having the smallest replaceable bit R value "1" and the smallest hit level value can be replaced by referring to the stored attribute information, that is, the replaceable bit R and the hit level value (step S14). Area (step S15). Next, after storing the information of the character data to be stored in the cache management table shown in FIG. 4 (step S16), the bit-mapped character data is stored in the cache data area (step S17). If it is determined in step S13 that the font cache area has a sufficient area for storing new character data, steps S16 and S1.
Do only 7.

[0027]

[Other Embodiments] FIG. 7 is a block diagram of a printer controller according to the second embodiment of the present invention. In the figure, 11
2 is a font cache area 105b of the RAM 105
It is a font cache control unit for reading the cache data of the text characters stored therein, converting it into multi-valued data and storing it in the page memory area, and its internal configuration diagram is shown in FIG. In the present embodiment, the font cache control unit 112 automatically executes steps S4 to S9 in the flowchart of FIG. 5 by hardware.

The configuration and operation of FIG. 8 will be described below. 112a and 112b are buffers for an external data bus and an external address bus, 112c generates an address for cache data and an address for a page memory area in the font cache area 105b,
Address control unit 112d for outputting to an external address bus
Is a sequencer for controlling data transfer between the CPU 101 and the RAM 105, and for controlling each register and arithmetic unit in the font cache control unit 112. The operations corresponding to steps S4 to S9 in FIG. 5 are controlled by all sequencers 112d.

112e is a font cache area 105.
a gradation value data register for storing a gradation value referred to when converting the cache data in b into multi-valued data, 11
2f is a cache data register for storing cache data loaded from the font cache area 105b, and 112g is each pixel data (1 bit) output from the cache data register 112f to multi-value pixel data (8 bits). A binary / multi-value conversion unit for converting data to "00" when the data is "0" and data stored in the gradation value data register when the data is "1".

Reference numeral 112h is a multi-valued register for storing the result of the binary / multi-value conversion unit 112g, which is stored in the multi-valued register having the same number as the reference bit field number of the cache data register. Reference numeral 112i is a multi-valued input / output register that holds output data to be stored in the page memory area 105a, or input data loaded from the page memory area 105a for operation with pixel data in the page memory area 105a. . 112j
Is a multi-value arithmetic unit that performs an operation (logical product, logical sum, addition, subtraction, etc.) between the data stored in the binary register 112h and the data stored in the multi-value input / output register 112i. The result is output to the multilevel input / output register 112i.

Next, the font cache control unit 11
The operation flow of No. 2 will be described based on the flowchart of FIG. In FIG. 5, the processes of steps S1 to S3 and steps S10 and S11 are performed by the software of the CPU 101. In step S3, the start address of the cache data, the total number of pixels N dots, and the number of pixels of the cache data read by one bus transfer ΔN
Is stored in the address control unit 112c and the sequencer 112d as control data, and the gradation value of the bitmap image data to be output to the page memory area 105a is stored in the gradation value data register 112e. After that, the CPU 101 determines that the font cache area 105b
Page memory area 105a after binary / multivalue conversion from
The font cache control unit 112 is caused to perform the process (steps S4 to S9) until the storage. Step S4 ~
The control of the operation flow corresponding to S9 is entirely controlled by the sequencer 112d (the CPU 101 transfers the bus control right to the sequencer 112d). In step S4, the cache data is transferred from the font cache area 105b to the cache data register 112f.

Next, in step S5, multi-valued pixel data is sequentially generated in the binary / multi-value conversion unit 112g based on the data in the cache data register 112f and the gradation value data register as described above. And stores it in the multi-valued register 112h. In steps S6 and S7,
An arithmetic operation of each pixel data in the page memory area 105a and each data in the multi-value register 112h is performed in the multi-value arithmetic unit, and the operation result is the multi-value input / output register 112i.
Through the page memory area 105a. ΔN
When the processing for the pixels (steps S4 to S7) is processed, the storage address C _ADR of the cache data is updated in the address control unit (step S8), and the above processing is repeated until all pixels are processed (steps S4 to S4).
9). When this process ends, the font cache control unit 112 (sequencer 112d) transfers the bus control right to the CPU 101, and the CPU 101 controls the entire printer controller again.

The present invention may be applied to either a system composed of a plurality of devices or an apparatus composed of a single device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0034]

According to the present invention, it is possible to provide a printer controller capable of reducing the RAM capacity required for a font cache area and speeding up the generation of bitmap image data as multi-valued data.

That is, in a printer controller that handles image data having a gradation (gray scale), the storage of character data expanded into bit map image data in the font cache area is binary-formed, and the printing output from the host device is performed. When the bitmap image data is generated from the data, it has the processing function of converting the character data in the font cache area to multi-valued data with gradation and storing it in the page memory area. The capacity can be reduced and the bit map image data as multi-valued data can be generated faster.

Further, reading of data in the font cache area, conversion from binary data to multi-valued data, and operation / storing with a page memory are provided as hardware to enable higher speed processing.

[Brief description of drawings]

FIG. 1 is a block diagram of a printer controller according to a first embodiment.

FIG. 2 is a RAM configuration diagram of a printer controller according to the present exemplary embodiment.

FIG. 3 is a configuration diagram of a font cache area of the printer controller according to the present embodiment.

FIG. 4 is a configuration diagram of a cache management area of a font cache area according to the present embodiment.

FIG. 5 is a flowchart showing a process of generating bitmap image data of a text character using the font cache area of this embodiment.

FIG. 6 is a flowchart showing storage of bitmapped text character data in a font cache area according to the embodiment.

FIG. 7 is a block diagram of a printer controller according to a second embodiment.

FIG. 8 is an internal block diagram of a font cache control unit of the second embodiment.

[Explanation of symbols]

101 ... CPU, 102 ... Memory I / O control unit, 103
… Code ROM, 104… Font ROM, 105
RAM 105a Page memory area 105b Font cache area 105c PDL work area 105d Other RAM area 105e Gradation value data area 106 Host I / F controller 107 Panel I / F control unit, 108 ... Printer I / F control unit, 1
09 ... Host device, 110 ... Operation panel, 111 ... Printer engine, 112 ... Font cache control unit, 1
12a, 112b ... I / O buffer, 112c ... Address control unit, 112d ... Sequencer, 112e ... Gradation value data register, 112f ... Cache data register,
112g ... Binary / multivalue converter, 112h ... Multivalue register, 112i ... Multivalue input / output register, 112j ... Multivalue calculator

Claims (2)

[Claims] 1. A printer controller for generating bitmap image data having gradation from code data, the font cache means storing the bitmap image data generated by the printer controller as binary data, and code data. When the bitmap image data corresponding to is already stored in the font cache means,
A printer controller comprising: a font cache control unit for converting binary data stored in the font cache unit into multi-valued data and outputting the multi-valued data. 2. The conversion from binary data to multi-valued data by the font cache control means is such that when the value of the binary data is 0, the value of the multi-valued data is 00, and when it is 1. The printer controller according to claim 1, wherein the printer controller is replaced with a predetermined gradation value.