JPH059968B2 - - Google Patents

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Publication number
JPH059968B2
JPH059968B2 JP58127106A JP12710683A JPH059968B2 JP H059968 B2 JPH059968 B2 JP H059968B2 JP 58127106 A JP58127106 A JP 58127106A JP 12710683 A JP12710683 A JP 12710683A JP H059968 B2 JPH059968 B2 JP H059968B2
Authority
JP
Japan
Prior art keywords
circuit
error signal
signal
input
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58127106A
Other languages
Japanese (ja)
Other versions
JPS6019322A (en
Inventor
Mitsuo Sano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yaesu Musen Co Ltd
Original Assignee
Yaesu Musen Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yaesu Musen Co Ltd filed Critical Yaesu Musen Co Ltd
Priority to JP58127106A priority Critical patent/JPS6019322A/en
Publication of JPS6019322A publication Critical patent/JPS6019322A/en
Publication of JPH059968B2 publication Critical patent/JPH059968B2/ja
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/104—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional signal from outside the loop for setting or controlling a parameter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

〔産業上の利用分野〕 本発明は、ローパスフイルタから電圧制御発振
回路に供給される誤差信号のレベルを、一定の範
囲内に制限するよう構成したPLL回路に関する
ものである。 〔従来の技術〕 従来のPLL回路において、第１図に示すよう
に入力基準信号frをVFO等の信号発生回路（図示
せず）から端子１を介して位相比較器３に入力
し、更にローパスフイルタ４及び電圧制御発振回
路５を経て端子２より発振信号fpを出力してい
た。一方、端子１に入力される入力基準信号frの
周波数変化域は、電圧制御発振回路５の最低発振
周波数と最高発振周波数により制限を受け、また
ローパスフイルタ４から前記電圧制御発振回路５
に供給される誤差信号Viが０のとき、前記電圧制
御発振回路５は自走周波数で発振し、前記入力基
準信号frの周波数と前記自走周波数との差によ
り、誤差信号Viのレベルを定めていた。そして、
前記電圧制御発振回路５から位相比較器３へ帰還
されるフイードバツク信号fd（発振信号fpの一部）
と、入力基準信号frにおける周波数及び位相が一
致したときをロツクされた状態といい、また
PLL回路で取扱う周波数帯と前記入力基準信号fr
の周波数範囲とが異なるときは、入力基準信号fr
を他の局部信号とで周波数変換する混合器を通し
て和信号か差信号にして位相比較器に入力して周
波数範囲を合わせるか、又はフイードバツク信号
fdを混合器を通して位相比較器に入力することで
PLL回路の動作に合致させていた。 〔発明が解決しようとする課題〕 上述のような従来技術では、異なる周波数範囲
のそれぞれの受持区分に属する発振周波数を得る
ためには、更に電圧制御発振回路に制御信号を供
給する回路が必要であり、第１図に示す入力基準
信号frを起源とする誤差信号ViのみのPLL回路で
は、上述のような発振周波数を得ることはできな
かつた。 本発明は、従来知られているPLL回路の、こ
のような欠点を改良する目的でなされたものであ
る。 〔課題を解決するための手段〕 本発明は第１の入力回路から誤差信号を、第２
の入力回路から制御信号を受けて発振信号の周波
数が変化する電圧制御発振回路を設け、また前記
誤差信号のレベルを中央値に対し、下限閾値と上
限閾値との間にあるように制限する制御手段を設
けることによつて前記第１の入力回路の誤差信号
のレベルを制限し、かつ、この誤差信号のレベル
が上限閾値又は下限閾値に到達して制限されるよ
うな状態になつたとき、第２の入力回路に制御信
号を送出するための検出手段としてアツプ・ダウ
ン（以下Ｕ／Ｄと記す）カウンタを設け、更に制
御信号生成手段を設けたPLL回路構成である。 〔実施例〕 本発明の実施例を第２図について詳細に説明す
る。 第１図のPLL回路のブロツク図に、誤差信号
Viを分岐して入力する誤差信号レベル制限回路１
０と、その出力のアツプ又はダウン信号を入力す
る閾値計数回路１９と、その出力をアナログに変
換するデジタルアナログ変換器（以下Ｄ／Ａ変換
器と記す）２４を設け、Ｄ／Ａ変換器２４の出力
電圧を第２の誤差信号Vi′として電圧制御発振器
（以下VCOと記す）５に供給するよう構成してあ
る。 上述の誤差信号レベル制限回路１０は、＋Vccか
ら直列に抵抗１１、定電圧ダイオード１２、逆流
阻止用のダイオード１３と１４、定電圧ダイオー
ド１５及び抵抗１６と接続し、抵抗１６の他端を
接地し、かつ、逆流阻止ダイオード１３と１４の
間をローパスフイルタ４の出力側と接続する。
又、抵抗１１と定電圧ダイオード１２の間を論理
アンプ１７の入力側と接続し、その出力側は閾値
計数回路１９の１９ａ端子に接続する。更に、定
電圧ダイオード１５と抵抗１６の中点に論理アン
プ１８の入力側を接続し、その出力側は閾値計数
回路１９の１９ｂに接続した構成である。 この誤差信号レベル制御回路１０の動作は、ロ
ーパスフイルタ４出力の誤差信号Viのレベルによ
つて３段階の動作をする。 まず下限制限動作については、ローパスフイル
タ４の誤差信号Vi出力が低く、 ＋Vcc−Vi＞定電圧ダイオードの規格値である
とVCO５の誤差信号Viの入力端子５ａに＋Vccの
電圧が抵抗１１、定電圧ダイオード１２、ダイオ
ード１３からなる回路定数で決まる電圧が供給さ
れて誤差信号Viが低くても定電圧ダイオード１２
による下限閾値以下にはならない。 次に上限制限動作については、ローパスフイル
タ４の出力する誤差信号Viが高くなり、 Vi＞定電圧ダイオード１５の規格値 であると誤差信号Viはダイオード１４、定電圧ダ
イオード１５及び抵抗１６を介して流れ、この回
路常数による電圧降下によつて定電圧ダイオード
１５による上限閾値に保たれ、誤差信号Viはそれ
以上に上昇する事はない。最後に、下限及び上限
の制約を受けない誤差信号Viの中間電圧帯では、 ＋Vcc−Vi＜定電圧ダイオード１２ Vi＜定電圧ダイオード１５ であると何の制御もうけずローパスフイルタ４の
誤差信号Vi出力の変化通りVCO５の入力端子５
ａに電圧が供給される。 上述の閾値制御と連動して、誤差信号レベル制
限回路１０は下限制限動作中は定電圧ダイオード
１２の動作により抵抗１１で電圧降下が生じた電
圧変化が論理アンプ１７を能動にして出力側をハ
イレベルとするダウン信号を出力し、上限制御用
の定電圧ダイオード１５が動作中は論理アンプ１
８の出力側をハイレベルとするアツプ信号を出力
する。 次に閾値計数回路１９について説明する。第２
図中２２はパルス発生器、２３はアツプダウンカ
ウンタ、および２０，２１のアンド回路で構成さ
れている。 この閾値計数回路１９は、誤差信号レベル制限
回路１０が下限閾値の動作中による論理アンプ１
７の出力をアンド回路２０に入力するとパルス発
生器２２のパルス信号をアンド回路２０から出力
してアツプダウンカウンタ２３のダウン端子Ｄに
入力してアツプダウンカウンタ２３をダウン修正
する。 誤差信号レベル制限回路１０が上限閾値の動作
中であればアンド回路２１からパルス信号を出力
してアツプダウンカウンタ２３のアツプ端子Ｕに
パルス信号が出力される。パルス発生器２２から
出力されるパルスの周期は、このPLL回路のロ
ツクアツプ時間よりも長い周期に設定しておけば
１パルス当り１ステツプだけ、上又は下に歩進す
る。 アツプダウンカウンタ２３の出力はＤ／Ａ変換
器２４でアナログ変換されてVCO５の５ｂ端子
に誤差信号Vi′として供給される。 VCO５はローパスフイルタ４からの誤差信号
Viを入力する5a端子の第１入力回路とＤ／Ａ変
換器２４の誤差信号Vi′を入力する５ｂ端子の第
２入力回路を設けてある。第１入力回路は端子５
ａから抵抗R1を介して、可変容量ダイオード６
と直流電流阻止用のコンデンサC1を通して発振
回路９とに接続されている。一方、第２入力回路
５ｂは抵抗R2を介して可変容量ダイオード７と
直流電流阻止のコンデンサC2を通して発振回路
９に接続されており、更に可変容量ダイオード
６，７と並列にコイル８が接続されて同調回路を
形成し、可変容量ダイオード６，７の容量変化に
応じて発振周波数が決定される。そこで誤差信号
レベル制限回路による誤差信号Viによる可変容量
ダイオード６の最大容量変化と、第２入力回路に
入力する誤差信号Vi′の１ステツプの電圧変化に
よる可変容量ダイオード７の容量変化を同じにな
るように設定しておく。 次に、第３図の周波数／電圧のグラフを用いて
第２図の回路の動作を説明する。 図のグラフはアツプダウンカウンタ２３の１ス
テツプ毎の変化によりおきる誤差信号Vi，Vi′の
変化と周波数変化を示したものである。 図において周波数1の場合を考えると、ローパ
スフイルタ４の誤差信号Viが下限閾値V1以下で
あれば定電圧ダイオード１２が動作して誤差信号
Viを下限閾値に保つとともに論理アンプ１７の出
力側をハイレベルとし、アツプダウンカウンタ２
３で１ステツプダウン補正しようとするが補正す
るデータが無いのでアツプダウンカウンタ２３の
出力は無く、従つてVCO５の第２入力回路は無
信号のため可変容量ダイオード７は最大容量値で
ある。このため、誤差信号Viは下限閾値V1レベ
ルでVCO５の第１入力回路に入り、可変容量ダ
イオード６の容量を設定し、可変容量ダイオード
６と７との容量和とコイル８とで決定される発振
周波数1でPLL回路はロツクアツプされる。 次に入力基準信号frを順次高い周波数に変化さ
せるとPLL回路のロツクアツプによる誤差信号
Vi電圧が周波数帯W1のb1の経路を通つて周波数
2まで変化する。誤差信号Vi電圧が上限閾値V2
を起えると定電圧ダイオード１５がオン動作とな
つて誤差信号Viの電圧は定電圧ダイオード１５を
介して分流されて上限閾値V2に固定され、かつ、
論理アンプ１８からアツプモードの信号を出力
（アツプダウンカウンタ２３から１ステツプのア
ツプ信号を出力し、VCO５の第２入力回路には
誤差信号Vi′が供給され可変容量ダイオード７の
容量は１ステツプ相当小さくなる。このため
VCO５は一時的に周波数2より高い周波数に変
わるので位相比較器３は入力基準信号frと位相が
合わなくなつてロツクアツプが解除される。その
ため誤差信号Viは降下して誤差信号レベル制限回
路１０によつて周波数帯W2の下限閾値V1に設定
されこの状態でVCO５の出力と入力基準信号frと
が位相整合されてPLL回路はロツクされ発振周
波数pはW2領域2に設定される。このように周
波数領域のW1，W2……においてアツプダウンカ
ウンタ２３の１ステツプ変化を誤差信号レベル制
限器１０により可変される可変容量ダイオード６
の容量変化と等量変化させるようにしておけばア
ツプ信号か、ダウン信号がアツプダウンカウンタ
２３に入力する毎にロツクアツプを解除して周波
数帯W1，W2……の隣合つた周波数領域の下限閾
値V1と上限閾値V2とに飛び移つてロツクアツプ
させる事で入力基準信号frが連続的に変化しても
PLL回路のロツクアツプに対応できるものであ
る。 なお、ダウン信号を受けてアツプダウンカウン
タ２３が下方修正された場合は、アツプ信号によ
るVCO５の発振周波数が一時的に高い周波数に
なるのに対し、Ｄ／Ａ変換器２４の電圧が下り、
可変容量ダイオード７の容量が大きくなつて一時
的に発振周波数を下げる。その為ロツクアツプが
くずれて、周波数領域W1，W2……が一段下つた
所の上限閾値の周波数となるよう可変容量ダイオ
ード６の容量が変化してPLL回路はロツクアツ
プされる。ただ入力基準信号frとVCO５の発振周
波数との位相差が大き過ぎて、誤差信号Viが下限
閾値V1又は上限閾値V2に張りついてアツプダウ
ンカウンタ２３の１ステツプでもロツクアツプし
ない時は次の１ステツプでロツクアツプすること
になる。 なお、b1曲線、b2，…曲線の受持区分W1，…
の上限と下限とが互いにオーバラツプするように
設定しておけば、閾値近傍における切換わりの動
作が安定できる。 〔発明の効果〕 本発明は、上述のようにPLL回路の誤差信号
を下限閾値と上限閾値との間に制限する誤差信号
レベル制限手段と、また前記上、下限閾値でカウ
ントモードとなるＵ／Ｄカウンタと、更にこの
Ｕ／Ｄカウンタの計数値に応じたレベルの制御信
号を電圧制御発振回路の第２の入力回路に供給す
る制御信号発生手段とを具備した構成にしてある
ため、誤差信号が一定の範囲内に保持され、かつ
前記制御信号の１ステツプごとのレベルに対応し
た動作が行える特長を有している。このため、リ
アクタンス素子を用いて、自走周波数を変更する
従来の回路に比べ、各回路素子の定数を容易に設
定できる効果がある。 [Industrial Application Field] The present invention relates to a PLL circuit configured to limit the level of an error signal supplied from a low-pass filter to a voltage controlled oscillation circuit within a certain range. [Prior Art] In a conventional PLL circuit, as shown in FIG. An oscillation signal f p was outputted from a terminal 2 via a low-pass filter 4 and a voltage-controlled oscillation circuit 5 . On the other hand, the frequency change range of the input reference signal f r input to the terminal 1 is limited by the lowest oscillation frequency and the highest oscillation frequency of the voltage controlled oscillation circuit 5, and
When the error signal V i supplied to V i is 0, the voltage controlled oscillation circuit 5 oscillates at a free running frequency, and due to the difference between the frequency of the input reference signal f r and the free running frequency, the error signal V i is The level was set. and,
Feedback signal f d (part of oscillation signal f p ) fed back from the voltage controlled oscillation circuit 5 to the phase comparator 3
When the frequency and phase of the input reference signal f r match, it is called a locked state.
Frequency bands handled by the PLL circuit and the input reference signal f r
When the frequency range differs from the input reference signal f r
pass through a mixer that converts the frequency with other local signals, convert it into a sum signal or difference signal, input it to a phase comparator to match the frequency range, or use it as a feedback signal.
By inputting f d to the phase comparator through the mixer,
It matched the operation of the PLL circuit. [Problems to be Solved by the Invention] In the above-mentioned conventional technology, in order to obtain oscillation frequencies belonging to each division of different frequency ranges, a circuit that supplies a control signal to the voltage-controlled oscillation circuit is required. Therefore, it was not possible to obtain the above-mentioned oscillation frequency with the PLL circuit using only the error signal V i originating from the input reference signal f r shown in FIG. The present invention has been made to improve these drawbacks of conventionally known PLL circuits. [Means for Solving the Problems] The present invention provides an error signal from a first input circuit to a second input circuit.
a voltage controlled oscillation circuit that changes the frequency of the oscillation signal in response to a control signal from an input circuit; and control that limits the level of the error signal to be between a lower limit threshold and an upper threshold with respect to the median value. Limiting the level of the error signal of the first input circuit by providing means, and when the level of the error signal reaches an upper threshold or a lower threshold and becomes limited, This is a PLL circuit configuration in which an up/down (hereinafter referred to as U/D) counter is provided as a detection means for sending a control signal to the second input circuit, and a control signal generation means is further provided. [Example] An example of the present invention will be described in detail with reference to FIG. The error signal is shown in the block diagram of the PLL circuit in Figure 1.
Error signal level limiting circuit 1 that branches and inputs V i
0, a threshold counting circuit 19 that inputs an up or down signal of its output, and a digital-to-analog converter (hereinafter referred to as a D/A converter) 24 that converts the output into analog. The output voltage is supplied to a voltage controlled oscillator (hereinafter referred to as VCO) 5 as a second error signal Vi ' . The error signal level limiting circuit 10 described above is connected in series from +V cc to a resistor 11, a constant voltage diode 12, diodes 13 and 14 for blocking reverse current, a constant voltage diode 15, and a resistor 16, and the other end of the resistor 16 is grounded. At the same time, the backflow blocking diodes 13 and 14 are connected to the output side of the low-pass filter 4.
Further, the resistor 11 and the constant voltage diode 12 are connected to the input side of the logic amplifier 17, and the output side thereof is connected to the 19a terminal of the threshold value counting circuit 19. Furthermore, the input side of the logic amplifier 18 is connected to the midpoint between the constant voltage diode 15 and the resistor 16, and the output side thereof is connected to 19b of the threshold value counting circuit 19. The operation of this error signal level control circuit 10 is performed in three stages depending on the level of the error signal Vi output from the low-pass filter 4. First, regarding the lower limit operation, if the error signal V i output of the low-pass filter 4 is low and +V cc −V i > the standard value of the constant voltage diode, a voltage of +V cc will be applied to the input terminal 5a of the error signal V i of the VCO 5. Even if the voltage determined by the circuit constants consisting of the resistor 11, voltage regulator diode 12, and diode 13 is supplied, and the error signal V i is low, the voltage regulator diode 12
does not fall below the lower limit threshold. Next, regarding the upper limit operation, the error signal V i output from the low-pass filter 4 becomes high, and when V i > the standard value of the voltage regulator diode 15, the error signal V i is output by the diode 14, voltage regulator diode 15, and resistor 16 The error signal V i is maintained at the upper limit threshold by the constant voltage diode 15 due to the voltage drop caused by this circuit constant, and the error signal V i does not rise any further. Finally, in the intermediate voltage band of the error signal V i which is not subject to the lower limit and upper limit constraints, if +V cc −V i < constant voltage diode 12 V i < constant voltage diode 15 , the low-pass filter 4 is switched off without any control. Input terminal 5 of VCO 5 as per change of error signal V i output
A voltage is supplied to a. In conjunction with the threshold control described above, the error signal level limiting circuit 10 operates such that during the lower limit limiting operation, the voltage change caused by the voltage drop across the resistor 11 due to the operation of the voltage regulator diode 12 activates the logic amplifier 17 and causes the output side to go high. The logic amplifier 1 outputs a down signal to set the level, and when the voltage regulator diode 15 for upper limit control is operating, the logic amplifier 1
Outputs an up signal that makes the output side of 8 high level. Next, the threshold value counting circuit 19 will be explained. Second
In the figure, 22 is a pulse generator, 23 is an up/down counter, and AND circuits 20 and 21 are constructed. This threshold value counting circuit 19 is caused by the error signal level limiting circuit 10 operating at the lower limit threshold.
When the output of 7 is inputted to the AND circuit 20, the pulse signal of the pulse generator 22 is outputted from the AND circuit 20 and inputted to the down terminal D of the up-down counter 23, and the up-down counter 23 is corrected down. If the error signal level limiting circuit 10 is operating at the upper limit threshold, the AND circuit 21 outputs a pulse signal and the pulse signal is output to the up terminal U of the up down counter 23. If the period of the pulses output from the pulse generator 22 is set to a period longer than the lock-up time of this PLL circuit, each pulse advances by one step upward or downward. The output of the up-down counter 23 is converted into analog by a D/A converter 24 and is supplied to the 5b terminal of the VCO 5 as an error signal Vi ' . VCO5 is the error signal from low pass filter 4
A first input circuit having a terminal 5a for inputting V i and a second input circuit having a terminal 5b for inputting an error signal V i ' of the D/A converter 24 are provided. The first input circuit is terminal 5
From a to the variable capacitance diode 6 through the resistor R 1
and the oscillation circuit 9 through a DC current blocking capacitor C1 . On the other hand, the second input circuit 5b is connected to an oscillation circuit 9 through a variable capacitance diode 7 and a DC current blocking capacitor C2 via a resistor R2 , and a coil 8 is connected in parallel with the variable capacitance diodes 6 and 7. to form a tuned circuit, and the oscillation frequency is determined according to the capacitance changes of the variable capacitance diodes 6 and 7. Therefore, the maximum capacitance change of the variable capacitance diode 6 due to the error signal V i by the error signal level limiting circuit is the same as the capacitance change of the variable capacitance diode 7 due to a one-step voltage change of the error signal V i ' input to the second input circuit. Set it so that Next, the operation of the circuit shown in FIG. 2 will be explained using the frequency/voltage graph shown in FIG. The graph in the figure shows changes in the error signals Vi , Vi ' and frequency changes caused by each step of the up-down counter 23. Considering the case of frequency 1 in the figure, if the error signal V i of the low-pass filter 4 is less than or equal to the lower limit threshold V 1 , the constant voltage diode 12 operates and the error signal
While keeping V i at the lower limit threshold, the output side of the logic amplifier 17 is set to high level, and the up-down counter 2
3, but since there is no data to be corrected, there is no output from the up-down counter 23. Therefore, since there is no signal in the second input circuit of the VCO 5, the variable capacitance diode 7 is at its maximum capacitance value. Therefore, the error signal V i enters the first input circuit of the VCO 5 at the lower limit threshold V 1 level, sets the capacitance of the variable capacitance diode 6, and is determined by the sum of the capacitances of the variable capacitance diodes 6 and 7 and the coil 8. The PLL circuit is locked up at an oscillation frequency of 1 . Next, when the input reference signal f r is successively changed to a higher frequency, an error signal due to lockup of the PLL circuit is generated.
The V i voltage passes through the path b 1 in the frequency band W 1 and the frequency
Varies up to 2 . The error signal V i voltage is the upper threshold V 2
occurs, the voltage regulator diode 15 turns on, and the voltage of the error signal V i is shunted through the voltage regulator diode 15 and fixed at the upper limit threshold V 2 , and
The logic amplifier 18 outputs an up-mode signal (the up-down counter 23 outputs a one-step up signal, the error signal V i ' is supplied to the second input circuit of the VCO 5, and the capacitance of the variable capacitance diode 7 increases by one step). It becomes considerably smaller.For this reason
Since the VCO 5 temporarily changes to a frequency higher than the frequency 2 , the phase comparator 3 becomes out of phase with the input reference signal fr , and lockup is released. Therefore, the error signal V i drops and is set to the lower limit threshold V 1 of the frequency band W 2 by the error signal level limiting circuit 10, and in this state, the output of the VCO 5 and the input reference signal f r are phase-matched, and the PLL circuit is locked and the oscillation frequency p is set to W2 region 2 . In this way, one step change of the up-down counter 23 in W 1 , W 2 .
If the capacitance is changed by the same amount as the change in the capacitance of By jumping between the lower threshold V 1 and the upper threshold V 2 and locking up, even if the input reference signal f r changes continuously,
It can be used to lock up PLL circuits. Note that when the up-down counter 23 is adjusted downward in response to the down signal, the oscillation frequency of the VCO 5 due to the up signal temporarily becomes a high frequency, while the voltage of the D/A converter 24 decreases.
The capacitance of the variable capacitance diode 7 increases and temporarily lowers the oscillation frequency. Therefore, the lock-up is broken, and the capacitance of the variable capacitance diode 6 is changed so that the frequency range W 1 , W 2 . However, if the phase difference between the input reference signal f r and the oscillation frequency of the VCO 5 is too large, and the error signal V i sticks to the lower limit threshold V 1 or the upper threshold V 2 and does not lock up even with one step of the up-down counter 23, the following occurs. It will be locked up in one step. In addition, the b 1 curve, b 2 ,... curve's holding division W 1 ,...
By setting the upper and lower limits of , so that they overlap with each other, the switching operation near the threshold can be stabilized. [Effects of the Invention] The present invention provides an error signal level limiting means for limiting the error signal of the PLL circuit between the lower limit threshold and the upper limit threshold, as described above, and a U/U that enters the count mode at the upper and lower limit thresholds. Since the configuration includes a D counter and control signal generating means for supplying a control signal of a level corresponding to the count value of the U/D counter to the second input circuit of the voltage controlled oscillation circuit, the error signal is is maintained within a certain range, and the operation can be performed in accordance with the level of each step of the control signal. Therefore, compared to conventional circuits that use reactance elements to change the free-running frequency, the constants of each circuit element can be easily set.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のPLL回路のブロツク図、第２
図は本発明によるPLL回路の一実施例の回路構
成図、第３図は第２図の動作を示すグラフであ
る。 １，２…端子、３…位相比較器、４…ローパス
フイルタ、５…電圧制御発振器（VCO）、６，７
…可変容量ダイオード、８…コイル、９…発振回
路、１０…誤差信号レベル制限回路、１１，１
６，R1，R2…抵抗、１２，１５…定電圧ダイオ
ード、１３，１４…ダイオード、１７，１８…論
理アンプ、２０，２１…アンド回路、２２…パル
ス発生器、２３…アツプダウンカウンタ、２４…
デジタルアナログ変換器、C1，C2…コンデンサ。 Figure 1 is a block diagram of a conventional PLL circuit, Figure 2 is a block diagram of a conventional PLL circuit.
The figure is a circuit configuration diagram of one embodiment of the PLL circuit according to the present invention, and FIG. 3 is a graph showing the operation of FIG. 2. 1, 2...Terminal, 3...Phase comparator, 4...Low pass filter, 5...Voltage controlled oscillator (VCO), 6,7
... Variable capacitance diode, 8... Coil, 9... Oscillation circuit, 10... Error signal level limiting circuit, 11, 1
6, R 1 , R 2 ... Resistor, 12, 15 ... Constant voltage diode, 13, 14 ... Diode, 17, 18 ... Logic amplifier, 20, 21 ... AND circuit, 22 ... Pulse generator, 23 ... Up-down counter, 24...
Digital-to-analog converter, C 1 , C 2 ... capacitor.

Claims (1)

【特許請求の範囲】 １ 位相比較器と、ローパスフイルタと、電圧制
御発振器とで構成し、発振周波数設定用の可変周
波数を基準信号として前記位相比較器に供給して
発振周波数と位相比較するPLL回路において、 誤差信号を出力する前記ローパスフイルタの出
力側に、電源との間に接続された下限設定用の定
電圧ダイオードを含む下限閾値回路及び基準電位
との間に接続された上限設定用の定電圧ダイオー
ドを含む上限閾値回路を配設して、前記誤差信号
出力を下限閾値と上限閾値の間に制限するととも
に前記誤差信号出力が下限閾値となつたときダウ
ン信号を出力し、前記誤差信号出力が上限閾値と
なつたときアツプ信号を出力する誤差信号レベル
制限手段と、 前記ダウン信号が入力されるとカウントダウン
し、前記アツプ信号が入力されるとカウントアツ
プするアツプダウンカウンタを備えた閾値計数回
路と、前記アツプダウンカウンタの計数値をアナ
ログ値に変換するデイジタルアナログ変換器とを
設け、また、前記電圧制御発振器は、前記誤差信
号レベル制限手段によつて制限された前記ローパ
スフイルタの出力を入力して可変容量ダイオード
の容量値を変化させる第１の入力回路と、前記ア
ツプダウンカウンタのアツプ又はダウンのワンス
テツプに対応する前記デイジタルアナログ変換器
のアナログ値毎に前記第１入力回路で可変される
最大可変容量値と等しい容量値を増減させる可変
容量ダイオード回路を有する第２入力回路を備
え、前記第１及び第２入力回路の容量値の和によ
つて発振周波数を設定するように構成されている
ことを特徴とするPLL回路。[Claims] 1. A PLL comprising a phase comparator, a low-pass filter, and a voltage controlled oscillator, which supplies a variable frequency for setting an oscillation frequency as a reference signal to the phase comparator and compares the phase with the oscillation frequency. In the circuit, on the output side of the low-pass filter that outputs the error signal, there is a lower limit threshold circuit including a constant voltage diode for lower limit setting connected between the power supply and a reference potential, and an upper limit setting circuit connected between the output side of the low pass filter and the reference potential. An upper limit threshold circuit including a voltage regulator diode is provided to limit the error signal output between the lower limit threshold and the upper limit threshold, and output a down signal when the error signal output reaches the lower limit threshold; A threshold counter comprising: error signal level limiting means for outputting an up signal when the output reaches an upper threshold; and an up-down counter that counts down when the down signal is input and counts up when the up signal is input. and a digital-to-analog converter for converting the counted value of the up-down counter into an analog value, and the voltage controlled oscillator is configured to output the output of the low-pass filter limited by the error signal level limiting means. a first input circuit that changes the capacitance value of the variable capacitance diode by inputting the input signal; a second input circuit having a variable capacitance diode circuit that increases or decreases a capacitance value equal to a maximum variable capacitance value, and is configured to set the oscillation frequency by the sum of the capacitance values of the first and second input circuits. A PLL circuit characterized by:
JP58127106A 1983-07-13 1983-07-13 Pll circuit Granted JPS6019322A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58127106A JPS6019322A (en) 1983-07-13 1983-07-13 Pll circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58127106A JPS6019322A (en) 1983-07-13 1983-07-13 Pll circuit

Publications (2)

Publication Number Publication Date
JPS6019322A JPS6019322A (en) 1985-01-31
JPH059968B2 true JPH059968B2 (en) 1993-02-08

Family

ID=14951747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58127106A Granted JPS6019322A (en) 1983-07-13 1983-07-13 Pll circuit

Country Status (1)

Country Link
JP (1) JPS6019322A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6248121A (en) * 1985-08-27 1987-03-02 Furuno Electric Co Ltd Frequency synthesizer

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5320980Y2 (en) * 1977-03-10 1978-06-02

Also Published As

Publication number Publication date
JPS6019322A (en) 1985-01-31

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