JPH059515U - DC correction device for digital phasing adder - Google Patents

Abstract

(57) [Abstract] [Purpose] To obtain a simple and inexpensive DC compensator for a digital phasing adder that corrects the DC offset component generated in the output of the digital phasing adder. A plurality of ADCs 3 each for obtaining sampling data from a reception signal for each ultrasonic detecting element, a digital phasing adder 4 for performing a phasing addition operation of the sampling data, and a digital phasing adder 4 are provided. A DAC 8 for converting output data into an analog DC voltage, and a DC voltage smoothing means 9 for negatively feeding back the offset correction signal obtained by smoothing the analog DC voltage to the respective input terminals of the plurality of ADCs 3.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

  The present invention is a digital phasing adder that performs beamforming of ultrasonic received signals. The present invention relates to a DC correction device.

[0002]

[Prior art]

  Recently, digital receiving beamforming equipment has been used in ultrasonic diagnostic equipment. Is starting to appear. At this time, the signals detected by each detection element of the ultrasonic probe are received. The echo signal of the reception frequency (generally called the RF frequency) is directly converted to analog / digital. In many cases, the sampled data is obtained by quantization through a converter (hereinafter referred to as ADC). However, in this case, the digital beam forming process is performed using the sampling data. DC offset generation that occurs when (this is also called digital phasing addition processing) Needed a minute correction.

[0003]   FIG. 3 is a block diagram showing an example of a DC correction device for a conventional digital phasing adder. It In the figure, 1 is n (for example, 64, 128, 256, etc.) transmitting / receiving vibrations. This is an ultrasonic probe in which pendulums are arrayed. 2 is a preamplifier (hereinafter referred to as PA ) Unit corresponding to # 1 to #n transducers in the ultrasonic probe 1 Each PA, including # 1 to #nPA, The signal is individually amplified and output. Reference numeral 3 is an ADC unit, and the above-mentioned # 1 to #nPA # 1 to #n ADC respectively corresponding to. Each ADC is externally supplied R An input analog based on a sampling clock signal of, for example, 20 to 40 MHz for the F frequency. The digital signal is sequentially converted into, for example, 8-bit digital data and output. In this example # 1 to #n ADC are 8-bit samples for each sampling cycle of 20 to 40 MHz. The converted data is supplied to the digital beam former 4.

[0004]   Reference numeral 4 in FIG. 3 denotes a digital beam former, which receives a wave at a predetermined scanning direction and distance. Samples sequentially supplied from the # 1 to #n ADCs in order to focus the beam. After giving a predetermined delay time for each digitized data, add it and add it up (eg 16 bits) Data value). Therefore, variable delay processing and addition processing for each channel data Logic through either digital hardware or programmatic software. It is something to do. Reference numeral 5 is a Doppler signal processing unit, and the measured object is, for example, a blood vessel. When there is a velocity component like blood flow, the velocity signal is detected from the Doppler shift frequency. It is something to put out. Reference numeral 6 is a logarithmic compressor. In this example, the input 16-bit data is The data is compressed by a logarithmic characteristic and output as 8-bit data. 7 is detection It detects the input data and outputs it as a B-mode image signal. here The logarithmic compressor 6 and the detector 7 are B-mode image system devices.

[0005]   Reference numeral 12 in FIG. 3 denotes a digital filter, which is output to the output of the digital beam former 4. High-pass filter (hereinafter referred to as HPF) for removing the offset DC offset component ) Or bandpass filter (hereinafter referred to as BPF) digital signal processing It is a thing.   In addition, a digital filter is provided on the output side of this digital beamformer as a DC correction device. The method of providing the filter is one of the conventional solutions, and when this is called the first method, In addition to this, the following second method and third method are also conceivable.   The second method is to use HPF or BPF provided on the output side of each ADC. The DC components are individually removed.   The third method is to integrate the DC component with an integrator provided on the output side of each ADC. After that, the data is converted via the digital / analog converter (hereinafter referred to as DAC). The log signal is negatively fed back to the input side of each ADC.

[0006]

[Problems to be solved by the device]

  However, in the DC correction device of the conventional digital phasing adder as described above, the following There was such a problem.   When the digital filter according to the first method is used as the DC correction device, phasing addition is performed. The dynamic range of the output signal due to Since one word of output data is at least 12 to 16 bits, this bit Digital filters that process large amounts of data are complex and large-scale devices. I will   The case of using the HPF or BPF according to the second method as the DC correction device, and the case of the third method When using the integrator and DAC by the DC method as the DC correction device, both are It is necessary to provide as many detectors as the number of detectors included in the module, and high cost due to an increase in the number of parts It becomes a device.

[0007]   The present invention has been made to solve such a problem, and it can be applied to ultrasonic wave reception signals, etc. DC offset generated at the output of a digital phasing adder that performs beamforming The aim is to obtain a DC compensation device for a digital phasing adder that is simple and inexpensive to compensate components. Target

[0008]

[Means for Solving the Problems]

A DC compensator for a digital phasing adder according to claim 1 of the present invention is an ultrasonic probe. The received signal obtained from each detector element in the A plurality of analog / digital converters that output sampled data by Digital phasing of sampled data output by log / digital converter The digital phasing adder that performs the arithmetic operation and the arithmetic result of the digital phasing adder Digital-analog converter that converts the digital data output as And the analog DC voltage output from the digital-analog converter , The smoothed DC voltage as an offset correction signal Equipped with DC voltage smoothing means for negative feedback to each input terminal of digital converter It is a thing.

[0009]   The DC compensator of the digital phasing adder according to claim 2 of the present invention is an ultrasonic probe. Quantize the received signal obtained from each detection element in A plurality of analog / digital converters that output sampled data by Digital phasing of sampled data output by each analog / digital converter A digital phasing adder that performs addition operation and a sampling with a predetermined sampling period Sampling pulse generator for generating a ring pulse, and the sampling pulse Operation of the digital phasing adder by sampling pulse supplied from the generator As a result, a data latch circuit for latching digital data to be output, and the data latch circuit The digital data latched by the data latch circuit and output is converted into an analog DC voltage. Digital-to-analog converter and the analog output from the digital-to-analog converter. The log DC voltage is smoothed, and the smoothed DC voltage is used as an offset correction signal. DC power for negative feedback to the respective input terminals of the plurality of analog / digital converters And pressure smoothing means.

[0010]

[Action]

  In the device according to claim 1, the plurality of analog / digital converters are ultrasonic waves. Received signals obtained from each detection element in the probe are sampled at predetermined sampling intervals. Quantize and output sampled data. The digital phasing adder is the plurality of analog -Digital phasing addition operation for the sampled data output by each digital converter Perform arithmetic. The digital-to-analog converter and the operation result of the digital phasing adder Then, the digital data output is converted into an analog DC voltage. DC voltage smoother The stage smoothes the analog DC voltage output from the digital-analog converter, The smoothed DC voltage is used as an offset correction signal for the plurality of analog / digital converters. Negative feedback to each input terminal of the converter.

[0011]   In the device according to claim 2, the plurality of analog / digital converters are ultrasonic waves. Received signals obtained from each detection element in the probe are sampled at predetermined sampling intervals. Quantize and output sampled data. The digital phasing adder is the plurality of analog -Digital phasing addition operation for the sampled data output by each digital converter Perform arithmetic. The sampling pulse generator is a sampling pulse generator with a predetermined sampling period. Generate a ring pulse. Is the data latch circuit the sampling pulse generator? As the calculation result of the digital phasing adder by the sampling pulse supplied from Latch the digital data to be output. The digital / analog converter is The digital data latched by the data latch circuit and output is converted into an analog DC voltage. It The DC voltage smoothing means is an analog direct output from the digital-analog converter. Current is smoothed, and the smoothed DC voltage is used as the offset correction signal to convert the Negative feedback to each input terminal of the analog-to-digital converter of the number.

[0012]

【Example】

  FIG. 1 is a block diagram of a DC correction device for a digital phasing adder showing a first embodiment of the present invention. 3 is the same as the device in FIG. 8 is DAC (digital Analog converter). Now the digital beam former 4 is When 16-bit digital data is output as output data, the DAC8 6-bit digital data is converted to analog DC voltage (for example, full span 0 to 5VDC , Or 0-10 VDC) and output. 9 is an integrator or LPF , The fluctuation of the output voltage of the DAC8 is removed to form a smoothed DC voltage, which is Negative feedback is provided to the input side of each ADC in the DC unit 3. This negative feedback signal is Offset DC component included in echo signal input from PA to corresponding ADC Is applied to each ADC to correct the sum of the Acts to remove the DC offset component generated on the output side of the beamformer 4. To do.

[0013]   FIG. 2 is a block diagram of a DC correction device for a digital phasing adder showing a second embodiment of the present invention. 1 to 9 are the same as the device of FIG. 10 is a data latch circuit And 16-bit data output from the digital beam former 4 is sampled. Each time a pulse is input, it is latched and this is input to the next sampling pulse. Hold in. Then, the held data is supplied to the DAC 8. 11 is a sample This is a sampling pulse generator that generates sampling pulses with a cycle described later It is supplied to the latch circuit 10. Of the pulses generated by the sampling pulse generator 11 The frequency or period has no correlation with the ultrasonic carrier frequency or repetition frequency. Of a short period that is shorter than the response time of the integrator 9 (or LPF). Ring pulses are used. Further, as the sampling pulse generator 11, The period in which the sampling pulse is generated may not be constant but may change randomly. For example, a pseudo random number whose cycle length and chip rate meet the above required specifications. A sound sequence generator or the like can be used. In this case the sampling pulse The generation cycle is not constant, but changes randomly to some extent, so naturally the ultrasonic wave It is possible to obtain sampling pulses that have no correlation with the carrier frequency or repetition frequency. it can. Thus, even if the sampling pulse generation period is constant, it is not constant. Either or both may be used.

[0014]   Moreover, in this case, the input speed of the data input to the DAC 8 should not be so high. Therefore, although the DAC8 has high precision for audio, for example, it has a relatively high response speed. Slow elements can be used.   In the embodiment of FIG. 2, the offset DC component correction signal that is fed back to each ADC is The fluctuation rate is reduced to stabilize the negative feedback loop control system.

[0015]   In the embodiment described above, the offset DC component is disclosed as the best mode disclosure. The correction signal is shown as an example in which the negative feedback is equally fed back to all ADCs. Is not limited to this.   For example, the negative feedback of the correction signal is applied to most ADCs or at most some ADCs. Or equivalent weighting results will give almost equivalent results. What can be obtained is obvious to experienced persons and those skilled in the art, and even with such a method The device can be implemented.   The above method is a method for uniformly negatively feeding back the correction signal to all ADCs shown in the embodiment. The point that is inferior to the case of the automatic mode is that the range of the correctable offset amount is narrowed at most. It

[0016]

[Effect of device]

  As described above, according to the present invention, the receiving device obtained from each detecting element in the ultrasonic probe is obtained. Digital phasing of sampled data obtained by quantizing the received signal at each predetermined sampling period The digital phasing is performed for a plurality of analog-to-digital converters supplied to the adder. The digital data output as the result of the adder operation is converted to a digital-to-analog converter. Converted to analog DC voltage, and then converted to DC voltage smoothing means such as an integrator. Note that the analog DC voltage is smoothed so that each offset correction signal is negatively fed back. DC compensation of digital phasing adder that can be configured with simple and inexpensive equipment The device can be obtained.

[0017]   Furthermore, according to the present invention, the sampling data is supplied to a digital phasing adder. Number of analog-to-digital converter Latch the digital data output as the calculation result of the digital phasing adder, The latched digital data is converted to analog DC power by a digital-analog converter. The analog DC voltage by converting it into a voltage and then using a DC voltage smoothing means such as an integrator. Since the offset correction signals smoothed by are fed back negatively, This negative feedback loop reduces the fluctuation rate of the offset DC component correction signal of the calculator. The control system is stabilized.

[Brief description of drawings]

FIG. 1 is a block diagram of a DC correction device of a digital phasing adder showing a first embodiment of the present invention.

FIG. 2 is a block diagram of a DC correction device for a digital phasing adder showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing an example of a conventional DC correction device for a digital phasing adder.

[Explanation of symbols]

1 Ultrasonic probe 2 PA unit 3 ADC unit 4 Digital beam former 5 Doppler signal processor 6 logarithmic compressor 7 Detector 8 DAC 9 Integrator 10 Data latch circuit 11 Sampling pulse generator 12 Digital filter

Claims (2)

[Scope of utility model registration request] 1. A plurality of analog-to-digital converters for quantizing a reception signal obtained from each detection element in an ultrasonic probe for each predetermined sampling period and outputting sampled data, and a plurality of said analog-to-digital converters. A digital phasing adder that performs a digital phasing addition operation on the sampled data output by each digital converter, and a digital-analog conversion that converts the digital data output as the operation result of the digital phasing adder into an analog DC voltage. And a DC voltage for smoothing the analog DC voltage output from the digital-analog converter and negatively feeding back the smoothed DC voltage as an offset correction signal to the respective input terminals of the plurality of analog-digital converters. A DC correction device for a digital phasing adder, comprising: a smoothing means. 2. A plurality of analog-to-digital converters for quantizing a reception signal obtained from each detection element in the ultrasonic probe for each predetermined sampling period and outputting sampled data, and the plurality of analog-to-digital converters. A digital phasing adder that performs a digital phasing addition operation on the sampled data output by each digital converter, a sampling pulse generator that generates a sampling pulse at a predetermined sampling period, and a sampling pulse generator A data latch circuit for latching digital data output as a calculation result of the digital phasing adder by a sampling pulse; and a digital-analog converter for converting digital data latched and output by the data latch circuit into an analog DC voltage. , Output of the digital / analog converter And a DC voltage smoothing means for negatively feeding back the smoothed DC voltage as an offset correction signal to the respective input terminals of the plurality of analog-digital converters. DC compensation device for digital phasing adder.