JPH0593038U - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0593038U JPH0593038U JP4023192U JP4023192U JPH0593038U JP H0593038 U JPH0593038 U JP H0593038U JP 4023192 U JP4023192 U JP 4023192U JP 4023192 U JP4023192 U JP 4023192U JP H0593038 U JPH0593038 U JP H0593038U
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- JP
- Japan
- Prior art keywords
- semiconductor chip
- metal particles
- solder
- connection conductor
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
(57)【要約】
【目的】 半導体チップと放熱性を有する接続導体との
間の半田層を所望厚さにする。
【構成】 接続導体１に半導体チップ３を半田２で固着
する時に、半田２に金属粒５を混入する。金属粒５が半
導体チップ３の下から外に流出することを防止するため
に半導体チップ３の外側部分の下に対応させて接続導体
１に環状の溝部４を形成する。
(57) [Abstract] [Purpose] A solder layer between a semiconductor chip and a connection conductor having a heat dissipation property has a desired thickness. [Structure] When the semiconductor chip 3 is fixed to the connection conductor 1 with the solder 2, the metal particles 5 are mixed into the solder 2. In order to prevent the metal particles 5 from flowing out from under the semiconductor chip 3, an annular groove 4 is formed in the connection conductor 1 under the outer portion of the semiconductor chip 3.
Description
【０００１】[0001]
本考案は接続導体に対して半導体チップを最適な厚みのろう材層を介して固着 した構造の半導体装置に関する。 The present invention relates to a semiconductor device having a structure in which a semiconductor chip is fixed to a connecting conductor via a brazing material layer having an optimum thickness.
【０００２】[0002]
電力用半導体装置では放熱効果を良好に得るために半導体チップを金属製放熱 板に半田付けする。この時、半導体チップと放熱板の間に介在する半田の厚みは 良好な放熱性が得られ且つ熱ストレスも良好に吸収できる最適な値に設定される 。これを実現するために、スペーサとして機能する金属粒を混入した半田を使用 して半導体チップを放熱板に固着することがある。 In power semiconductor devices, semiconductor chips are soldered to metal heat sinks in order to obtain good heat dissipation effects. At this time, the thickness of the solder interposed between the semiconductor chip and the heat radiating plate is set to an optimum value capable of obtaining good heat dissipation and also satisfactorily absorbing thermal stress. To achieve this, the semiconductor chip may be fixed to the heat sink using solder mixed with metal particles that function as spacers.
【０００３】[0003]
しかしながら、金属粒が半田と共に半導体チップの下面から流出し、半田層の 厚みを所望値にできないことがある。半田中の金属粒の含有量を増大すれば、上 記問題はある程度解決できるが、含有量の増大によって半田層中のボイドが増大 し、熱伝導率が低下するという問題が生じる。また、所定粒径の金属粒は比較的 に高価になるので、この使用量が増大すると半導体装置のコストが必然的に高く なる。 However, the metal particles may flow out from the lower surface of the semiconductor chip together with the solder, and the thickness of the solder layer may not reach a desired value. The above problem can be solved to some extent by increasing the content of the metal particles in the solder, but the increase in the content causes an increase in voids in the solder layer, resulting in a problem that the thermal conductivity decreases. Further, since metal particles having a predetermined particle diameter become relatively expensive, the cost of the semiconductor device inevitably increases as the amount of use increases.
【０００４】 そこで、本考案の目的は半導体チップと接続導体との間のろう材の中に金属粒 を良好に介在させ、所望厚さのろう材層を確実に得ることができる半導体装置を 提供することにある。Therefore, an object of the present invention is to provide a semiconductor device capable of reliably obtaining a brazing material layer having a desired thickness by properly interposing metal particles in a brazing material between a semiconductor chip and a connection conductor. To do.
【０００５】[0005]
上記目的を達成するための本考案は、半導体チップが金属粒を含むろう材によ って接続導体の主面上に固着された半導体装置において、前記接続導体の主面の 前記半導体チップに対向している領域内に前記金属粒の流出を防止する部分が設 けられていることを特徴とする半導体装置に係わるものである。 なお、請求項２に示すように、流出を防止する部分を環状に形成された溝部と し、あらゆる方向への金属粒の流出を確実に防止することができる。 また、請求項３に示すように、流出を防止する部分を環状に配設した突起とし 、あらゆる方向への金属粒の流出を防止することができる。 また、請求項４に示すように、半導体チップに対向させて窪み部を設け、この 壁によって金属粒の流出を防止し、窪み部の中に金属粒をとじ込めるように構成 することができる。 また、請求項５に示すように、流出をを防止する部分を多数の凹凸を有する面 （例えば梨地加工面）とし、半導体チップの外への流出防止のみでなく、半導体 チップ下面領域内においての金属粒の移動も防止することができる。 The present invention for achieving the above object provides a semiconductor device in which a semiconductor chip is fixed on a main surface of a connection conductor by a brazing material containing metal particles, and the semiconductor chip on the main surface of the connection conductor faces the semiconductor chip. The present invention relates to a semiconductor device characterized in that a portion for preventing the metal particles from flowing out is provided in the region where the metal particles are present. As described in claim 2, the portion for preventing the outflow is a groove formed in an annular shape, so that the outflow of the metal particles in all directions can be surely prevented. Further, as described in claim 3, the portion for preventing the outflow is a protrusion arranged in an annular shape, so that the outflow of the metal particles in all directions can be prevented. Further, as described in claim 4, it is possible to provide a recessed portion facing the semiconductor chip, prevent the metal particles from flowing out by this wall, and confine the metal particles in the recessed portion. Further, as described in claim 5, the portion for preventing the outflow is a surface having a large number of irregularities (for example, a satin processed surface), and not only for preventing the outflow of the semiconductor chip to the outside, but also in the lower surface area of the semiconductor chip. The movement of metal particles can also be prevented.
【０００６】[0006]
各請求項の考案によれば、接続導体の主面に金属粒の流出を防止する部分を設 けたので、ろう材が流動しても金属粒が半導体チップの下面から外に流出しない 。従って、金属粒のスペーサ効果を維持し、所望厚さのろう材層を得ることがで きる。 According to the invention of each claim, since the portion for preventing the metal particles from flowing out is provided on the main surface of the connecting conductor, the metal particles do not flow out from the lower surface of the semiconductor chip even if the brazing material flows. Therefore, the spacer effect of the metal particles can be maintained and a brazing material layer having a desired thickness can be obtained.
【０００７】[0007]
【第１の実施例】 次に、図１及び図２を参照して第１の実施例に係わる電力用整流素子を説明す る。図１の整流素子は放熱性を有する金属製平板から成る接続導体１にろう材と しての半田２を介して半導体チップ３を固着することによって構成されている。 放熱性を有する接続導体１は平面的に見て円形の半導体チップ３の外縁よりも少 し内側に対応する位置に形成された環状溝部４を有する。半田２は粒径が約２０ μｍのニッケル（Ｎi ）粒子からなるほぼ球形の金属粒５を１０重量％含む。こ の金属粒５の融点はＰb −Ｓn 半田２のそれよりも高い。なお、金属粒５の直径 は２０〜６０μｍの範囲とし、この半田に対する含有率は２０重量％以下にする ことが望ましい。平板状の半導体チップ３はｐｎ接合を有する半導体層３ａと、 この上下の主面に形成された一対の金属電極層３ｂ、３ｃとから成り、下側の金 属電極層３ｂが半田２で接続導体１の主面に固着されている。First Embodiment Next, a power rectifying device according to the first embodiment will be described with reference to FIGS. 1 and 2. The rectifying element shown in FIG. 1 is constructed by fixing a semiconductor chip 3 to a connecting conductor 1 made of a metal flat plate having a heat dissipation property via a solder 2 as a brazing material. The heat-dissipating connection conductor 1 has an annular groove 4 formed at a position corresponding to the inner side of the outer edge of the semiconductor chip 3 which is circular in plan view. The solder 2 contains 10 wt% of substantially spherical metal particles 5 made of nickel (Ni) particles having a particle size of about 20 μm. The melting point of the metal particles 5 is higher than that of the Pb-Sn solder 2. It is desirable that the diameter of the metal particles 5 be in the range of 20 to 60 μm, and that the content of this metal in the solder be 20% by weight or less. The flat semiconductor chip 3 is composed of a semiconductor layer 3a having a pn junction and a pair of metal electrode layers 3b and 3c formed on the upper and lower main surfaces, and the lower metal electrode layer 3b is connected by a solder 2. It is fixed to the main surface of the conductor 1.
【０００８】 金属粒５の流出防止部分として働く接続導体１の溝部４の幅Ｗは金属粒５の直 径Ｄよりも若干小さく形成されている。The width W of the groove portion 4 of the connecting conductor 1 which functions as a portion for preventing the metal particles 5 from flowing out is formed to be slightly smaller than the diameter D of the metal particles 5.
【０００９】 半導体チップ３を接続導体１の主面に固着する際には、接続導体１の主面の半 導体チップ固着予定領域上に、金属粒５を含む半田箔を載置し、この上に半導体 チップ３を載置し、半田箔を溶融させる。この時、半田箔の量は最終的に半導体 チップ３と接続導体１との間に介在させたい半田量以上にする。半田箔を溶融す ると半田の流動が生じ、金属粒５も流動するが、外方向に流動した金属粒５は溝 部４に捕獲され、この一部が溝部４に入り込み、これ以上外に流動しない。溝部 ４の幅Ｗは金属粒５の径Ｄよりも小さく、且つ溝部４の深さは金属粒５の径Ｄよ りも浅いので、溝部４に入り込んだ金属粒５の一部が接続導体１の表面から突出 し、これが別の金属粒５の流出防止部分として機能する。溝部４に入り込んだ金 属粒５はスペーサとしての機能を持たないが、ここに入り込まない金属粒５はス ペーサとしての機能を有し、この直径Ｄが半田２の層厚となり、半田２の層の厚 さを所望値にすることができる。また、半導体チップ３を固着した後に半田２が 再溶融されたとしても半田２の厚さの変化が生じない。なお、半田付け時に、半 導体チップ３を接続導体１に対して加圧してもよいし、しなくてもよい。しかし 、加圧すると、金属粒５は移動しにくくなるが、半田２中の気泡も抜けにくくな る。本実施例では溝部４で金属粒５の移動を阻止しているので、気泡の放出を円 滑に進めるために特別に加圧しない半田付け方法を採用することができる。When the semiconductor chip 3 is fixed to the main surface of the connecting conductor 1, a solder foil containing metal particles 5 is placed on the semi-conductor chip fixing area of the main surface of the connecting conductor 1, The semiconductor chip 3 is placed on and the solder foil is melted. At this time, the amount of solder foil is finally set to be equal to or larger than the amount of solder to be interposed between the semiconductor chip 3 and the connection conductor 1. When the solder foil is melted, the solder flows, and the metal particles 5 also flow, but the metal particles 5 that have flowed outward are captured by the groove portion 4, part of which enters the groove portion 4 and further outside. It doesn't flow. Since the width W of the groove 4 is smaller than the diameter D of the metal grain 5 and the depth of the groove 4 is shallower than the diameter D of the metal grain 5, part of the metal grain 5 that has entered the groove 4 is the connecting conductor 1. Of the metal particles 5 and functions as an outflow preventing portion for other metal particles 5. The metal particles 5 that have entered the groove portion 4 do not have a function as a spacer, but the metal particles 5 that do not enter here have a function as a spacer, and this diameter D becomes the layer thickness of the solder 2 and The layer thickness can be as desired. Further, even if the solder 2 is remelted after the semiconductor chip 3 is fixed, the thickness of the solder 2 does not change. Note that the semiconductor chip 3 may or may not be pressed against the connection conductor 1 during soldering. However, when pressure is applied, the metal particles 5 are less likely to move, but bubbles in the solder 2 are also less likely to escape. In this embodiment, since the movement of the metal particles 5 is blocked by the groove portion 4, it is possible to adopt a soldering method in which no special pressure is applied in order to smoothly promote the emission of bubbles.
【００１０】[0010]
【第２の実施例】 次に、図３に示す第２の実施例の整流素子を説明する。但し、図３及び後述す る図４及び図５において図１及び図２と共通する部分には同一の符号を付してそ の説明を省略する。図３の実施例では放熱性を有する接続導体１の表面に図１の 溝部４の代りに突起部６が設けられている。この突起部６の形成位置は溝部４の 位置と同様に半導体チップ３の外縁よりも少し内側であり、溝部４と同様に環状 に形成されている。この突起部６の高さＨは金属粒５の直径Ｄよりも小さい。こ の突起部６はこの形成予定領域の外側に第１の型を配置し、形成予定領域の内側 を第２の型で加圧することによって形成する。これにより、突起部６の内側には 接続導体１の別の主面よりも少し低い面７が生じている。この突起部６は加圧加 工に限ることなく、切削加工、エッチング等で形成し得る。Second Example Next, a rectifying element of a second example shown in FIG. 3 will be described. However, in FIG. 3 and later-described FIGS. 4 and 5, the same parts as those in FIGS. 1 and 2 are designated by the same reference numerals and the description thereof will be omitted. In the embodiment shown in FIG. 3, a projection 6 is provided on the surface of the connection conductor 1 having heat dissipation properties instead of the groove 4 shown in FIG. The formation position of the protrusion 6 is slightly inside the outer edge of the semiconductor chip 3 similarly to the position of the groove 4, and is formed in an annular shape like the groove 4. The height H of the protrusion 6 is smaller than the diameter D of the metal grain 5. The protrusion 6 is formed by arranging the first mold outside the region to be formed and pressing the inside of the region to be formed with the second mold. As a result, a surface 7 slightly lower than the other main surface of the connecting conductor 1 is formed inside the protrusion 6. The protrusion 6 can be formed by cutting, etching or the like without being limited to pressure processing.
【００１１】 半導体チップ３を半田２で接続導体１に固着する際には、半田２に含まれてい る金属粒５の外側への流出が環状配置の突起部６により制限される。この結果、 突起部６の内側に所定量の金属粒５が残存し、スペーサとして機能し、第１の実 施例と同一の作用効果が得られる。When the semiconductor chip 3 is fixed to the connection conductor 1 with the solder 2, the outflow of the metal particles 5 contained in the solder 2 to the outside is restricted by the protruding portion 6 arranged in an annular shape. As a result, a certain amount of metal particles 5 remain inside the protrusions 6, function as spacers, and the same effect as the first embodiment can be obtained.
【００１２】[0012]
【第３の実施例】 図４に示す第３の実施例の整流素子においては、図２の溝部４の内側に対応す るように接続導体１の主面に窪み部８が形成されている。この窪み部８の深さＡ は金属粒５の直径Ｄよりも小さい。従って、窪み部８内の金属粒５は接続導体１ の他の主面よりも突出し、半導体チップ３のスペーサとして機能し、接続導体１ と半導体チップ３との間の半田２の厚みが所望値になる。なお、窪み部８は半導 体チップ３の下面に対応するように配設されているので、窪み部８内の金属粒５ は半田付け時に流動しても窪み部８の壁面で制限され、これより外には流動しな い。Third Embodiment In the rectifying element of the third embodiment shown in FIG. 4, a depression 8 is formed on the main surface of the connecting conductor 1 so as to correspond to the inside of the groove 4 of FIG. .. The depth A of the recess 8 is smaller than the diameter D of the metal grain 5. Therefore, the metal particles 5 in the recess 8 project from the other main surface of the connection conductor 1 and function as a spacer of the semiconductor chip 3, and the thickness of the solder 2 between the connection conductor 1 and the semiconductor chip 3 is a desired value. become. Since the recess 8 is arranged so as to correspond to the lower surface of the semiconductor chip 3, the metal particles 5 in the recess 8 are restricted by the wall surface of the recess 8 even if they flow during soldering. It does not flow outside this.
【００１３】[0013]
【第４の実施例】 図５に示す第４の実施例においては、接続導体１の半導体チップ３の下面に対 応するほぼ全領域が梨地加工面からなる凹凸面９である。凹凸面９は金属粒５の 直径Ｄよりも小さい高さ及び深さを有する多数の凹部と凸部とを有する。半導体 チップ３を接続導体１に半田付けする際に金属粒５が流動しようとしても、凹凸 面９の凹凸によってこの流動が制限され、半導体チップ３と接続導体１との間に 所望量の金属粒５を残存させることができる。Fourth Embodiment In a fourth embodiment shown in FIG. 5, almost the entire area of the connection conductor 1 corresponding to the lower surface of the semiconductor chip 3 is an uneven surface 9 made of a matte surface. The uneven surface 9 has a large number of concave portions and convex portions having a height and a depth smaller than the diameter D of the metal particles 5. Even if the metal particles 5 try to flow when the semiconductor chip 3 is soldered to the connection conductor 1, the flow of the metal particles 5 is limited by the unevenness of the uneven surface 9, so that a desired amount of metal particles can be provided between the semiconductor chip 3 and the connection conductor 1. 5 can remain.
【００１４】[0014]
本考案は上述の実施例に限定されるものでなく、例えば次の変形が可能なもの である。 （１） 整流素子に限ることなく、トランジスタ、サイリスタ等にも適用可能 である。 （２） 図１及び図２の溝部４及び図３の突起部６を完全な環状とせずに、不 連続部分を有して実質的に環状に形成してもよい。なお、溝部４又は突起部６の 不連続になる部分の幅は金属粒５の直径以下にすることが望ましい。 （３） 図６に示すように、半導体チップ３の上に金属粒５を含む半田箔２ａ 及び接続導体１を配置し、半田箔２ａを溶融することができる。特別に加圧しな い場合には半田よりも比重の小さい金属粒５が溶融半田の上側に浮いた状態とな り、流出しようとするが、半田の上側に配置された接続導体１の流出防止手段と しての凹凸面９の凹凸によって金属粒５の流出が効果的に防止される。この種の 方法は、図１、図３、図４の各実施例にも採用することができる。 （４） 半導体チップ３の下面の面積が大きい場合には、半導体チップ３の下 方の複数（好ましくは３以上）の環状溝部又は環状突起又は窪み部を配置し、こ れ等の中から金属粒が流出することを防ぎ、半導体チップ３の下方の特定された 複数箇所に金属粒５を配置することができる。 The present invention is not limited to the above-mentioned embodiment, and the following modifications are possible, for example. (1) The invention is not limited to rectifying devices, but can be applied to transistors, thyristors, and the like. (2) The grooves 4 in FIGS. 1 and 2 and the protrusion 6 in FIG. 3 may be formed in a substantially annular shape having a discontinuous portion, instead of being formed in a perfect annular shape. The width of the discontinuous portion of the groove 4 or the protrusion 6 is preferably equal to or smaller than the diameter of the metal grain 5. (3) As shown in FIG. 6, the solder foil 2a containing the metal particles 5 and the connection conductor 1 are arranged on the semiconductor chip 3, and the solder foil 2a can be melted. If no special pressure is applied, the metal particles 5 having a smaller specific gravity than the solder will float above the molten solder and attempt to flow out, but prevent the connection conductor 1 placed above the solder from flowing out. The unevenness of the uneven surface 9 as a means effectively prevents the metal particles 5 from flowing out. This type of method can also be adopted in the embodiments of FIGS. 1, 3, and 4. (4) When the area of the lower surface of the semiconductor chip 3 is large, a plurality (preferably 3 or more) of annular groove portions or annular protrusions or depressions on the lower side of the semiconductor chip 3 are arranged, and a metal is selected from these. The particles can be prevented from flowing out, and the metal particles 5 can be arranged at a plurality of specified locations below the semiconductor chip 3.
【図１】第１の実施例の整流素子を示す断面図である。FIG. 1 is a cross-sectional view showing a rectifying element of a first embodiment.
【図２】図１の接続導体の平面図である。2 is a plan view of the connection conductor of FIG. 1. FIG.
【図３】第２の実施例の整流素子を示す断面図である。FIG. 3 is a cross-sectional view showing a rectifying element of a second embodiment.
【図４】第３の実施例の整流素子を示す断面図である。FIG. 4 is a cross-sectional view showing a rectifying element of a third embodiment.
【図５】第４の実施例の整流素子を示す断面図である。FIG. 5 is a sectional view showing a rectifying element of a fourth embodiment.
【図６】変形例の半田付け方法を示す断面図である。FIG. 6 is a sectional view showing a soldering method of a modified example.
１ 接続導体 ２ 半田 ３ 半導体チップ ４ 溝部 ５ 金属粒 1 Connection Conductor 2 Solder 3 Semiconductor Chip 4 Groove 5 Metal Grain
フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 23/373 Ｈ０１Ｌ 23/36 Ｍ Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI Technical display area H01L 23/373 H01L 23/36 M
Claims (5)
って接続導体の主面上に固着された半導体装置におい
て、 前記接続導体の主面の前記半導体チップに対向している
領域内に前記金属粒の流出を防止する部分が設けられて
いることを特徴とする半導体装置。1. A semiconductor device in which a semiconductor chip is fixed on a main surface of a connection conductor by a brazing material containing metal particles, wherein the metal particle is provided in a region of the main surface of the connection conductor facing the semiconductor chip. A semiconductor device, which is provided with a portion for preventing the outflow of liquid.
チップの外縁に沿って実質的に環状に形成された溝部で
ある請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the portion for preventing the outflow is a groove portion formed in a substantially annular shape along an outer edge of the semiconductor chip.
チップの外縁に沿って実質的に環状に配設され且つ前記
金属粒の径よりも低い高さを有している突起である請求
項１記載の半導体装置。3. The protrusion for preventing the outflow is a protrusion which is arranged in a substantially annular shape along the outer edge of the semiconductor chip and has a height lower than the diameter of the metal particles. 1. The semiconductor device according to 1.
チップに対向するように前記接続導体の主面に形成され
た窪み部の壁である請求項１記載の半導体装置。4. The semiconductor device according to claim 1, wherein the portion for preventing the outflow is a wall of a recessed portion formed on the main surface of the connection conductor so as to face the semiconductor chip.
チップに対向する領域に形成された多数の凹凸を有する
面である請求項１記載の半導体装置。5. The semiconductor device according to claim 1, wherein the outflow preventing portion is a surface having a large number of irregularities formed in a region facing the semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4023192U JP2589329Y2 (en) | 1992-05-20 | 1992-05-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4023192U JP2589329Y2 (en) | 1992-05-20 | 1992-05-20 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0593038U true JPH0593038U (en) | 1993-12-17 |
| JP2589329Y2 JP2589329Y2 (en) | 1999-01-27 |
Family
ID=12574961
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4023192U Expired - Fee Related JP2589329Y2 (en) | 1992-05-20 | 1992-05-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2589329Y2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005260181A (en) * | 2004-03-15 | 2005-09-22 | Hitachi Ltd | Resin-sealed semiconductor device and manufacturing method thereof |
| JP2014131076A (en) * | 2014-03-07 | 2014-07-10 | Toshiba Corp | Semiconductor element |
-
1992
- 1992-05-20 JP JP4023192U patent/JP2589329Y2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005260181A (en) * | 2004-03-15 | 2005-09-22 | Hitachi Ltd | Resin-sealed semiconductor device and manufacturing method thereof |
| JP2014131076A (en) * | 2014-03-07 | 2014-07-10 | Toshiba Corp | Semiconductor element |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2589329Y2 (en) | 1999-01-27 |
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