JPH059191U - Switching circuit - Google Patents
Switching circuitInfo
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- JPH059191U JPH059191U JP5417891U JP5417891U JPH059191U JP H059191 U JPH059191 U JP H059191U JP 5417891 U JP5417891 U JP 5417891U JP 5417891 U JP5417891 U JP 5417891U JP H059191 U JPH059191 U JP H059191U
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- conductor
- phase
- semiconductor switch
- terminal
- stack
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Abstract
(57)【要約】
【目的】組立，分解等の作業性を向上させ、かつ良好な
パルス発生特性が得られるようにする。
【構成】放熱フィン６に半導体スイッチ４ｂ（Ｘ相），
４ｃ（Ｖ相），４ｄ（Ｙ相），４ａ（Ｕ相）の順に上下
方向に沿って横向きに取付けてスタック11を構成し、こ
のスタック11の下方にヒューズ３，コンデンサ２を配置
する。半導体スイッチ４ａと４ｃのコレクタ端子に接続
するＰ導体12ｃ、半導体スイッチ４ｂと４ｄのエミッタ
端子に接続するＮ導体13ｂ、半導体スイッチ４ａのエミ
ッタ端子と半導体スイッチ４ｂのコレクタ端子に接続す
るＲ導体17ｂ、半導体スイッチ４ｃのエミッタ端子と半
導体スイッチ４ｄのコレクタ端子に接続するＴ導体18ｂ
を、これらの順にそれぞれ絶縁物22，23，24を挿入して
密着させ一体状に構成し、Ｐ導体12ｃとＮ導体13ｂの下
端、Ｒ導体17ｂとＴ導体18ｂの上端に接続ボルト用のＵ
状をなす切欠き部を設ける。
(57) [Summary] [Purpose] To improve workability in assembling and disassembling and to obtain good pulse generation characteristics. [Structure] The radiation fin 6 has a semiconductor switch 4b (X phase),
4c (V-phase), 4d (Y-phase), 4a (U-phase) are mounted laterally in the vertical direction to form a stack 11, and a fuse 3 and a capacitor 2 are arranged below the stack 11. A P conductor 12c connected to the collector terminals of the semiconductor switches 4a and 4c, an N conductor 13b connected to the emitter terminals of the semiconductor switches 4b and 4d, an R conductor 17b connected to the emitter terminals of the semiconductor switches 4a and the semiconductor switch 4b, T conductor 18b connected to the emitter terminal of the semiconductor switch 4c and the collector terminal of the semiconductor switch 4d
Are formed in such a manner that the insulators 22, 23, and 24 are inserted and adhered to each other in this order to form a unitary structure, and U for connecting bolts is formed at the lower ends of the P conductor 12c and the N conductor 13b and the upper ends of the R conductor 17b and the T conductor 18b.
A notch is formed.
Description
【０００１】[0001]
本考案は、半導体スイッチを用いたスイッチング回路の改良に関するものであ 。 The present invention relates to improvement of a switching circuit using a semiconductor switch.
【０００２】[0002]
半導体素子、例えばＧＴＯ等のゲート回路においては、高周波でスイッチング （オン・オフ）動作させてパルス波を得るスイッチング回路が使用される。 In a semiconductor element, for example, a gate circuit such as a GTO, a switching circuit that performs a switching (ON / OFF) operation at high frequency to obtain a pulse wave is used.
【０００３】 図７は、この種のスイッチング回路の代表的な回路構成例を示す図であり、１ は直流電源、２はコンデンサ、３は過電流保護用のヒューズ、４ａ〜４ｄは半導 体スイッチであり、Ｕ，Ｘ，Ｖ，Ｙ相を構成する。この回路は、同図に示すよう な極性で直流電源１から所定電圧がコンデンサ２に充電される。オンパルス電流 は、コンデンサ２に充電された電圧をＵ，Ｙ相の半導体スイッチ４ａ，４ｄを高 速にスイッチングし放電させることによって、Ｒ端子からＴ端子に流れる。また 、オフパルス電流は、Ｖ，Ｘ相の半導体スイッチ４ｃ，４ｂをスイッチングさせ てＴ端子からＲ端子に流れる。FIG. 7 is a diagram showing a typical circuit configuration example of this kind of switching circuit. 1 is a DC power supply, 2 is a capacitor, 3 is a fuse for overcurrent protection, and 4a to 4d are semiconductors. It is a switch and constitutes U, X, V and Y phases. In this circuit, the capacitor 2 is charged with a predetermined voltage from the DC power supply 1 with the polarity shown in the figure. The on-pulse current flows from the R terminal to the T terminal by switching the voltage charged in the capacitor 2 at high speed and discharging the U and Y phase semiconductor switches 4a and 4d. Further, the off-pulse current flows from the T terminal to the R terminal by switching the V and X phase semiconductor switches 4c and 4b.
【０００４】 このような回路においては、高速繰返しの短パルス波形が要求されるため、配 線インダクタンスを極めて小さく抑えなければならない。また、半導体スイッチ の交換保守を簡単に行えることが要求される。In such a circuit, a short pulse waveform that repeats at high speed is required, and therefore the wiring inductance must be suppressed to an extremely small value. In addition, it is required that semiconductor switches be easily replaced and maintained.
【０００５】 図８は、上記したスイッチング回路に係る具体的な構造を示す正面図であり、 図９はその側面図を示す。図８および図９において、２はコンデンサ、３は過電 流保護用のヒューズ、５は放熱フィン６に半導体スイッチ４ａ（Ｕ相）と４ｃ（ Ｖ相）および４ｂ（Ｘ相）と４ｄ（Ｙ相）をそれぞれ近接させて取付けたスタッ クで、垂直状に配置されている。また、７ａはコンデンサ２の正極端子とヒュー ズ３の一方の端子に接続されたＰ導体、７ｂはヒューズ３の他方の端子に一端を 接続され半導体スイッチ４ａ，４ｃのコレクタ端子とそれぞれＰ導体７ｃ，７ｄ を介して接続されたＰ導体、８ａはコンデンサ２の負極端子に一端を接続され半 導体スイッチ４ｂ，４ｄのエミッタ端子とそれぞれＮ導体８ｂ，８ｃを介して接 続されたＮ導体であり、Ｐ導体７ａ，７ｂとＮ導体８ａは、配線インダクタンス を小さくするために、近接させ平行状に配置して取付けられている。９ａは半導 体スイッチ４ａ，４ｂのそれぞれエミッタ端子，コレクタ端子に接続されたＲ導 体、９ｂは一端をこのＲ導体９ａに接続され他端を負荷（図示しない）に接続さ れるＲ導体、10ａは半導体スイッチ４ｃ，４ｄのそれぞれエミッタ端子，コレク タ端子に接続されたＴ導体、10ｂは一端をこのＴ導体10ａに接続され他端を負荷 （図示しない）に接続されるＴ導体であり、Ｒ導体９ｂとＴ導体10ｂは近接させ 平行状に配置して取付けられている。なお、コンデンサ２，スタック５等は、図 示しない構造物（例えば閉鎖箱）に支持される。FIG. 8 is a front view showing a specific structure of the above switching circuit, and FIG. 9 is a side view thereof. 8 and 9, 2 is a capacitor, 3 is a fuse for overcurrent protection, 5 is a radiation fin 6, and semiconductor switches 4a (U phase) and 4c (V phase) and 4b (X phase) and 4d (Y). Phases) are stacked in close proximity to each other and are arranged vertically. Further, 7a is a P conductor connected to the positive terminal of the capacitor 2 and one terminal of the fuse 3, and 7b is one end connected to the other terminal of the fuse 3 and the collector terminals of the semiconductor switches 4a and 4c and the P conductor 7c, respectively. , 7d are P conductors, and 8a is an N conductor whose one end is connected to the negative terminal of the capacitor 2 and which is connected to the emitter terminals of the semiconductor switches 4b and 4d via N conductors 8b and 8c, respectively. , P conductors 7a, 7b and N conductor 8a are arranged in parallel and attached in order to reduce the wiring inductance. Reference numeral 9a denotes an R conductor connected to the emitter terminal and collector terminal of each of the semiconductor switches 4a and 4b, and 9b denotes an R conductor having one end connected to the R conductor 9a and the other end connected to a load (not shown), Reference numeral 10a denotes a T conductor connected to the emitter terminals and collector terminals of the semiconductor switches 4c and 4d, and 10b denotes a T conductor having one end connected to the T conductor 10a and the other end connected to a load (not shown), The R conductor 9b and the T conductor 10b are arranged close to each other and mounted in parallel. The capacitors 2 and the stack 5 are supported by a structure (not shown) such as a closed box.
【０００６】 以上のように構成されたスイッチング回路においては、導体がそれぞれ単体で 分割構成されているので、半導体スイッチ４ａ〜４ｄの交換保守をする際の分解 ，再組立作業時における位置決めが面倒になり、作業性を悪くする。また、Ｐ導 体とＮ導体、Ｒ導体とＴ導体の間隔が大きく、さらに半導体スイッチ４ａ〜４ｄ の端子部分の配線が効果的なリターン配線にならないので、インダクタンスが大 きくなる。In the switching circuit configured as described above, the conductors are divided into individual units, so that the disassembling and replacement of the semiconductor switches 4a to 4d at the time of maintenance are troublesome in positioning. And deteriorate workability. In addition, since the distance between the P conductor and the N conductor and between the R conductor and the T conductor is large, and the wiring of the terminal portions of the semiconductor switches 4a to 4d does not become an effective return wiring, the inductance becomes large.
【０００７】[0007]
上述したように、従来の構成では半導体スイッチ４ａ〜４ｄの交換保守をする 際の分解，再組立時における作業性が悪いために作業所要時間を長くする欠点が あり、また、Ｐ，Ｎ，Ｒ，Ｔ導体が効果的なリターン配線を形成せずインダクタ ンスを大きくするので、所望のパルス特性が得られないという欠点があった。 As described above, the conventional configuration has a drawback in that the work time is lengthened due to poor workability in disassembling and reassembling when replacing and maintaining the semiconductor switches 4a to 4d. Since the T conductor does not form an effective return wiring and increases the inductance, there is a drawback that desired pulse characteristics cannot be obtained.
【０００８】 本考案は、上述した欠点を解消すべくなされたものであり、その目的とすると ころは組立，分解等の作業性を向上させ、かつ良好なパルス発生特性を得ること ができるスイッチング回路を提供することにある。The present invention has been made to solve the above-described drawbacks, and an object thereof is to improve switching workability such as assembly and disassembly, and to obtain a good pulse generation characteristic. To provide.
【０００９】[0009]
本考案は、充放電用コンデンサ，限流ヒューズ，放熱フィンにＵ，Ｘ，Ｖ，Ｙ 相をそれぞれ構成する半導体スイッチを取付けたスタックをほぼ直線状に上下方 向に沿って配設して成るスイッチング回路において、Ｘ相とＶ相、Ｙ相とＵ相を それぞれ隣接させると共に直線状に配置し、入力導体Ｐ，Ｎ、出力導体Ｒ，Ｔを スタックの長さ方向で分割し、かつこれらの順に絶縁物を介して密着させ一体状 に構成し、半導体スイッチの前面にほぼ中心で上下方向に沿って配置し、半導体 スイッチのそれぞれの端子に接続するようにしたものである。 The present invention comprises a stack of charge / discharge capacitors, a current limiting fuse, and a radiation fin to which semiconductor switches for forming U, X, V, and Y phases are attached, and the stack is arranged substantially linearly along the upper and lower directions. In the switching circuit, the X-phase and V-phase, and the Y-phase and U-phase are arranged adjacent to each other and arranged linearly, and the input conductors P and N and the output conductors R and T are divided in the length direction of the stack, and The semiconductor switches are arranged in close contact with each other with an insulator in between, and are integrally formed. They are arranged on the front surface of the semiconductor switch substantially vertically along the vertical direction and are connected to the respective terminals of the semiconductor switch.
【００１０】[0010]
入力導体Ｐ，Ｎ、出力導体Ｒ，Ｔが一体状に構成され、かつスタックの長さ方 向で分割されているので、半導体スイッチの前面における取外しが容易となり、 半導体スイッチの交換保守作業が容易になる。また、入力導体Ｐ，Ｎ、出力導体 Ｒ，Ｔを絶縁物を介して密着しているので、効果的なリターン配線とすることが でき、インダクタンスを可及的に小さくして、良好なパルス発生特性を得ること ができる。 Since the input conductors P and N and the output conductors R and T are integrally formed and divided in the length direction of the stack, the front surface of the semiconductor switch can be easily removed and the semiconductor switch can be easily replaced and maintained. become. In addition, since the input conductors P and N and the output conductors R and T are in close contact with each other through the insulator, it is possible to make an effective return wiring, reduce the inductance as much as possible, and generate a good pulse. The characteristics can be obtained.
【００１１】[0011]
以下、本考案の一実施例を図面を参照して説明する。図１は、本考案の一実施 例を示す正面図、図２は図１の側面図である。図１および図２において、11はス タックで、上下方向に沿って半導体スイッチ４ｂ（Ｘ相），４ｃ（Ｖ相），４ｄ （Ｙ相），４ａ（Ｕ相）を隣接させ、かつ図１に示す極性で横向きに放熱フィン ６に取付けて構成している。このスタック11の下方には、ヒューズ３，コンデン サ２が順に配置され、スタック11とコンデンサ２は図示しない構造物（例えば閉 鎖箱）に支持される。 An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a front view showing an embodiment of the present invention, and FIG. 2 is a side view of FIG. In FIGS. 1 and 2, reference numeral 11 denotes a stack, which is adjacent to the semiconductor switches 4b (X phase), 4c (V phase), 4d (Y phase), 4a (U phase) in the vertical direction, and It is constructed by horizontally attaching to the radiation fin 6 with the polarity shown in. Below the stack 11, a fuse 3 and a capacitor 2 are arranged in order, and the stack 11 and the capacitor 2 are supported by a structure (for example, a closed box) not shown.
【００１２】 コンデンサ２には、正極端子にＰ導体12ａ、負極端子にＮ導体13ａが接続され 、ヒューズ３には一方の端子にＰ導体12ａ、他方の端子にＰ導体12ｂが接続され る。これらのＰ導体12ａ，12ｂとＮ導体13ａの間には、Ｐ導体12ａ，12ｂ，Ｎ導 体13ａの幅より広い幅を有し、かつ上端がＰ導体12ｂとＮ導体13ａの上端より若 干伸び帯状とした絶縁物14を密着するように挿入する。Ｐ導体12ｂの上端にはス タッド15を固着し、Ｎ導体13ａの上端にはスタッド15と同径のスタッド16を固着 する。また、スタック11の上方には、図示しない負荷側と接続されるＲ導体17ａ とＴ導体18ａが垂直方向に沿って配置され、これらの間にはＲ導体17ａやＴ導体 18ａの幅より広い幅を有し、かつ下端がＲ導体17ａとＴ導体18ａの下端より若干 伸び帯状とした絶縁物19を密着するように挿入する。Ｒ導体17ａの下端にはスタ ッド20を固着し、Ｔ導体18ａの下端にはスタッド20と同径のスタッド21を固着す る。The capacitor 2 is connected to the P conductor 12a at the positive terminal and the N conductor 13a at the negative terminal, and the fuse 3 is connected to the P conductor 12a at one terminal and the P conductor 12b at the other terminal. Between the P conductors 12a, 12b and the N conductor 13a, there is a width wider than the width of the P conductors 12a, 12b, N conductor 13a, and the upper end is slightly shorter than the upper ends of the P conductor 12b and the N conductor 13a. The strip-shaped insulator 14 is inserted so as to be in close contact. A stud 15 is fixed to the upper end of the P conductor 12b, and a stud 16 having the same diameter as the stud 15 is fixed to the upper end of the N conductor 13a. An R conductor 17a and a T conductor 18a, which are connected to the load side (not shown), are arranged above the stack 11 along the vertical direction, and between them are wider than the widths of the R conductor 17a and the T conductor 18a. An insulator 19 having a lower end of the R conductor 17a and a lower end of the T conductor 18a having a slightly elongated shape is inserted so as to be in close contact with each other. A stud 20 is fixed to the lower end of the R conductor 17a, and a stud 21 having the same diameter as the stud 20 is fixed to the lower end of the T conductor 18a.
【００１３】 一方、半導体スイッチ４ａ〜４ｄの前側には、半導体スイッチ４ａ，４ｃのコ レクタ端子に接続するＰ導体12ｃ、半導体スイッチ４ｂ，４ｄのエミッタ端子に 接続するＮ導体13ｂ、半導体スイッチ４ａのエミッタ端子と半導体スイッチ４ｂ のコレクタ端子に接続するＲ導体17ｂ、半導体スイッチ４ｃのエミッタ端子と半 導体スイッチ４ｄのコレクタ端子に接続するＴ導体18ｂを垂直方向に沿って配置 する。ここで、Ｐ導体12ｃには、半導体スイッチ４ａと４ｃのそれぞれのコレク タ端子に接続するための接続部12ｄと12ｅが設けられ、Ｎ導体13ｂには、半導体 スイッチ４ｂと４ｄのそれぞれのエミッタ端子に接続するための接続部13ｃと13 ｄが設けられ、Ｒ導体17ｂには、半導体スイッチ４ａのエミッタ端子と半導体ス イッチ４ｂのコレクタ端子に接続するための接続部17ｃと17ｄが設けられ、Ｔ導 体18ｂには、半導体スイッチ４ｃのエミッタ端子と半導体スイッチ４ｄのコレク タ端子に接続するための接続部18ｃと18ｄが設けられる。また、Ｐ導体12ｃとＮ 導体13ｂの間には、Ｐ導体12ｃ，Ｎ導体13ｂの幅より広い幅を有し、かつ上端が Ｐ導体12ｃの上端より若干上方に伸びると共に下端が上記した絶縁物14の上端と 当接するようにした帯状の絶縁物22を密着するように挿入し、Ｒ導体17ｂとＴ導 体18ｂの間には、Ｒ導体17ｂ，Ｔ導体18ｂの幅より広い幅を有し、かつ上端が上 記した絶縁物19の下端に当接し下端がＲ導体18ｂの下端より若干下方に伸びるよ うにした帯状の絶縁物23を密着するように挿入し、Ｒ導体17ｂとＮ導体13ｂの間 には、Ｒ導体17ｂ，Ｎ導体13ｂの幅より広い幅を有し、かつ上端がＮ導体13ｂの 上端より若干伸びると共に下端がＲ導体17ｂの下端より若干伸びるようにした絶 縁物24を密着するように挿入する。ここで、絶縁物14と22は同一厚さ、絶縁物19 と23は同一厚さとする。また、Ｐ導体12ｃは、下部をＰ導体12ｃの厚さ分だけ広 がるように折曲げると共に、図４に示すようにスタッド15が挿入可能の幅を有し 、かつ開口部25ａをスタック11側とするＵ形状の切欠き部25を設けている。Ｎ導 体13ｂも同様に、下部をＮ導体13ａの厚さ分だけ広がるように折曲げると共に、 スタッド16が挿入可能の幅を有する切欠き部25を設けている。Ｒ導体17ｂは、上 部をＲ導体17ａの厚さ分だけ広がるように折曲げると共に、図５に示すように絶 縁スタッド20が挿入可能の幅を有し、かつ開口部26ａをスタック11側とするＵ形 状の切欠き部26を設けている。Ｔ導体18ｂも同様に、上部をＲ導体17ａの厚さ分 だけ広がるように折曲げると共に、スタッド21が挿入可能の幅を有する切欠き部 26を設けている。ここで、Ｐ導体12ｃ，Ｎ導体13ｂ，Ｒ導体17ｂ，Ｔ導体18ｂ， 絶縁物22，23，24は接着剤により一体状とし、下部ではスタッド15，16とナット 27，27によりＰ導体12ｂとＮ導体13ａに接続し、上部ではスタッド20，21とナッ ト28，28によりＲ導体17ａとＴ導体18ａに接続する。On the other hand, on the front side of the semiconductor switches 4a to 4d, a P conductor 12c connected to the collector terminals of the semiconductor switches 4a and 4c, an N conductor 13b connected to the emitter terminals of the semiconductor switches 4b and 4d, and a semiconductor switch 4a. An R conductor 17b connected to the emitter terminal and the collector terminal of the semiconductor switch 4b, and a T conductor 18b connected to the emitter terminal of the semiconductor switch 4c and the collector terminal of the semiconductor switch 4d are arranged along the vertical direction. Here, the P conductor 12c is provided with connecting portions 12d and 12e for connecting to the respective collector terminals of the semiconductor switches 4a and 4c, and the N conductor 13b is provided with the emitter terminals of the semiconductor switches 4b and 4d. And the connecting portions 13c and 13d for connecting to the T conductor, and the R conductor 17b is provided with connecting portions 17c and 17d for connecting to the emitter terminal of the semiconductor switch 4a and the collector terminal of the semiconductor switch 4b. The conductor 18b is provided with connecting portions 18c and 18d for connecting to the emitter terminal of the semiconductor switch 4c and the collector terminal of the semiconductor switch 4d. In addition, the width between the P conductor 12c and the N conductor 13b is wider than that of the P conductor 12c and the N conductor 13b, and the upper end extends slightly above the upper end of the P conductor 12c and the lower end is the above-mentioned insulator. Insert a strip-shaped insulator 22 that is brought into contact with the upper end of 14 so as to be in close contact, and have a width wider than the widths of the R conductor 17b and the T conductor 18b between the R conductor 17b and the T conductor 18b. Also, a strip-shaped insulator 23 whose upper end is in contact with the lower end of the above-described insulator 19 and whose lower end extends slightly below the lower end of the R conductor 18b is inserted so as to be in close contact with each other, and the R conductor 17b and the N conductor 13b are inserted. In between, an insulator 24 having a width wider than the widths of the R conductor 17b and the N conductor 13b and having an upper end slightly extending from the upper end of the N conductor 13b and a lower end slightly extending from the lower end of the R conductor 17b. Insert so that they come into close contact. Here, the insulators 14 and 22 have the same thickness, and the insulators 19 and 23 have the same thickness. Further, the P conductor 12c is bent so that its lower portion is widened by the thickness of the P conductor 12c, has a width in which the stud 15 can be inserted, and has the opening 25a formed in the stack 11 as shown in FIG. A U-shaped notch 25 is provided on the side. Similarly, the N conductor 13b is also bent at its lower portion so as to expand by the thickness of the N conductor 13a, and is provided with a notch 25 having a width into which the stud 16 can be inserted. The R conductor 17b is bent so that its upper portion is expanded by the thickness of the R conductor 17a, has a width into which the insulating stud 20 can be inserted, and has the opening 26a on the stack 11 side as shown in FIG. A U-shaped notch 26 is provided. Similarly, the T conductor 18b is bent so that the upper portion thereof is expanded by the thickness of the R conductor 17a, and a notch 26 having a width into which the stud 21 can be inserted is provided. Here, the P conductor 12c, the N conductor 13b, the R conductor 17b, the T conductor 18b, and the insulators 22, 23 and 24 are integrally formed by an adhesive, and the studs 15 and 16 and the nuts 27 and 27 are used to form the P conductor 12b in the lower portion. It is connected to the N conductor 13a, and is connected to the R conductor 17a and the T conductor 18a by the studs 20 and 21 and the nuts 28 and 28 at the upper part.
【００１４】 なお、半導体スイッチ４ａ〜４ｄには、それぞれ一端がベース端子に接続され 、他端を正面側からリード線（図示しない）が接続可能とした端子導体29を設け ている。Each of the semiconductor switches 4a to 4d is provided with a terminal conductor 29 having one end connected to a base terminal and the other end to which a lead wire (not shown) can be connected from the front side.
【００１５】 したがって、以上のように構成することにより、図６に示すように半導体スイ ッチ４ａ〜４ｄのコレクタ端子，エミッタ端子のねじを外し、ナット27，27と28 ，28を緩めるだけで、半導体スイッチ４ａ〜４ｄの前面側の導体（絶縁物を含む ）を矢印Ｂで示すように前面側へ引抜けば取外すことができ、半導体スイッチ４ ａ〜４ｄの交換保守作業が容易となる。また、導体を絶縁物を挿入して密着して いるので、インダクタンスを大幅に低減することができる。Therefore, with the above-described configuration, as shown in FIG. 6, it is only necessary to remove the screws of the collector terminals and the emitter terminals of the semiconductor switches 4a to 4d and loosen the nuts 27, 27 and 28, 28. The conductors (including insulators) on the front side of the semiconductor switches 4a to 4d can be removed by pulling them out to the front side as shown by the arrow B, which facilitates replacement and maintenance work of the semiconductor switches 4a to 4d. Moreover, since the conductor is closely attached by inserting an insulator, the inductance can be greatly reduced.
【００１６】[0016]
【考案の効果】 以上説明したように本考案によれば、半導体スイッチの交換保守作業等で導体 の組立をするための面倒な位置決めを不要として作業を容易にすると共に、イン ダクタンスを小さくして良好なパルス発生特性を得ることができるスイッチング 回路を提供できる。As described above, according to the present invention, the troublesome positioning for assembling the conductors such as the replacement and maintenance work of the semiconductor switch is not required and the work is facilitated, and the inductance is reduced. A switching circuit that can obtain good pulse generation characteristics can be provided.
【図１】本考案の一実施例の構成を示す正面図。FIG. 1 is a front view showing the configuration of an embodiment of the present invention.
【図２】図１の側面図。FIG. 2 is a side view of FIG.
【図３】図１のＡ−Ａ断面図。3 is a sectional view taken along line AA of FIG.
【図４】本考案の一実施例におけるＰ，Ｎ導体の下端部
の詳細図。FIG. 4 is a detailed view of the lower ends of P and N conductors according to an embodiment of the present invention.
【図５】本考案の一実施例におけるＲ，Ｔ導体の上端部
の詳細図。FIG. 5 is a detailed view of the upper ends of the R and T conductors in one embodiment of the present invention.
【図６】本考案の一実施例の作用を示す説明図。FIG. 6 is an explanatory view showing the operation of one embodiment of the present invention.
【図７】本考案に関連するスイッチング回路図。FIG. 7 is a switching circuit diagram related to the present invention.
【図８】従来のスイッチング回路の正面図。FIG. 8 is a front view of a conventional switching circuit.
【図９】図８の側面図。9 is a side view of FIG.
１…直流電源、２…コンデンサ、３…ヒューズ、４ａ〜
４ｄ…半導体スイッチ、６…放熱フィン、11…スタッ
ク、12ａ，12ｂ，12ｃ…Ｐ導体、13ａ，13ｂ…Ｎ導体、
14，19，22，23，24…絶縁物、15，16，20，21…スタッ
ド、27，28…ナット、17ａ，17ｂ…Ｒ導体、18ａ，18ｂ
…Ｔ導体。1 ... DC power supply, 2 ... Capacitor, 3 ... Fuse, 4a ...
4d ... Semiconductor switch, 6 ... Radiation fin, 11 ... Stack, 12a, 12b, 12c ... P conductor, 13a, 13b ... N conductor,
14, 19, 22, 23, 24 ... Insulator, 15, 16, 20, 21 ... Stud, 27, 28 ... Nut, 17a, 17b ... R conductor, 18a, 18b
... T conductor.
Claims (1)
熱フィンにＵ，Ｘ，Ｖ，Ｙ相をそれぞれ構成する半導体
スイッチを取付けたスタックをほぼ直線状に上下方向に
沿って配設して成るスイッチング回路において、前記Ｘ
相とＶ相、Ｙ相とＵ相をそれぞれ隣接させると共に直線
状に配置し、入力導体Ｐ，Ｎ、出力導体Ｒ，Ｔを前記ス
タックの長さ方向で分割し、かつこれらの順に絶縁物を
介して密着させ一体状に構成し、前記半導体スイッチの
前面にほぼ中心で上下方向に沿って配置し、前記半導体
スイッチのそれぞれの端子に接続するようにしたことを
特徴とするスイッチング回路。[Claims for utility model registration] [Claim 1] A stack in which a semiconductor switch for forming each of U, X, V, and Y phases is attached to a charging / discharging capacitor, a current limiting fuse, and a radiating fin is substantially linear in the vertical direction. A switching circuit formed along the
Phase and V phase, Y phase and U phase are arranged adjacent to each other and arranged in a straight line, and the input conductors P and N and the output conductors R and T are divided in the length direction of the stack, and the insulators are arranged in this order. A switching circuit characterized in that it is formed in close contact with the semiconductor switch through an integral structure, and is arranged in the front surface of the semiconductor switch substantially vertically along the vertical direction, and is connected to each terminal of the semiconductor switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1991054178U JP2543166Y2 (en) | 1991-07-12 | 1991-07-12 | Power converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1991054178U JP2543166Y2 (en) | 1991-07-12 | 1991-07-12 | Power converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH059191U true JPH059191U (en) | 1993-02-05 |
| JP2543166Y2 JP2543166Y2 (en) | 1997-08-06 |
Family
ID=12963293
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1991054178U Expired - Fee Related JP2543166Y2 (en) | 1991-07-12 | 1991-07-12 | Power converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2543166Y2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002164484A (en) * | 2000-11-29 | 2002-06-07 | Hitachi Ltd | Power circuit |
| JP2015503893A (en) * | 2011-12-29 | 2015-02-02 | ゼネラル・エレクトリック・カンパニイ | Inverter and power system with fuse protection |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6240069A (en) * | 1985-08-16 | 1987-02-21 | Meidensha Electric Mfg Co Ltd | Connecting structure of voltage type inverter |
| JPH01185172A (en) * | 1988-01-18 | 1989-07-24 | Fuji Electric Co Ltd | Transistor inverter apparatus |
| JPH01194344A (en) * | 1988-01-28 | 1989-08-04 | Fuji Electric Co Ltd | Parallel connection of power transistors |
| JPH01209951A (en) * | 1988-02-18 | 1989-08-23 | Fuji Electric Co Ltd | Power conversion device |
| JP3060886U (en) * | 1999-01-19 | 1999-09-07 | 鍾李杏枝 | Thunder rotation reduction unit |
-
1991
- 1991-07-12 JP JP1991054178U patent/JP2543166Y2/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6240069A (en) * | 1985-08-16 | 1987-02-21 | Meidensha Electric Mfg Co Ltd | Connecting structure of voltage type inverter |
| JPH01185172A (en) * | 1988-01-18 | 1989-07-24 | Fuji Electric Co Ltd | Transistor inverter apparatus |
| JPH01194344A (en) * | 1988-01-28 | 1989-08-04 | Fuji Electric Co Ltd | Parallel connection of power transistors |
| JPH01209951A (en) * | 1988-02-18 | 1989-08-23 | Fuji Electric Co Ltd | Power conversion device |
| JP3060886U (en) * | 1999-01-19 | 1999-09-07 | 鍾李杏枝 | Thunder rotation reduction unit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002164484A (en) * | 2000-11-29 | 2002-06-07 | Hitachi Ltd | Power circuit |
| JP2015503893A (en) * | 2011-12-29 | 2015-02-02 | ゼネラル・エレクトリック・カンパニイ | Inverter and power system with fuse protection |
| US9553443B2 (en) | 2011-12-29 | 2017-01-24 | General Electric Company | Inverter and power system with fuse protection |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2543166Y2 (en) | 1997-08-06 |
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